dlp talks - ieee web hosting · usando célula add31 (low-power) usando célula add32 figura 6.5:...
TRANSCRIPT
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DLP Talks Distinguished Lecture Program
Ricardo Reis
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Trends on Micro and Nanoelectronics Ricardo Reis
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Part
1
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Everything ends
in a Chip
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Part
2
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65 45 28 22 ... 6
nm
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Minimal channel sizeof a transistor
~ 7000 smaller
Hair~ 14 nm
~ 100 µ
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Ricardo Reis
10 quintillions em 2009
2009
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Embedded Systems
What is “design of an embedded system”?We consider the design of a dedicated system from specification till implementation.
Optimization, specially power optimization should be done in all levels of abstraction.
Optimization means dedicated solutions“Application Specific Embedded Systems”
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A grain of rice has the price of more than a100 thousand transistorsSource: The Economist, September 6, 2010
A transistor is cheapBUT
Energy is expensive
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Power Consumption drives MOS evolution
NMOS CMOS
S
Vcc
Terra
A
B
S
Vcc
Terra
A
B
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Design Levels of Abstraction
+
Vcc
SiOSiO22
poço Npoço N
substrato Psubstrato P
NN++ NN++ PP++ PP++
Modules
System
Electrical Circuit
Logic Gates
Devices
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Challenge:Power Optimization must be done in all levels of abstraction
Power Estimation Tools for each level of abstraction
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Power consumption bigger than power dissipation capability
POWER WALL
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HardwareAccelerators
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FromDavidBrooks,Harvard,2014
APPLE82 Billions of transistors
TSMC 20 nm 89 mm2
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DARK SILICON
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ENERGY HARVESTING
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Ultra Low Power
Medical Applications
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Internal and External Noise
Aging
Variability
Radiation Effects
Some Reliability Issues
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2 Main Problems in NanoCMOS
VARIABILITY
POWER (mainly Static Power)
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VARIABILITY
VARIABILITY
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VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
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VARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITYVARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
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VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY VARIABILITY
VARIABILITY VARIABILITY VARIABILITY VARIABILITY
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VARIABILITY 60 VARIABILITY 56
VARIABILITY 12 VARIABILITY 8
4 points
4 points
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TrendsCMOS Technologies: Chanel: 5 nanometers (0.005 µm)in 2028
From Roadmap 2013 SIA - Semiconductor Industry Associationhttp://www.itrs.net/
17 metal Layers
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Trends
Structured ASICs
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Roadmap 1997Trends
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Power ReductionIleakage is become more and more
important in nano circuits
It is function of the number of transistors
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1 2 3 4 5
1 1 2 3 4 5
2 2 7 18 42 90
3 3 18 87 396 1677
4 4 42 396 3503 28435
5 5 90 1677 28435 125803
NUMBER OF STACKED PMOS TRANSISTORS
NUMBER OF STACKED NMOS TRANSISTORS
Automatic Layout Synthesis Using Complex Gates (SCCG)
E. Detjens et al., Technology Mapping in MIS, ICCAD 1987
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Using Static CMOS Complex Gates (SCCG)
with cell generation on-the-fly
Freedom to Logic Designers !!!!
A way to reduce the amount of transistors to implement a function
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A
B
C
D
A
B C
D
S
S
14 Transistors
Example
S = A + (( B + C)+D)
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A
B C D
S
S = A + (( B +C).D)
8 Transistors
A
A
B
B
C
C
D
D
S
Use of SCCG
S = A + (( B + C)+D)
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A
B C D
S
8 Transistors
Use of SCCG
A
B C
D
S
14 Transistors
S = A + (( B +C).D) S = A + (( B + C)+D)
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LESS TRANSISTORS MEANS
LESS
LEAKAGE POWER
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LESS TRANSISTORS ALSO MEANS
LESS
CONNECTIONS
green chips
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LESS CONNECTIONS ALSO MEANS
MORE SPACE BETWEEN CONNECTIONS
Reliability Increases
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POWER
Reliability
are related
&
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Trends
Years 70 : microprocessors “hand made” computer used just as graphical input
End Years 70: Random Logic ROMs, PLAs Z8000 M68000
Years 90: ROMs, PLAs Standard Cell 486, Pentium
Next Step: Standard Cell Random Logic Automatic Layout of
Cells-on-the-fly
Logic Design Evolution
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- transistor topologies- management of routing in all layers- VCC and Ground distribution - clock distribution - contacts and vias management- body ties management- transistor sizing and folding
LayoutStrategies
Many layout decisions can contribute to power reduction
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physical design as the
design of a network of transistors
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43
• ---
ASTRAN Layouts
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44
Non-Complementary Logic
LBBDD_0117177F177F7FFF (68 transistors)
Runtime: 36 min
L.S.da Rosa Jr., F.Marques, T.M.G.Cardoso, R.P.Ribas, S.S.Sapatnekar, A.I.Reis, Fast Transistor Networks from BDDs. SBCCI 2006, pp. 137-142.
ASTRAN Layouts
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Multiplier Carry-Save 4x471
Standard-cell
Compilador de PO
Figura 6.4: Leiaute de um multiplicador carry-save 4x4
Cadeia de
carry
Usando célula ADD31 (Low-Power) Usando célula ADD32
Figura 6.5: Leiaute de dois somadores Ripple-Carry de 4 bits usando células com difer-entes potências
71
Standard-cell
Compilador de PO
Figura 6.4: Leiaute de um multiplicador carry-save 4x4
Cadeia de
carry
Usando célula ADD31 (Low-Power) Usando célula ADD32
Figura 6.5: Leiaute de dois somadores Ripple-Carry de 4 bits usando células com difer-entes potências
Standard Cell (Vendor Flow)
Generated with our Data Path Compiler
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Multiplier Carry-Save 4x4
Standard Cell Cell Compiler Gain(%)
Number of Cells 52 28 46
Number of Transistors 634 376 59.3
Area (µm2) 6716 5070 24.5
Delay (ps) 2174 1896 12.8
Power (mW) 6.45 3.97 61.55
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ASTRAN
•65 nm
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Regular Layouts Adder
Mux
Register
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Trends
H&S Codesign
Embeddedsystems
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PowerPC 750
+ CACHEMemory
6.35 Millions de Transistors67 mm2
1997
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MultiCPU Intel® Core™ i7 Nehalem200845nm metal gate
732 M Transistors 263 mm2
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Intel® Core™ i7 -3920 (third generation)1,4 Billions Transistors in 160mm2
April 2012
22 nm technology4 cores
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Intel® Xeon® E7-8800/4800/2800513 mm2 with 2,6 billions transistors. 32 nm. 10 cores
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Intel Teraflops Research Chip com 80 cores
MultiCPU
100 million transistors
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Trends
SOC Systems on a chip
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Trends
NOC Network on a chip
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Trends
Reconfigurable Architectures
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Trends
Test
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3D Circuits
source: www.ziptronix.com
tier 2
Oxide
Stacking of several chips
3D-Vias
tier 1
Slide by Sandro Sawicki
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3D Design Methologies
Analog
RF
Memory
Processor
Processor
Memory
Memory
Memory
3D chips
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3D Circuits
45nm Technology Stacked on 130nm Interposer and Packaged Courtesy of STMicroelectronics
Source: 3D integration process flow for set-top box application: description of technology and electrical results. S. Cheramy, EMPC 2009
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Ricardo Reis
Tendências
CMOS Integrated Silicon Nanophotonics
Optical Connections source: IBM
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Trends
Tolerance to
RadiationEffects
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Single Event Effect (SEE)The SEE genera+on mechanism
Thiago Assis
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65
NanoSatC-BR1
UFRGS UFSM
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AgingCell-‐internal EM – INV_X4 (45nm NANGATE)
(NANGATE, 2011)
Electromigration
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Cell-‐internal EM – INV_X4 (45nm NANGATE)
J is 2.43X larger and the lifetime is 2.78X smaller (22nm technology)
AgingElectromigration
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Trends
Microsystems
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Trends
Stretchable Silicon
Wearable Computing
From: Technology Review MIT March/April 2006
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Trendsnew transistors
FinFETsFin-‐type DG-‐FET
The chanel is not anymore planar, but ver5cal
FDSoI
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Beyond CMOS
With CMOS
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Source: ITRS2009, Original Source P.Kim, Columbia University
Carbon-based Nanoelectronics
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broadband frequency mixer operating at frequencies up to 10 gigahertz
source: IBM
Graphenethe thinnest electronic material consisting of a single layer of carbon atoms
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Quantum Circuits
eight-qubit unit cell
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Quantum Circuits
D-Wave's 512-qubit chip, code-named Vesuvius. The white square on the right contains the quantum goodness.
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Factory Integration
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Foundry IBM
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Fonte: Intel
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Visualization Tools
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More on colors…
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Placement using PlaceDL
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Placement of the IBM18 circuit using UFRGS tools > 200 thousand logic cells
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Placement
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Routing Colors IBM1
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Routing Colors IBM18
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A Tool to Simulate Optical Lithography
in NanoCMOs
Tania Mara Ferla, Guilherme Flach, Ricardo ReisI2MTC2014
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A Problem in NanoCMOs
Technology Scaling
Why optical lithography is an issue? Lost of resolution in nanometric technologies.
… and the technology node is at 14nm !
Lithography Systems Evolution did not followed the technology scaling
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Diffraction Problem: Some solutions...
Improvements in optical lithography systemExample: reduction of the wavelength
RET (resolution enhancement techniques):→ DPL / MPL (multiple and double patterning lithography)→ RDR (Restricted Design Rules)→ OPC (Optical Proximity Correction)→ Regular Layout
Li-‐Da Huang, 2004
Other Lithography Technologies under development: Extreme Ultra-‐Violet Lithography (EUV) E-‐bream direct-‐write (EBDW) Directed self-‐assembly (DSA)
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Lithux
Mask Intensity Map Printing Pattern
EDA tool for Lithography Simulation
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MULTIPLE PATTERNING
source: Mentor Graphics
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EDA Tools Running
on FPGAs
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Conclusions
IC design qualitydepends on the quality of the tools
more &
more
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Conclusions
Application Specific Embedded Systems
more &
more
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Conclusions
PowerOptimizationin all abstraction levels
more &
moregreen chips
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Low PowerReliability
Health Specs
Conclusions
Dedicated Chips
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keyword in Nanoelectronics
OPTIMIZATION
Conclusions
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Everything finishes
in aChip
more &
more
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Trends on Micro and Nanoelectronics Ricardo Reis
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www.inf.ufrgs.br/cassw
This year, for the first time, the workshop includes 2 poster sessions. The program will cover topics on Circuits and Systems, including but not limited to Analog and Digital Circuits, Mixed-Mode Circuits, Biomedical Electronics, Communication/RF Circuits, Wireless Sensor Networks, Nanoelectronics, Electronic Design Automation, VLSI Sys-tems and Applications, FPGA Design and Applications, Circuit Testing, Fault Tolerant Circuits.The authors must submit an A4 pdf with a copy of the proposed poster. The proceed-ings will be published in pdf with the collection of accepted posters. More information about poster guidelines are at the event website.
Important Dates
Poster submission deadline: 20 September 2015 (firm deadline)
Notification of acceptance: 27 September 2015
Publication-ready final version : 5 October 2015
General Chair Ricardo Reis
Program Chair Marcelo Johann
Poster Session Chair: Raphael Brum
Finance Chair: Gracieli Posser
Publication Chair: Carolina Metzler Web Chair: Tania Ferla
5th IEEE CASS Rio Grande do Sul WorkshopPorto Alegre, BrasilOctober 22-23, 2015
Poster Session
CALL FOR POSTERSThe IEEE Circuits and Systems Workshop will be held for the fith time in Porto Alegre on October 22-23, Thursday and Friday. It is an event intended for academic and industrial exchange between local researchers and foreign researchers. The speak-ers are renowned researchers and from institutions with significant work in the field of microelectronics. The event will last for two days and the programming will consist of a series of invited tutorials and 2 poster sessions.The Workshop Location is the Instituto de Informática of the Universidade Federal do Rio do Grande do Sul.
Some of the invited speakers are: Andrew Kahng - UCSD (USA) Gi-Joon Nam - IBM Yorktown (USA) François Rivet - IMS (France) Onur Mutlu - CMU (USA) Victor Grimblatt - Synopsys (Chile) Ricardo Jacobi - UNB (Brazil)
More details at the event webpage.
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LASCAS is the international symposium of the IEEE Circuits and Systems Society in Latin America. Its seventh edition will take place on Ingleses Beach, Florianopolis, Brazil. The city of Florianopolis, a.k.a. the magic island, is located mainly on the island of Santa Catarina. Florianopolis has also a continental part and surrounding small islands. With a population of around 500,000 people, the city is known for having a very high quality of life. The island is a delicious slice of paradise with over 520 km2 (200 sq mi) of green hills, blue lagoons and 42 white sand beaches. The fishing boats, the lace makers, the folklore, the cuisine and the colonial architecture contribute to tourism. The economy of Florianopolis is heavily based on information technology, tourism and services. Florianopolis is home to the Federal University of Santa Catarina (UFSC), one of the largest in Brazil, with over 34,500 students. During the symposium, the temperature is expected to be in the range 22 oC - 31 oC.
The symposium will cover technical novelties and tutorial overviews on circuits and systems topics including but not limited to:
Social Activities: Besides the technical program, a very entertaining social program is planned. Special tours to tourist attractions will be available to the Symposium attendees and their guests.
LASCAS 20167th IEEE Latin American Symposium on Circuits and SystemsFlorianópolis, BrazilFebruary 28-March 2, 2016
ieee-lascas.org/lascas2016/
Andreas Andreou, Johns Hopkins Univ, USA
Camera-ready: December 21, 2015
Call for Papers
The 22nd edition of the Workshop will take place at Ingleses Beach, Florianopolis, Brazil. With a population of around 500,000, the city is known for having a high quality of life. The city is located in a paradisiac island with over 520 km2 (200 sq mi) of green hills, blue lagoons and 42 white sand beaches. During the symposium, the temperature is expected to be in the range of 22 oC - 31 oC. The Iberchip workshop provides an annual forum to academic and industrial researchers from Iberoamerican countries in which to exchange experiences, share knowledge and establish relations to foster the development of activities related to the field of Microelectronics. Special emphasis is put in the improvement of education and training, and in the promotion of joint cooperative projects.
Topics of Interest
Besides the technical program, a very entertaining social program is planned. Special tours to tourist attractions will be available to the Workshop attendees and their guests.
Florianopolis, BrazilFebruary 28-March 2, 2016
UFSC, Brazil Marcio Cherem Schneider, UFSC, Brazil
Jorge Juan-Chico, Univ. Sevilla, Spain
More Information in the conference webpage.
Call for Papers
Iberchipxxii workshop ieee-lascas.org/lascas2016
IWS’2016
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ASYNC2016PORTO ALEGRE BRAZIL
May 1 to 4 2016
CALL FOR PAPERS
22nd IEEE International Symposium on Asynchronous Circuits and Systems
www.asyncsymposium.org
A large number of VLSI chips and digital systems designs contain multiple, interacting timing domains. The resulting asynchrony is both an opportunity and a challenge for design, validation, and test. The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design.
REGULAR PAPERSAuthors are invited to submit papers on any aspect of asynchronous design topics ranging fromdesign, synthesis, and test, to asynchronous applications in system-level integration and emerging computing technologies. Topics of interest include:– Mixed-timed circuits, GALS systems, Network-on-Chip, and multi-chip interconnects– Elastic and latency-tolerant synchronous design– Asynchronous pipelines, architectures, CPUs, and memories– Asynchronous ultra-low power systems, energy harvesting, and mixed-signal/analogue– Asynchronous logic in power-constrained applications– Asynchronous techniques for 3D integration– Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing– CAD tools for asynchronous design, synthesis, analysis, and optimization– Formal methods for verification and performance/power analysis– Test, security, and fault tolerance– Asynchronous variability-tolerant design and design for manufacturing– Circuit designs, case studies, comparisons, and applicationsSubmissions must report original scientific work, in 6-8 pages IEEE double-column conferenceformat, with author information concealed. Accepted papers will be published in the IEEEdigital library IEEEXplore and symposium proceedings.
INDUSTRIAL PAPERSASYNC 2016 will include a special industrial workshop with papers and tutorials from industry and research on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are targeted at industry and include:– Synchronizers and clock domain crossing techniques– Techniques for combining asynchronous and clocked designs– CAD tools to integrate asynchronous circuits with clocked designs– Circuit designs, case studies, comparisons, and applicationsWe solicit 1-to-2-page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.
“Fresh Ideas” Workshop / Tools & DemosASYNC 2016 will include a special workshop to present “fresh ideas” in asynchronous design, not yet ready for publication. We solicit 1-to-2-page submissions for the workshop, which will go through a separate light-weight review process. Accepted submissions will be assembled and handed out at the workshop. We also solicit tools and demos for presentation at the conference.
Important Dates
Abstract Registration deadline: 24 Nov 2015Full paper submission deadline: 1 Dec 2015Notification of acceptance: 13 Feb 2016Workshop submission deadline: 27 Feb 2016Publication-ready final version : 6 Mar 2016
General ChairNey Calazans, PUCRS, Brazil [email protected]
Program ChairsPeter BeerelJulian Pontes
Local Chair:Fernando Moraes
Finance Chair:TBD
Publication Chair:TBD
Publicity Chair:Ricardo Reis
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Something Else
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ISPD - International Symposium on Physical Design Discrete Gate Sizing Contest 2012
organized by Intel
Second Place in one ranking (result metric)
First Place in the second ranking (that included running time)
Tiago Reimann, Guilherme Flach, Gracieli Posser
Jozeanne Belomo, Marcelo Johann, Ricardo Reis
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ISPD - International Symposium on Physical Design Discrete Gate Sizing Contest 2013
organized by Intel
First Place in the Primary Metric Ranking
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ICCAD Contest 2014 First Prize
Incremental Timing-Driven Placement
Team:Guilherme Flach, aluno de doutorado, Jucemar Monteiro, aluno de mestrado, Julia Puget, bolsista IC Mateus Fogaça, graduando na FURG,
Advisors:Marcelo JohannRicardo ReisPaulo Butzen (FURG)
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Trends on Micro and Nanoelectronics Ricardo Reis