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DLX Instruction Set DescriptionNotation

Symbol Meaningx_y bit y of x

x_y..z bits y to z of x (right justified)

x^y xx....x (x repeated y times)

x##y xy (x concatenated with y)

IR instruction register

IAR interrupt address register

PC program counter

R[rega] integer register[IR_6..10]R[regb] integer register[IR_11..15]

R[regc] integer register[IR_16..20]

F[frega] fp register[IR_6..10]

F[fregb] fp register[IR_11..15]

F[fregc] fp register[IR_16..20]

D[drega] double register[IR_6..10]

D[dregb] double register[IR_11..15]

D[dregc] double register[IR_16..20]

imm16 value of (IR_16)^16 ## IR_16..31

uimm16 value of 0^16 ## IR_16..31imm26 value of (IR_6)^6 ## IR_6..0

fps floating point status bit

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of x are allowed (double register addresses are aligned).

Single precision floating point is 32 bits and double precision

floating point is 64 bits. The exact floating point format used is

that of the machine on which the simulator is running.

The specifications for branches and jumps assume that the PC hasnot yet been incremented (for the next instruction) when the

specified actions are performed. Note that this does not represent

the actual behavior in any reasonable pipelined implementation; it

is assumed merely to simplify the description.

Memory will be stored in big endian format and all effectiveaddresses must be aligned with the data type.

InstructionsaddEx: add r1,r2,r3

R[regc]

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R[regb]

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D[dregc]

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if (F[frega] == F[fregb]) fps = 1 else fps = 0

Both are single precision floats.

gedEx: ged f8,f6

if (D[drega] >= D[dregb]) fps = 1 else fps = 0

Both are double precision floats.

gefEx: gef f3,f6

if (F[frega] >= F[fregb]) fps = 1 else fps = 0

Both are single precision floats.

gtdEx: gtd f8,f6if (D[drega] > D[dregb]) fps = 1 else fps = 0

Both are double precision floats.

gtfEx: gtf f3,f6

if (F[frega] > F[fregb]) fps = 1 else fps = 0

Both are single precision floats.

jEx: j labelPC

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R[rega] is treated as an unsigned integer. Does an absolute jump to the

target address contained in R[rega].

lbEx: lb r1,40-4(r2)

R[regb]

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lhEx: lh r1,32(r3)

R[regb]

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movfEx: movf f1,f2

F[fregc]

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F[fregc]

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address computed by adding signed integer imm16 and signed integer

R[rega].

seqEx: seq r1,r2,r3

if (R[rega] == R[regb]) R[regc]

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sgtiEx: sgti r1,r2,#-3000

if (R[rega] > imm16) R[regb]

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R[regc]

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R[regc] >R[regb])_R[regb]..31

R[rega] and R[regc] are signed integers. R[regb] is an unsigned

integer. R[rega] is arithmetically shifted right by R[regb]. The

sign bit is shifted into the most-significant bit. (Actually uses

only the five low order bits of R[regb].)

sraiEx: srai r2,r3,#5

R[regb] >uimm16)_uimm16..31

R[rega] and R[regc] are signed integers. uimm16 is an unsigned

integer. R[rega] is arithmetically shifted right by R[regb]. The

sign bit is shifted into the most-significant bit. (Actually uses

only the five low order bits of uimm16.)

srlEx: srl r15,r2,r3

R[regc] > R[regb]_27..31

All are unsigned integers. R[rega] is arithmetically shifted right

by R[regb]. Zeros are shifted into the most significant bit.

srliEx: srli r1,r2,#5

R[regb] > uimm16_27..31

All are unsigned integers. R[rega] is arithmetically shifted right

by uimm16. Zeros are shifted into the most significant bit.

subEx: sub r3,r2,r1

Ex: R[regc]

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subuEx: subu r3,r2,r1

R[regc]