PRESENTATION

DIRECT MEMORY ACCESS (DMA)

By: Digvijay Singh Karakoti

WHAT IS DMA? An important aspect of governing the Computer System

performance is the transfer of data between memory and I/O devices.

The operation involves loading programs or data files from disk into memory, saving file on disk, and accessing virtual memory pages on any secondary storage medium.

The process would be much quicker if we could bypass the CPU & transfer data directly from the I/O device to memory. Direct Memory Access does exactly that.

During DMA transfer, the CPU is idle and no control of the memory buses.

CPU bus signals for DMA transfer

BG

BR

ABUS

DBUS

WR

RD

High-Impedance (disable) when BG is enabled

CPU

BG BUS GRANT

BR BUS REQUEST

ABUS ADDRESS BUS

DBUS DATA BUS

RD READ

WR WRITE

What these symbols indicates...

BUS REQUEST (BR) The bus request input is used by the DMA controller torequest the CPU to relinquish the control of the memory buses.

BUS GRANT (BG) The CPU activates the bus grant output to inform theexternal DMA and the buses are in the high-impedance state.

DATA BUS (DBUS) It is used to store the data or information in the CPU from peripheral devices through DMA.

ADDRESS BUS (ABUS) It is used to store the base address of the datato be sent to the CPU through DMA.

READ (RD) It is used to read the data stored in the Source or from the Destination file.

WRITE (WR) It is used to write the data stored in the Source or to the Destination file.

DMA in Computer System A DMA controller implements direct memory

access in a computer system.

It connects directly to the I/O device at one end and to the system buses at the other end. It also

interacts with the CPU and I/O both via the system buses and two new direct connections.

It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may

be incorporated directly into the I/O device.

Data Transfer using DMA Controller

To transfer data from an I/O device to memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU

sets it’s Bus grant signal, BG to 1.

The CPU also tri-state it’s address, data, and control lines thus truly granting control of the system buses to the

DMA controller.

The CPU will continue to tri-state it’s outputs as long as BR is asserted.

Internal Configuration of DMA Controller

The DMA controller includes several registers :-

The DMA Address Register contains the memory address to be used in the data transfer. The CPU treats this signal as one or more output ports.

The DMA Count Register, also called Word Count Register, contains the number of bytes of data to be transferred. Like the DMA address register, it too is treated as an O/P port (with a different address) by the CPU.

The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.

The DMA Data Register are used to store intermediate data values and result when any arithmetic operation is performed.

Internal Configuration

Process of DMA Transfer

To initiate a DMA transfer, the CPU loads the address of the first memory location of the memory block (to be read

or written from) into the DMA address register.

It then writes the number of bytes to be transferred into the DMA count register in the same manner.

Finally, it writes one or more commands to the DMA control register.

SUMMARY• Advantages of DMA:– Computer system performance is improved by

direct data transfer between memory and I/O devices, bypassing the CPU.

– CPU is free to perform operations that do not use system buses.

• Disadvantages of DMA:– In case of Burst Mode data transfer, the CPU is

rendered inactive for relatively long periods of time.

– It takes more power, more money and has less speed as compared to CPU Cost of transistors.

THANK YOU