dnc, gec & non-linear interpolation

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DNC, GEC & Non-linear Interpolation [email protected] DNC, GEC & Non-linear interpolation A Review of ”A Digitally Enhanced 1.8V 15-bit 40- MSample/s CMOS Pipelined ADC”[1] & ”Background Digital Calibration Techniques for Pipelined ADC’s”[2]

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DNC, GEC & Non-linear interpolation. A Review of ”A Digitally Enhanced 1.8V 15-bit 40-MSample/s CMOS Pipelined ADC”[1] & ”Background Digital Calibration Techniques for Pipelined ADC’s”[2]. Pipelined ADC review. Non-linearities in DAC levels cause harmonic distortion - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: DNC, GEC & Non-linear interpolation

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DNC, GEC & Non-linear interpolation

A Review of ”A Digitally Enhanced 1.8V 15-bit 40-MSample/s

CMOS Pipelined ADC”[1] &

”Background Digital Calibration Techniques for Pipelined ADC’s”[2]

Page 2: DNC, GEC & Non-linear interpolation

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Pipelined ADC review

• Non-linearities in DAC levels cause harmonic distortion– Common solution: Try to randomly distribute non-

linearities in DAC so energy is spread out in the frequency spectrum

• Interstage gain errors reduce SNDR/SNR– Solution: Apply correction gain digitally

Page 3: DNC, GEC & Non-linear interpolation

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Detecting a known signal component in the output of an unknown system

Mean of td = 0

• Td with a mean of zero:– Periodic signal

• Pro: Can have a small N since power of td is evenly distributed in time

• Con: Delta function in the frequency domain

– White noise signal• Pro: Flat power density spectrum• Con: Need large N, ideally N=∞

Page 4: DNC, GEC & Non-linear interpolation

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A Digitally Enhanced 1.8V 15-bit 40-MSample/s CMOS Pipelined ADC

Page 5: DNC, GEC & Non-linear interpolation

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• Dynamic Element Matching (DEM)• DAC Noise Cancellation (DNC)• Gain Error Correction (GEC)• Bootstrapped Switches• Timing

Outline

Page 6: DNC, GEC & Non-linear interpolation

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Pipeline ADC from [1]

Page 7: DNC, GEC & Non-linear interpolation

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Dynamic Element Matching (1)

• Errors in DAC paths cause signal dependent error• Signal dependent error => Distortion

R

Vout

Bin

ary

to T

herm

omet

er

B0

B1

Iref

T = 0001 => Vout = RIref (1+ e0)

T = 1111 => Vout = RIref (4+ e0e1 e2 e3 )

Vout = RIref [T0 (1+ e0) + T1 (1+ e1)+ T2 (1+ e2)+ T3 (1+ e3 )]

Page 8: DNC, GEC & Non-linear interpolation

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Dynamic Element Matching (2)

• Scrambler randomly selects a sequence of Sn such that Vout equals (1)

• The error, e, is uncorrelated with the input signal if it is done correctly

• This will effectively spread DAC noise power in the frequency spectrum

Bin

ary

to T

herm

omet

er

B0

B1

Iref

S0

S1

S2

S3

Scr

ambl

er

R

Vout

S4

S5

S6

S7

T0

T1

T2

T3

Random Sequence

(1)Vout = RIref [T0 + T1+ T2 +T3] + e

Page 9: DNC, GEC & Non-linear interpolation

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• With DEM encoder from [1] it can be shown that DAC noise inherits statistical properties of the pseudorandom sequence used in DEM

• This can be used to estimate the mismatch in the DAC paths

• Each path error is related to a specific pseduorandom sequence

DEM encoder from [1]

DAC path errors

Known sequences

Page 10: DNC, GEC & Non-linear interpolation

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DAC Noise Cancellation

• Detect presence of known pseduorandom signal, s[n], in output, u[n] + εs[n], by calculating the covariance

• Estimate DAC path error, ε, from covariance• Multiply psedurandom sequence by path error estimate and

subtract from output • Repeat for all DAC paths

u[n] + εs[n] - εs[n]

s[n]

Estimate errorε

s[n]

u[n] + εs[n]

Page 11: DNC, GEC & Non-linear interpolation

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Gain Error Calibration (GEC) from [1]

• Estimate gain error from covariance of digitized residue and pseudorandom signal

• Assuming small ε =>(1 + ε ) ≈ 1, multiply digitized residue by gain estimate and subtract from output

r[n]

Estimate error

ε

(1 + ε)

u[n]

d1[n]

d2[n]

y[n]

d1[n] = u[n] + εu[n] + εr[n]

d2[n] = εu[n] + ε2u[n] + ε2r[n] ≈ εu[n]

y[n] = u[n] + εu[n] + εr[n] - εu[n] - εr[n] = u[n]

Page 12: DNC, GEC & Non-linear interpolation

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Bootstrapped switches

• Used on continous-time input sampling switches – Increased linearity

• Used on switches connected to mid-supply or time-constant matching constrains – Reduced resistance

Page 13: DNC, GEC & Non-linear interpolation

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Timing

• First stage amplification is most important• Steal time for first stage Flash from second stage

Page 14: DNC, GEC & Non-linear interpolation

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Results from [1]

• SFDR is improved by 12dB with DNC and GEC enabled• SNDR is improved by 20dB with DNC and GEC enabled

Signal

Without calibration With calibration

Page 15: DNC, GEC & Non-linear interpolation

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Background Digital Calibration Techniques for Pipelined ADC’s

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Outline

• Error Model• Calibration Method• Non-linear Interpolation• Quantization Effects on Interpolation

Page 17: DNC, GEC & Non-linear interpolation

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Error Model

Page 18: DNC, GEC & Non-linear interpolation

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Error measurement

• Measure gain error in each stage by applying known calibration voltage, Vcal-i

1 1_ (2 ) ( (2 ) )i i

gain error i cal i offset i i cal i offset iV e V V e V V

Positive calibration voltage Negative calibration voltage

Page 19: DNC, GEC & Non-linear interpolation

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Simulation results

• Simulated performance (DNL & INL) with and without gain calibration

Page 20: DNC, GEC & Non-linear interpolation

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Non-linear Interpolation

• Uses fitting of high order polynomials to estimate missing sample.

• Uses causal and noncausal taps

Normalized coefficients

Page 21: DNC, GEC & Non-linear interpolation

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• Limits input bandwidth of converter below Nyquist

Non-linear Interpolation

Fin < ½ Nyquist Fin < Nyquist

Page 22: DNC, GEC & Non-linear interpolation

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Non-linear Interpolation

• Interpolation error depends on the number of taps• Achieve higher bandwith with a certain error by using

more taps

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Quantization Effects on Interpolation

• Quantization noise limits performance of interpolation• Each tap adds quantization noise to total noise power• Limits the number of taps

Variance vs number of taps

Page 24: DNC, GEC & Non-linear interpolation

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References

1. Eric Siragusa & Ian Galton; ”A Digitally Enhanced 1.8V 15-bit 40-MSample/s CMOS Pipelined ADC”; IEEE Journal of Solid State, Vol. 39, NO. 12, December 2004

2. Un-Ku Moon & Bang-Sup Song;” Background Digital Calibration Techniques for Pipelined ADC’s”; IEEE Transatctions on Circuits and Systems-II, Vol. 44, NO. 2, Febuary 1997