DOCUMENTATION ON NON CONSTANT VALUED RESET DESIGN

When signal is assigned to asynchronous set/reset, it may cause simulation mismatch between RTL and

Gate because after the synthesis, the signal will be changed only when the asynchronous set/reset is

active.

Warning : Referenced signal not in sensitivity list. This may cause simulation mismatches between the

original and synthesized designs. [CDFG-360]

: Signal 'i_Rst_Val' in module 'dff' in file '././dff.v' on line 9.

Warning : Accessed non-constant signal during asynchronous set or reset operation. [CDFG2G-608]

: Variable 'i_Rst_Val' in file '././dff.v' on line 12, column 7.

: This may cause simulation mismatches between the original and synthesized designs.

To eliminate the above mentioned warning we can modify the code as mentioned below: