donny domagoj cosic - division of experimental physics, ru‘er
TRANSCRIPT
Donny Domagoj Cosic Ruđer Bošković Institute
DAQ Workshop FP7 Particle Detectors Project
4.– 5.11.2011. Zagreb, Croatia
Requirements
Current Solutions
Digital FPGA Solutions
Development Process
Future Prospects
Conclusions
HV Tandem VDG 0.5 to 6.0 MV
HV Tandetron 0.1 to 1.0 MV
Microprobe ◦ Multiple Detectors
◦ Pulse Height Processing
◦ Beam Scanning (x-y)
◦ 2D Map Acquisition
◦ Time Stamping
Pulse Height Analyser
MeV SIMS ◦ Timing Analysis
◦ Multiple Stop TDC
◦ Pulse Generation
◦ Beam Scanning (x-y)
◦ 2D Map Acquisition Preamplifier
Control Circuitry
Triplet quadruple
magnetic lens Beam blanker
Sample Pulse width < 200 ns
Multi Channel Timing Analyzer / Pulse Generator
Multiple detectors acquisition
Pulse Processing with minimal dead time ◦ Pulse Shaping
◦ Pile Up Rejection
◦ Baseline Restoration
◦ Peak Detection
◦ Live Time Correction
◦ Timing Analysis / Multi TDC
Ion Beam Scanning / Pulse Generation
Motor Control
Incorporation into custom acquisition software
Upgradable
NIM Standard Components
All pulse processing done in analog domain
ADC connected to simple data relay board for computer communication
TAC CDF Timing Filter
Advantages ◦ Reduction in size (compact) ◦ Higher resolution ◦ Lower deadtime ◦ Multifunctional ◦ Upgradable ◦ Possible automation of entire acquisition process ◦ Remote acquisition
Disadvantages
◦ Signal requires prefiltering due to ADC limitations ◦ Complex design procedure (requires knowledge of
C/C++, VHDL/Verilog, Matlab) ◦ Expensive hardware and software
Xilinx Virtex 4 FPGA
14bit 105 MHz ADC (2x)
14bit 160 MHz DAC (2x)
PCI Interface
Matlab/
Simulink
Algorithm
Simulation
Xilinx ISE
Timing
Simulation
Microsoft
Visual Studios
Spectar
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Matlab / Simulink ◦ High level programming
◦ Algorithm development
◦ Compiler generates VHDL code
Ex. Pulse Shaping
Xilinx ISE ◦ Integrate Matlab/Simulink algorithms into FPGA
project
◦ Connect algorithm I/O to FPGA hardware I/O pins
◦ Timing simulation of signal flow
Xilinx ISE ◦ Integrate Matlab/Simulink algorithms into FPGA
project
◦ Connect algorithm I/O to FPGA hardware I/O pins
◦ Timing simulation of signal flow
Xilinx ISE ◦ Integrate Matlab/Simulink algorithms into FPGA
project
◦ Connect algorithm I/O to FPGA hardware I/O pins
◦ Timing simulation of signal flow
Xilinx ISE ◦ Integrate Matlab/Simulink algorithms into FPGA
project
◦ Connect algorithm I/O to FPGA hardware I/O pins
◦ Timing simulation of signal flow
Microsoft Visual Studio (Spector) ◦ Allows custom built software to communicate with
FPGA acquisition system
◦ Communication synchronization not critical due to all processing done on FPGA
◦ Acquisition software reprograms FPGA on demand
Microsoft Visual Studio (Spector) ◦ Allows custom built software to communicate with
FPGA acquisition system
◦ Communication synchronization not critical due to all processing done on FPGA
◦ Acquisition software reprograms FPGA on demand
Microsoft Visual Studio (Spector) ◦ Allows custom built software to communicate with
FPGA acquisition system
◦ Communication synchronization not critical due to all processing done on FPGA
◦ Acquisition software reprograms FPGA on demand
ADC range and speed are limited
Need to condition the input signal into the ADCs to achieve higher resolutions ◦ Pole-Zero correction
◦ High/Low pass filter
◦ Gain adjustment
◦ DC offset
ADC range and speed are limited
Need to condition the input signal into the ADCs to achieve higher resolutions ◦ Pole-Zero correction
◦ High/Low pass filter
◦ Gain adjustment
◦ DC offset
Integrate/ eliminate prefilters with higher resolution and faster ADCs
Add Ethernet interface for remote measuring
Increase amount of analog inputs
Integrate actuator control onto FPGA platform
Virtex 6 with FMC (FPGA Mezzanine Card) connector
Integrate/ eliminate prefilters with higher resolution and faster ADCs
Add Ethernet interface for remote measuring
Increase amount of analog inputs
Integrate actuator control onto FPGA platform
Virtex 6 with FMC (FPGA Mezzanine Card) connector
Integrate/ eliminate prefilters with higher resolution and faster ADCs
Add Ethernet interface for remote measuring
Increase amount of analog inputs
Integrate actuator control onto FPGA platform
Virtex 6 with FMC (FPGA Mezzanine Card) connector
Integrate/ eliminate prefilters with higher resolution and faster ADCs
Add Ethernet interface for remote measuring
Increase amount of analog inputs
Integrate actuator control onto FPGA platform
Virtex 6 with FMC (FPGA Mezzanine Card) connector
Unlike microprocessors, FPGAs have to ability to run processes in parallel achieving greater performance
Strict timing constraints allows precise data flow control and time stamping
Fast reprogramming allows for multi parameter measurements with single setup
Wide range of experiment parameters can be changed in real time
Xilinx I/O Design Flexibility with FPGA Mezzanine Card (FMC)
http://www.xilinx.com
4DSP, http://www.4dsp.com
M. Bogovac, Digital Multiparameter Data Acquisition, New detector technologies for advanced materials research using ion beam analysis
Conference (Presentation)
M. Bogovac, M. Jakšić, D. Wegrzynek, A. Markowicz, Digital pulse processor for ion beam microprobe tomography, Nucl. Instr. and Meth A. 608, (2009),
P. 157-162