001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product IntroductionRev *A Tech Lead: SKRG
High-Performance, Low-Power Synchronous SRAMsWith On-Chip ECC to Improve Reliability 1,000x
New Product Introduction:
Synchronous SRAM with On-Chip ECC
ECC = Error-Correcting Code
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Networking
The SRAMs Required by Modern Systems Must Have High Reliability
3a
Military and Avionics Signal Processing and Computing
Modern systems need error-free, high-performance Synchronous SRAMs Systems running mission-critical applications need memories with a high RTR1 and zero system errors
Data in traditional SRAMs is corrupted by Soft Errors2 caused by background radiation
Soft Errors in SRAMs cause functional failures that lead to system downtime
1 Random Transaction Rate: The maximum rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s)2 A data error that results in the state (Logic 1 or Logic 0) of SRAM memory cells being flipped3 Error-Correcting Code: A method of encoding and decoding a bit stream with extra bits to detect and correct bit errors
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Cypress Is the SRAM Market LeaderCypress is a preferred SRAM supplier to all major network equipment providers with: More than 2.7 billion cumulative units shipped
49%1 market share for Synchronous SRAM products
Cypress has the broadest Synchronous SRAM portfolio and offers:More than 2,300 Synchronous SRAM products
Standard Sync SRAMs and No Bus Latency™ (NoBL™)2 SRAMs with densities from 2Mb to 72Mb
Four generations of QDR®3 SRAMs with densities from 18Mb to 144Mb
And, now, Synchronous SRAMs with on-chip ECC and 0.01-FIT/Mb4 reliability
Cypress is the most dependable Synchronous SRAM supplier with: Lead times of ≤6 weeks with >99% on-time delivery
Multiple qualified fabs, assembly sites and test sites
Legacy product support for up to 20 years
1 2014 Gartner and WSTS market research reports estimated for Synchronous SRAM products2 A Synchronous SRAM that transfers data on the rising edge of the clock signal with either a one (Standard Sync) or zero (NoBL™) clock cycle delay between read and write operations3 Quad Data Rate: A synchronous SRAM with two ports, each of which transfers data on both the rising and falling edges of a clock signal4 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data
3b
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Terms You Will Hear Today Synchronous SRAMAn SRAM device in which read or write operations are synchronized with one or more external clocks
Standard Sync SRAM and No Bus Latency™ (NoBL™)A Synchronous SRAM that transfers data on the rising edge of the clock signal with either one (Standard Sync) or zero (NoBL) clock cycle delay between read and write operations
Flow-Through and Pipeline ModesModes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline)
Soft ErrorA data error caused by background radiation
Soft Error Rate (SER)The rate at which a device is predicted to have Soft Errors
Error-Correcting Code (ECC)Data encoded with extra “parity” bits to detect and correct bit errors
Failures-in-Time (FIT) per Megabit of Data (FIT/Mb) The projected failure rate of a device
One FIT/Mb equals one failure per billion device hours per megabit of data
Random Transaction Rate (RTR)The maximum rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s)
Memories with higher RTR enable proportionally higher processing rates
Restriction of Hazardous Substances (RoHS)A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components
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001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Standard SRAMs without ECC cannot achieve FIT rates of <10 FIT/Mb Today's Synchronous SRAMs have FIT rates of 150-1,500 FIT/Mb
Correcting Soft Errors with a system-level ECC solution forces undesirable system design trade-offsSystem-level error detection and correction increase design complexity and cycle time
These solutions require additional memory and error-correction chips, increasing board space and cost
Systems require memories with both high performance and low power consumption10-Gbps to 20-Gbps1 network switches and routers require memory solutions with RTRs of 120 MT/s to 240 MT/s, respectively
A 72Mb Standard Sync/NoBL SRAM without ECC that has an RTR of 250 MT/s consumes 1.65 W of active power
Cypress Synchronous SRAMs with on-chip ECC solves these problems:Ensures a FIT rate of <0.01 FIT/Mb that is 1,000x lower than a standard SRAM without ECC
Offers pin-to-pin compatibility with Cypress’s existing products to simplify design
Provides an RTR of 250 MT/s with an active power consumption of 1.05 W
Cypress’s Synchronous SRAMs with on-chip ECC provide low-power, error-free memory solutions for systems that require high performance and high reliability
Design Problems Engineers Face
5
1 Number of data bits transmitted or received at the network interface of a switch or router, expressed in gigabits per second (Gbps)
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Synchronous SRAM With On-Chip ECC Is a Superior Solution
Synchronous SRAM with on-chip ECC
By choosing Synchronous SRAM with on-chip ECC as your memory
solution…
To produce more reliable solutions
for critical applications.
6
ECC logic circuitry
Synchronous SRAM memory
Mitigate risks and reduce the cost of a non-ECC memory
based design…
Switches and routers
Radar and signal processing
Test equipment
Automotive
Military and aerospace systems
Additional SRAM memory for ECC
r0 r1 r2 r3 r4 r5 r6
d3d2d1
en
Close after 7 Cycles(SW)
SerialOut
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
SRAM Family Features
On-Chip ECC Yes No No
Soft Error Rate (FIT/Mb) <0.01 >150 5671
RTR (MT/s) 250 250 250
Power2 for 72Mb SRAM (mW) 1,056 1,650 1,254
Power2 for 36Mb SRAM (mW) 792 1,485 1,006
Power2 for 18Mb SRAM (mW) 660 957 891
Cypress Synchronous SRAMs WithOn-Chip ECC vs. Competition
7
CY7C14xKVE-250x IS61LPSxx-250x
1 GSI Technology application note AN10242 Maximum value at 3.3-V core voltage, +85ºC
GS86xx-250x
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Standard Syncand NoBL™
Standard Sync and NoBL™ with ECC2
QDR® -II/DDR-II
QDR-II+/ DDR-II+
QDR-II+X/ DDR-II+X
QDR-IV
Max RTR1: 250 MT/sMax BW: 18 GbpsLatency: 1 Cycle
Pipeline and Flow-through Modes
Max RTR1: 250 MT/sMax BW: 18 GbpsLatency: 1 Cycle
Pipeline and Flow-through Modes
Max RTR1: 666 MT/sMax BW: 47.9 GbpsLatency: 1.5 Cycles
CIO3 and SIO4
Max RTR1: 666 MT/sMax BW: 79.2 Gbps
Latency: 2 or 2.5 Cycles
CIO3and SIO4, ODT5
Max RTR1: 900 MT/sMax BW: 91.1 Gbps Latency: 2.5 Cycles
SIO4, ODT5
Max RTR1: 2.1 GT/sMax BW: 153.5 Gbps
Latency: 5 or 8 CyclesDual-Port Bidirectional
ODT5
Synchronous SRAM Portfolio (NDA)High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth
De
ns
ity
10
Production Development
QQYYQQYYAvailability
Sampling ConceptStatus
CY7C41xKV13144Mb; 667-1066 MHz
1.3 V; x18, x36Burst 2
CY7C147/8xB 72Mb; 133-250 MHz2.5, 3.3 V; x18, x36
CY7C144/6xA 36Mb; 133-250 MHz2.5, 3.3 V; x36, x72
CY7C137/8xD 18Mb; 100-250 MHz3.3 V; x18, x32, x36
CY7C135/6xC 9Mb; 100-250 MHz3.3 V; x18, x32, x36
Auto E7
CY7C134/2xG2,4Mb; 100-250 MHz3.3 V; x18, x32, x36
CY7C144/6xK36Mb; 133-250 MHz2.5, 3.3 V; x18, x36
CY7C137/8xK 18Mb; 100-250 MHz2.5, 3.3 V; x18, x36
CY7C161/2xKV18144Mb; 250-333 MHz
1.8 V; x9, x18, x36Burst 2, 4
CY7C141/2xKV1836Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36Burst 2, 4
CY7C131/2/9xKV1818Mb; 250-333 MHz1.8 V; x8, x18, x36
Burst 2, 4
CY7C1911xKV1818Mb; 250-333 MHz
1.8 V; x9Burst 2, 4
CY7C151/2xKV1872Mb; 250-333 MHz1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx4/5/6/7xKV18144Mb; 300-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7Cx54/5/6/7KV1872Mb; 250-550 MHz
1.8 V; x18, x36RH6; Burst 2, 4
CY7Cx24/5/6/7xKV1836Mb; 400-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7Cx14/5/6/7xKV1818Mb; 400-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7C156/7xXV1872Mb; 366-633 MHz
1.8 V; x18, x36Burst 2, 4
CY7C126/7x36Mb; 366-633 MHz
1.8 V; x18, x36Burst 2, 4
CY7C40xKV1372Mb; 667-1066 MHz
1.3 V; x18, x36Burst 2
CY7C147/8xK72Mb; 133-250 MHz
2.5, 3.3 V; x18, x36, x72
Q315
Q116
Q115
Random Transaction Rate
NEW
NEW
NEW
NEW
NEW
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Standard Sync SRAM WithOn-Chip ECC
Switches and routersRadar and signal processingTest equipmentAutomotiveMilitary and aerospace systems
Applications
Available in two modes: Pipeline and Flow-Through1
Single-cycle (SCD) and double-cycle (DCD)2 deselect optionsBus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-Correcting Code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, Restriction of Hazardous
Substances (RoHS)-compliant packages
Features
Preliminary Datasheet: Contact Sales
Collateral
Family Table
Sampling: Q1 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb)Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb)
Availability
Block Diagram
11a
Option Density MPN RTR FIT/Mb3
Standard Sync withOn-Chip ECC Pipeline
183672
MbMbMb
CY7C1370/2KCY7C1440/2KCY7C1470/2K
250 MT/s <0.01
Standard Sync withOn-Chip ECCFlow-Through
183672
MbMbMb
CY7C1371/3KCY7C1441/3KCY7C1471/3K
133 MT/s <0.01
Data Port x18, x36
x19-x21
Chip Enable
Byte WriteAddressBus
Control
Input Register
Output Register (Pipeline)
Control Logic
SRAM Array
JTAG Interface
x2
Clock
OutputEnable
ECC Encoder
ECC Decoder
1 Modes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline)2 Modes of operation in Pipeline mode where the output driver is tri-stated after either a single cycle (SCD) or dual cycle (DCD) of issuing the deselect command3 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
NoBL™ SRAM With On-Chip ECC
Switches and routersRadar and signal processingTest equipmentAutomotiveMilitary and aerospace systems
Applications
Available in two modes: Pipeline and Flow-Through1
No Bus Latency™ (NoBL) architecture for balanced read and write
Bus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-Correcting Code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, Restriction of Hazardous
Substances (RoHS)-compliant packages
Features
Preliminary Datasheet: Contact Sales
Collateral
Family Table
Sampling: Q1 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb)Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb)
Availability
Block Diagram
11b
AddressBus
Input Register
Output Register (Pipeline)
NoBLLogic
SRAM Array
JTAG Interface
Controlx2
Clock
OutputEnable
ECC Encoder
ECC Decoder
Data Port x18, x36
Chip Enable
Byte Write
Option Density MPN RTR FIT/Mb2
NoBL™ with On-Chip ECC Pipeline
183672
MbMbMb
CY7C1380/2KCY7C1460/2KCY7C1480/2K
250 MT/s <0.01
NoBL™ with On-Chip ECC Flow-Through
183672
MbMbMb
CY7C1381/3KCY7C1461/3KCY7C1481/3K
133 MT/s <0.01
1 Modes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline)2 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data
x19-x21
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
1. Visit the Cypress Synchronous SRAM with ECC web page to learn more
2. Download the Synchronous SRAM Roadmap and Synchronous SRAM with ECC Product Overview
3. Contact Sales to request a preliminary datasheet
Here’s How to Get Started
12
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
APPENDIX
15
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
36Mb Synchronous SRAM WithOn-Chip ECC Product Selector GuidePart Number Architecture Option Bus Width Max Freq Voltage Package
CY7C1440KVE33-167AXC Standard Sync Pipeline SCD1 x36 167 MHz 3.3 V TQFP
CY7C1441KVE33-133AXC Standard Sync Flow-through x36 133 MHz 3.3 V TQFP
CY7C1460KVE33-167AXI NoBL Pipeline x36 167 MHz 3.3 V TQFP
CY7C1460KVE33-200AXC NoBL Pipeline x36 200 MHz 3.3 V TQFP
CY7C1460KVE25-250AXC NoBL Pipeline x36 250 MHz 2.5 V TQFP
CY7C1460KVE25-200BZXI NoBL Pipeline x36 200 MHz 2.5 V BGA
CY7C1460KVE25-167AXC NoBL Pipeline x36 167 MHz 2.5 V TQFP
CY7C1460KVE33-167BZC NoBL Pipeline x36 167 MHz 3.3 V BGA
CY7C1462KVE33-167AXC NoBL Pipeline x18 167 MHz 3.3 V TQFP
CY7C1462KVE25-167BZI NoBL Pipeline x18 167 MHz 3.3 V BGA
16
1 Modes of operation in pipeline mode where output driver is tri-stated after one cycle (SCD) of issuing the deselect command
Synchronous SRAM with ECC Part Number Decoding
CY 7 C 14XX K VEXX XXX XX X X
Temperature Range: C = Commercial, I = Industrial
Pb Free: X = Pb Free
Package Type: BZ = 165-ball BGA, A = 100-pin TQFP
Frequency Range: XXX = 100-250 MHz
VEXX: VE33 = ECC part with 3.3-V core voltage, VE25 = ECC part with 2.5-V core voltageK = K die revision
Part Identifier = 144 x 36M Standard Sync, 146 x 36M NoBL
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
References and LinksCypress Synchronous SRAM webpage: www.cypress.com/sync_SRAMs
Synchronous SRAM with ECC web page: www.cypress.com/SyncNoBLECC
Contact Sales to request a preliminary datasheet
18
001-94587 Owner: SKRG Synchronous SRAM With On-Chip ECC New Product Introduction Rev *A Tech Lead: SKRG
Competitor
Closest equivalent: GSI GS8320Z36AGT-250VPrice: $46.201
BOM Integration
Additional SRAM for ECC: 9Mb (GS880Z36CGT-250V) is used to implement ECC scheme to store an additional 6 parity bits per 36 bits of dataValue: $16.502
Additional Value
Cooling Cost: $7.00 cooling cost/watt x 0.61-W savings GSI solution consumes 1.21 W compared to 0.60 W for Cypress’s solutionValue: $4.283
Board Space Savings: GSI GS880Z36CGT-250VValue: $0.014
$46.20
$16.50
$16.50
$4.28
$0.01
$4.29
$66.99
Competitor
Additional SRAM for ECC
BOM Integration Value
Cooling Cost
Board Space Savings
Total Additional Value
Total Value Delivered
Sync SRAM with ECC: Total Cost:
28% Total Savings:
CY7C1460KVE25-250AXC$47.965
$19.03
1 Avnet website 500+ units pricing on 09/16/142 Avnet website 1ku pricing on 09/16/143 Microsoft Data Center costs provided to Schneider Electric4 0.97-sq-cm space savings at $0.01 per sq cm = $0.015 Digikey website 1ku pricing on 09/16/14
19
36Mb SRAM With On-Chip ECCSolution Value