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A CAM-based keyword match processor architecture
Author:Long Bu, John A. Chandy *Publisher:Microelectronics Journal 37 (2006)Presenter:Han-Chen ChenDate:2009/11/18
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Outline Introduction Architecture of Keyword match
processor Performance
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Introduction Pattern match :1. Software algorithms : slow 2. FPGA Base : must be reconfigured when change
keyword sets3. CAM Base : reliance on fixed size keys.
Presents a cellular automata based design that is more space efficient and can easily handle arbitrarily sized keywords .The architecture is flexible enough to allow for ‘approximate word’ matches as well.
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Introduction
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Architecture of Keyword match processor
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Architecture of Keyword match processor
CAM and PE arrayMotomura: 4 match signals form the CAM array in a 5*3 PE array, a n-colume CAM array requires 5n/4*3 PE array
=>Waste space
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Architecture of Keyword match processor
1.if Mt(i) = 1 and PEt (i, j) = 1 thenPEt+1 (i+1, j) = 1PEt+1 (i, j+1) = 1
2.if Mt(i) ≠ 1 and PEt (i, j) = 1 thenPEt+1 (i+1, j+1)=1PEt+1 (i, j+1)=1
3.for (1 ≥ d ≤ D-j )PEt (i+d, j+d)=1
Overall:PEt+1 (i, j)= PEt (i, j-1) + PEt (i-1, j) M∙ t(i-1) +
PEt (i-1, j-1) M∙ t(i-1) + PEt+1 (i-1, j-1)
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Cycle10 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match signal
Input: CONE
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 1 0 0 0 0 0 0 0 0 0 0 0 0
Cycle2
C
0 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match signal
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 0 1 0 0 0 0 0 0 0 0 0 0 0
Cycle3
O
0 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match signal
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 0 0 1 1 0 0 0 0 0 0 0 0 0
Cycle4
N
0 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match signal
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 0 0 0 0 0 0 0 0 0 0 1 0 0
Cycle5
E
0 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match signal
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Architecture of Keyword match processor
U C O N N \0 H U S K I E S \0
0 0 0 0 0 1 0 0 0 0 0 0 0 1
Cycle6
Match signal
\0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
rule 1
rule 2
rule 3
Match distance=2 Unmatch
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Architecture of Keyword match processor
Distance decoder:WM(i) = END M(i) (PE(i, 0)+PE(i, 1)+…+PE(i, D))∙ ∙
Match position finder:Find the previous word endOutput Match Position array (size n)
0 0 0 0 0 1 0 0 0 0 0 0 0 1
0 0 0 0 1 1 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0
M(i) array
PE match array
Word Match array
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Architecture of Keyword match processor
Matched address output (MAO) logic Binary tree priority encoder structure To generate the matched address available
All need : p+q+2 cycles p: length of input stream ,q match times , 2 initial & process distance flags
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Architecture of Keyword match processor
Keyword match processor with no delimiters: add E(i) array 1:last character 0:otherwise
Subsequence keyword match:
1.if Mt(i) = 1 and PEt (i, j) = 1PEt+1 (i, j+1) = 1if(E(i) ≠ 1 ) PEt+1 (i+1, j) = 1
2.if Mt(i) ≠ 1 and PEt (i, j) = 1 PEt+1 (i, j+1)=1if(E(i) ≠ 1 ) PEt+1 (i+1, j+1)=1
3.for (1 ≥ d ≤ D-j )if(E(i+d-1) ≠ 1 ) PEt (i+d, j+d)=1
4.PEt (0,0)=1 if(E(i) = 1 )
PEt (i+1, 0)=1
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Performance•0.5μm 3-metal layer process: tCLK>tDD+tDD2MPF+tMPF =>tCLK>7.66 ns. leads to a maximum clock frequency of 130.5 MHz.Taking into account the setup times and propagation times of the registers, we have been able to comfortably run the circuit at 100 MHz. equal to 800Mb/s .• 0.1μm 3-metal layer process: 500MHZ , 4Gb/s
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Thanks for your
listening