Download - 2017 IFIP/IEEE International VLSI-SOC Conference Proposal Boston, Massachusetts USA Martin Margala
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2017 IFIP/IEEE International VLSI-SOC Conference Proposal
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Location BenefitsAttractive Location – Choice between Urban and
Resort locationTraditionally, from mid-September to mid
October very mild weatherMajor Travel Hub for International TravelMore than 100 semiconductor companies have
Massachusetts as their main East Coast US location
20 major Universities (many among the best in the world) in New England with significant VLSI related programs (more than 40 if we include NY, NJ and PA)
Full support of IEEE Boston
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Realistic GoalsIncrease # of submitted papers
by 40%Increase selectivityIncrease the # of full
registrations by 20%Increase industrial participation
and sponsorshipNew attractive student programs
– industrial tours, student competitions
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Facilities and TransportationSeveral possible hotel and
conference facilities are possible within the vicinity (25 miles) of the City of Boston, from urban to coastline (Waltham, Woburn, Cambridge, Charlestown, Lowell, Salem,…)
Easy access using local rail and bus transportation
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Potential SponsorsEDA Companies: Cadence, Mentor
GraphicsCPU/GPU Companies: Intel, AMD,
NVIDIASOC Companies: Broadcom,
Qualcomm, Cisco, OracleMixed-Signal: Analog Devices,
Maxim, Fairchild, Infineon, NXP, RFMD
Test Companies: TeradyneDefense Companies: Raytheon,
Lockheed-Martin, BAE
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TeamConference Chair - Martin Margala, UMLProgram Chair and Co-Chair - TBAPanel Chair - TBASpecial Sessions Chair - TBAFinance Chair – Robert Alongi, IEEE BostonPublication Chair - TBAPublicity Chair - Ayse K. Coskun, BUSponsorship Chair - TBALocal Arrangement – Robert Alongi, IEEE
BostonWeb Manager - TBA
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Budget - IncomeRegistration
◦Regular ($500) x 170 attendees = $85,000
◦Student ($250) x 75 attendees = $18,750
Sponsorship $15,000
Total $118,750
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Looking Forward to Seeing You In Boston, Massachusetts
Thank you