Download - 4 bit counter
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4-Bit Counter Design and Simulation using Microwind, Dsch3.0
and Spice
Mr. Nayyer Abbas Hira Shaukat 2010131
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OBJECTIVE
“The purpose of this project is to design with Microwind a 4-bit asynchronous counter with a reset function.”
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BLOCK DIAGRAM
• Transistor level
• Microwind
NOT Gate
• DSCH• Microwind
Complex Gate • DSCH• Microwind
D Latch
• By compiling earlier layouts
D-Register • Cascading D-Registers
Counter
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Design Details
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NOT Gate
• One NMOS and one PMOS is required• Gates are interconnected to do the input• Sources are interconnected to do the output
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NOT Gate (Schematic Diagram)
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NOT Gate (Microwind design)
Layout of the NOT Gate (Microwind)
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Complex Gate
• Compressed and optimized design• Error in the design of paper• Design characteristics do not need to be
followed
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Complex Gate
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Complex Gate (Schematic Diagram)
Schematic diagram of a complex gate
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Complex Gate (Microwind design)
Layout of a complex gate (Microwind)
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D Latch
• D Latch is designed using two Complex Gates and one Inverter
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D Latch (Schematic Diagram)
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D Latch (Microwind Design)
Layout of a D Latch (Microwind)
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D Register
• Master-Slave structure is chosen • 2 D Latches and a NOT Gate is used to get a
single design
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D Register (Schematic Diagram)
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D Register (Microwind Design)
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COUNTER
• 4 D Registers are cascaded • Output of previous register is given to the
clock of next register
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Counter (Schematic Diagram)
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Counter (Microwind Design)
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The End