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Intel 80286 to PentiumIntel 80286 to Pentium
Processor ArchitectureProcessor Architecture
By
Prof. Dr. Shaiq A. HaqChairman CSE Department
University of Engineering & Technology, Lahore
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Scheme of PresentationScheme of Presentation
Architecture of;
80286 Processor
80386 Processor
80486 Processor
Intel Pentium Processor
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80286 Features80286 Features
Introduced in Feb. 1982
Originally 6.0MHz, went up to 20 MHz
MIPS = 0.90 No. of Transistors = 134,000
Design Resolution (Pixel Size) = 1.5 micron
Address Bus = 24 bit (16 MB)
Data Bus = 16 bit
Register Size = 16 bit No. of Registers = 14
No. of Instructions in Instruction Set = 225 +
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80286 Features (cont.)80286 Features (cont.)
Two modes of operation;
Real Mode
Protected Mode
Introduced Memory Management Unit to
support multi tasking at the processor level. Little-Endian Architecture
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80286 Processor80286 Processor
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Flag RegistersFlag Registers
The 8086 has 9 flags, the 80286 has 11 flags, and the80386 has 13 flags. All of these flag registers include 6flags related to data conditions (sign, zero, carry, auxiliary
carry, overflow, and parity) and three flags related tomachine operations (Interrupt, Single-step and Strings).The 80286 has two additional flags: I/O Privilege and
Nested Task. The I/O Privilege uses two bits in protectedmode to determine which I/O instructions can be used, andthe nested task is used to show a link between two tasks.
The processor also includes control registers and system
address registers, debug and test registers for system anddebugging operations.
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80386 Features80386 Features
Introduced in Oct. 1985
Originally 16MHz, went up to 33 MHz
MIPS = 5.0 No. of Transistors = 275,000
Design Resolution (Pixel Size) = 1.5 micron
Address Bus = 32 bit (4 GB RAM)
Data Bus = 32 bit
Register Size = 32 bit No. of Registers = 14
No. of Instructions in Instruction Set = eq. 80286+
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80386 Features (cont.)80386 Features (cont.)
Paging Unit and Segmentation Unit tosupport Virtual Memory at the processor
level. Three Modes;
Real Mode
Protected Mode
Virtual Mode
Pipelined architecture. The 80386 was thefirst processor in the Intel family to include
parallel stages in its execution cycle.
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80386 Features (cont.)80386 Features (cont.)The six stages and the parts of the 386 processor that
carry them out:
Bus Interface Unit (BIU): accesses memory and I/O.
Code Prefetch Unit: receives machine instructions fromthe BIU and inserts them into the instruction prefetchqueue.
Instruction Decode Unit: decodes machine instructions
from the prefetch queue and translates them intomicrocode.
Execution Unit: executes the microcode instructionsproduced by the instruction decode unit.
Segment Unit: translates logical addresses to linearaddresses and performs protection checks.
Paging Unit: translates linear addresses into physical
addresses, performs page protection checks, and keepsa list of recently accessed pages.
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80386 Processor80386 Processor
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80386 Execution Sequence80386 Execution Sequence
Bus
Interface
Prefe
tchQueue
Deco
ding
Un
it
Control Unit
MicrocodeROM
MicrocodeQueue
Execu
tion
Un
it
Register
Register
Register
Register
ALU
Coprocessor
CISC Processor
In a microprogrammed CISC the processor fetches the instructions via the bus interface into aprefetch queue, which transfers them to a decoding unit. The decoding unit breaks the machineinstruction into many elementary micro-instructions and apples them to a microcode queue. Themicro-instructions are transferred from the microcode queue to the control and execution unit which
drives the ALU and the registers
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80486 Features80486 Features
Introduced in Apr. 1989
Originally 25MHz, went up to 33 MHz
MIPS = 20.0 No. of Transistors = 1.2 million
Design Resolution (Pixel Size) = 1.0 micron
Address Bus = 32 bit
Data Bus = 32 bit
Register Size = 32 bit
No. of Registers = 14
No. of Instructions in Instruction Set = i386 + i387
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80486 Features (cont.)80486 Features (cont.)
Longer Pre-Fetch Queue, 32 instead of 16 bytes
Some concepts of RISC architecture wereintroduced for the first time.
Pipelined Architecture. Decoding and execution ofup to 5 instructions could be done in parallel. Thisallowed many instructions to be implemented in
only one clock cycle. first Intel processor to integrate the floating-point
unit directly into the CPU chip.
Has 8K high-speed level-1 cache memory thatholds copies of instructions and data that have
been most recently accessed.
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80486 Simple Block Diagram80486 Simple Block Diagram
BusIn
terface
Cache(8K
bytes)
Prefetcher
(32-byte
queue)
PagingUnit
Decoding
Unit
Segmentation
Unit
ControlUnit
Registerand ALU
FloatingPoint Unit
A31-A0
D31-D0
Control andStatus Signals
i486 CPU
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80486 Processor80486 Processor
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80486 Pipeline80486 Pipeline
InstructionFetc
Dec
ode1
(memoryacces
Dec
ode2
Execution
Write-back
ADD eax,
mem32
Decode ADD,
fetch mem32
Decode ADD
(continued)
Write result
into eax
Add eax and
mem32
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
Cycle n+4
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Intel Pentium FeaturesIntel Pentium Features
Introduced in Mar. 1993 Originally 66MHz, up to 220 MHz (Pentium Pro)
MIPS = 66
No. of Transistors = 3.1 million
Design Resolution (Pixel Size) = 0.8 micron
Address Bus = 32 bit
Data Bus = 64 bit
Register Size = 32 bit No. of Registers = 16 + a set of control/test registers
No. of Instructions in Instruction Set = eq. 80486+
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Intel Pentium Features (cont.)Intel Pentium Features (cont.)
Gave about 90% improvement over 486. Superscalar design with two instruction pipelines.
Dual integer pipelines (the U-pipeline for IA-32
and the V-pipeline for simple instructions).
Short command execution, through manyhardwired instructions
Under best case conditions the Pentium cancomplete two instructions in every clock
Two separate 8K internal caches for instructionand data (the 486 had only a single cache).
The pipelined floating-point unit in Pentium
performs faster operations than i486.
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Intel Pentium Features (cont.)Intel Pentium Features (cont.)
Branch Prediction using the Branch Target Buffer(BTB). Branch prediction logic allows the Pentium
to analyze instructions that are about to be executed.
When the instructions contain a conditional branch
(in a loop or IF statement, for example), the CPU
predicts where the branch is likely to go and loadsthe instructions at the target address.
Even-parity checking is implemented for the data bus
and the internal RAM arrays (caches and TLBs).
System Management Mode (SMM)
i i ( )
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Pentium Registers(1)Pentium Registers(1)
EIP IP
31 16 15 0
FLAG
31 16 15 E0
EFLAG
AH
31 16 15 0
AL
78
BH BL
EAX
EBX
CH CLECX
DH DLEDX
SIESI
DIEDI
BPEBP
SPESP
Instruction Pointer EFLAG Register
General-Purpose Registers Segment Registers
15 0
CS
SS
DS
ES
FS
GS
i i ( )P i R i (2)
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Pentium Registers(2)Pentium Registers(2)TSS Selector
015
TR
LDTSS SelectorLDTR
TSS Base Address
031
LDT Base Address
IDT Base AddressIDTR
GDT Base AddressGDTR
TSS Limit
019
LDT Limit
IDT Limit
GDT Limit
Control Registers
31 15 016
DR7
DR6
DR5
DR4
Debug Registers
DR3
DR2
DR1
DR0
31 15 016
TR12
TR7
Test Registers
TR6
31 15 016
CR4
CR3
CR2
CR1
CR0
P i Bl k DiP i Bl k Di
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Pentium Block DiagramPentium Block Diagram
Bus Interface
TLBData Cache
8 KbytesCode Cache
8 KbytesTLB BTB
Control Unit
Prefetch Buffer
Instruction Decode
v pipeline u pipeline
Register
MicrocodeROM
Floating PointPipeline
64-bit Data bus32-bit
Address bus
Pentium
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Intel PentiumIntel Pentium
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DemandDemand--Paged Virtual MemoryPaged Virtual Memory
Demand-Paged Virtual Memory
Uses a combination of main memory
(semiconductor memory, RAM) and systemhard-disk to make it appear to applications as ifthe computer has access to a much larger mainmemory
Allows swapping of pages in and out of memory
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SummarySummary