A simple and fast tool for the modelling of
inter-symbol interference and equalization in
high-speed chip-to-chip interfaces
A. Cortiula*, M. Dazzi*♯, M. Marcon*, D. Menin*, M. Scapol*, A. Bandiziol‡,
A. Cristofoli‡, W. Grollitsch‡, R. Nonis‡, P. Palestri* * DPIA, University of Udine, Udine, Italy
♯ now with IBM Zurich, Switzerland ‡ Infineon Technologies Austria, Villach, Austria
e-mail address: [email protected]
Abstract – We describe a simulator that based on the
architecture of a specified transmission channel (microstrip
plus cables) and the main features of transmitter and
receiver (impedance, voltage swing, etc.) computes the eye
diagram and the bit-error rate of high-speed serial
interfaces. Different equalization strategies are included in
the model such as feed-forward equalization at the
transmitter, continuous-time linear equalization and
decision-feedback equalization at the receiver. A
user-friendly graphical interface has been implemented to
facilitate the use of the program in the lab for the courses of
electronics.
Keywords – Chip-to-chip communications, modelling,
equalization
I. INTRODUCTION
Due to the continuing miniaturization of CMOS devices, the number of functionalities integrated on an integrated circuit and its speed have significantly increased over the last decade. The major bottleneck is becoming the communication between different integrated circuits that requires interfaces working up to 56 Gbps with energies per bit as low as 1 pJ [1]. At those rates, inter-symbol interference (ISI) due to the dispersive nature of the channel is the main factor affecting the performance of the interface and demands for complex equalization strategies [2]. These include feed-forward equalization (FFE) at the transmitter (a FIR filter that pre-distorts the transmitted pulses in order to compensate for the distortion introduced by the channel), decision-feedback equalization (DFE) at the receiver (the sequence of received bits is used to correct the analog voltage at the input of the sampler to cancel ISI) and continuous-time linear equalization (CTLE) at the receiver (a peaking amplifier that compensates for the high frequency attenuation of the channel). The interfaces also include algorithms for clock recovery and calibration/adaptation of their parameters, resulting in very complex electronic systems. Designing such systems directly at transistor level is almost impossible so that system level models have been developed to support the design [3]-[5].
In this paper, we describe a model based on the pulse response of the channel that includes an accurate description of the microstrip and of the equalization schemes described above. An efficient algorithm is used to derive the eye diagram and the bit-error probability.
Such a tool is useful for an initial system level design of high-speed chip-to-chip interfaces in order to help selecting, e.g. the number of equalization taps, the structure of the CTLE filter and assessing the amount of jitter that can be tolerated. A graphical interface has been developed in order to be employed in the lab of a course on high-frequency electronic systems in the master degree of electronics. In fact, the topic of high-speed interfaces is becoming more and more relevant and should be covered at least at the master level. It is also a topic of interesting didactical implications since it merges know-how in signal theory, control theory, circuit design and signal propagation.
The paper proceeds as follows. The algorithms are described in section II, while the graphical interface is shown in section III. Results for a PCIe interface at 8 Gbps are reported in section IV. Conclusions are drawn in section V.
II. MODEL DESCRIPTION
The algorithm used to derive the eye diagram and the bathtub plot is briefly summarized in the following.
Its starts with a procedure to obtain the pulse response of the system, as sketched in Figure 1.
The microstrip impedance Z0(f) and the effective dielectric constant are modeled following [6][10]. These parameters are then used to derive the RLCG per-unit-length parameters r(f), l(f), c(f) and g(f), including skin effect and dielectric losses. Telegrapher’s equations are used to derive the transfer function
L
RXTX
TXRX
L
linee
efH
21
11)(
where cjgljr , L is the line length
and the TX and RX reflection coefficients are computed
relative to the frequency-dependent line impedance
0/0// / ZZZZ TXRXTXRXTXRX .
CTLE is implemented by multiplying Hline(f)
with a rational function HCTLE(f) that contains the poles
and zeros of the corresponding CTLE filter.
116 MIPRO 2019/MEET
The transmitted pulse is described as a trapezoidal pulse with Fourier transform Vpulse(f). FFE is implemented in the frequency domain by considering that a single bit results in many pulses shifted by a bit time TB and scaled by the tap weight wn. The Fourier transform of the TX pulse is thus
n
nTj
npulseTXBewfVfV
)()(
The inverse Fourier transform of
VTX(f)Hline(f)HCTLE(f) using the method in [11] gives the
pulse response hRX(t). The time t=0 is set at the maximum
of hRX(t).
DFE is modelled by subtracting to hRX(t)
rectangular pulses with amplitude equal to the tap weight
kn and duration TB, centered at t=nTB (see Figure 2). The resulting response h(t) to the trapezoidal
pulse is used to derive the eye diagram. For a given sampling time tS, the levels that can be received are all the possible combinations (with positive and negative signs) of the samples hn=h(tS+nTB), where n=0 is the main cursor and the index ranges from negative (pre-cursors) to positive (post-cursors) values [1]. To efficiently compute these levels we consider a permutation matrix similar to a truth table (where the ‘0’ are replaced by -1 due to the differential signaling employed in chip-to-chip communications). For example, for a case with one pre- and one post-cursor:
111
111
111
111
P
The product between P and hn gives all the possible
levels corresponding to the sampling time tS. By defining
voltage bins, we can create a histogram that represents
the eye corresponding to the ‘1’ bit sampled at tS. This is
denoted as eye1(V,tS). The calculation is performed for tS
ranging from –TB to +TB.
The eye for the ‘0’ bit is just the flipped version of the
one for the ‘1’: eye0(V,tS)= eye1(-V,tS).
To account for jitter, we use the simplified
approach in [12] and convolve the eyes with a Gaussian
distribution in time.
Finally, the overall eye diagram is given by
2
),(),(),( 11 SS
S
tVeyetVeyetVeye
while the bathtub (bit-error rate with threshold equal to 0) is given as
dVtVeyetBER SS 0 ),()( 1
Figure 1 Sketch of the procedure to obtain the received pulse response.
Vswing /2
time
TB
Fourier Transform
Vpulse(f)
FFE taps (Eq.2)
VTX(f) Hline(f) HCTLE(f)
microstrip geometry and parameters
Eq.1
poles/zeros of CTLE
inverse Fourier Transform
hRX(t)
r,l,g,cZRX, ZTX
hRX(t)
time
TB
t=0
DFEk1 k2
time
time
h(t)
tS
h0
h-1h1 h2
TB TB TB
TB TB
Figure 2 Procedure to derive the overall response to the transmitted
pulse by applying DFE to the received pulse.
MIPRO 2019/MEET 117
III. GRAPHICAL INTERFACE
The main window of the graphical interface is
reported in Figure 3. It allows to enter the parameters of
the model described in the previous sections. On top we
see the boxes where to type the TX and RX impedance,
on the left side the ones for the parameters of the
transmitted pulse (bitrate, swing, rise/fall time), in the
middle the microstrip parameters. Buttons allow plotting
the microstrip’s impedance and attenuation vs. frequency,
and the overall response to the transmitted pulse. It is also
possible to add to the microstrip a cable dominated by
skin effect, so that one only needs to specify the
attenuation at a given frequency (the other frequencies
will be found by extrapolation). The button
“CALCULATE” displays the eye diagram and the
bathtub plot.
The equalization parameters are entered in
separate windows. For example, the one for DFE is
shown in Figure 4. Equalization taps can be entered
manually or by emulating a fully-adaptive LMS loop with
the procedure described in [13].
IV. RESULTS
To exemplify the possible analyses that can be
performed with the model, we consider a template
differential channel consisting of two microstrips
separated enough to neglect their mutual coupling. They
have both approximately 50 impedance and both TX
and RX are matched on this value. The material
parameters are typical of PCB technology and the length
is adjusted so to have the attenuation specified in the
PCIe standard for links working at 8 Gbps [14]: 20 dB at
the Nyquist frequency of 4 GHz. The voltage swing is set
to 0.5 V.
The frequency response of the channel is plotted
in Figure 5a and shows the linear dependence with
frequency typical of PCB lines dominated by substrate
loss. The corresponding response to the transmitted pulse
is reported in Figure 5b: the high channel dispersion
results in a large number of pre- and post-cursors,
demanding equalization. In fact, the eye diagram reported
in Figure 6 (top) is essentially closed and the resulting
BER (bottom plot) is very high.
We first apply FFE using only two taps (pre- and
main-cursor), that is the simplest architecture to
implement FFE. We see in Figure 7a that this is not
enough to open the eye. When instead 4 taps are used, a
significant improvement is observed (Figure 7b),
although this requires more complex transmitter
architectures [15]. If instead we add DFE to the 2 tap
FFE, we obtain the eye in Figure 8a that is largely
improved thanks to the reduction of most of the cursors in
the transmitted pulse response (Figure 8b). Notice that the
pulse response has an amplitude of approximately 40mV
and the DFE taps are just a few mV. This means that in a
practical implementation, an amplifier should be present
before the DFE summer, also to help the slicer.
The effect of timing jitter is analyzed with the
bathtub plots in Figure 9: jitter with rms values as low as
few ps strongly enhances the BER at the center of the
eye. In this model the jitter is just an input parameter. A
model to compute the rms value based on the noise of the
oscillators and the CDR algorithm is under development.
Figure 3 Screenshot of the main window of the graphical interface.
Figure 4 Screenshot of the window to enter the DFE taps. k1, k2
and k3 are the taps (see Figure 2), while u_l and u_a are the
parameters of the LMS loop [13].
118 MIPRO 2019/MEET
V. CONCLUSION
We have presented a model to evaluate the performance of high-speed chip-to-chip communication interfaces. An efficient probabilistic algorithm is used to compute the eye diagram. As other similar models presented in the literature, such an approach is a powerful alternative to time-domain simulations, that for systems working with BER as low as 10-15 require simulating a huge number of bit periods. The effect of the major equalization strategies is included in the model, so that the simulation tool can be used for system level planning of interfaces working with various standard. We reported as an example a PCIe interface working at 8 Gbps, showing
that the combination of different equalization strategies is needed to obtain a compliant bit-error-rate. A graphical interface has been developed in order to employ such a tool in the lab of the master degree in electronic engineering.
(a)
(b)
Figure 5 (a) frequency response and (b) response to the transmitted
pulse of the template channel employed in the following.
Figure 6 Eye diagram (top) and bathtub plot (bottom) for the
channel of Figure 5.
(a)
(b)
Figure 7 Eye diagrams obtained applying FFE to the channel in
Figure 5. Plot (a): w-1=-0.3, w0=0.7. Plot (b): w-1=-0.2, w0=0.65,
w1=-0.1, w2=-0.05.
(a)
(b)
Figure 8 (a) Eye diagram and (b) response to the transmitted pulse
for the channel in Figure 5 using FFE (w-1=-0.3, w0=0.7) and DFE
(k1=19mV, k2=9mV k3=5mV).
MIPRO 2019/MEET 119
ACKNOWLEDGMENT
We would like to thank prof. Luca Selmi (University of Modena and Reggio Emilia) for support.
REFERENCES
[1] T. C. Carusone, “Introduction to Digital I/O: Constraining I/O
Power Consumption in High-Performance Systems,” IEEE Solid-State Circuits Magazine, vol. 7, no. 4, pp. 14–22, Fall 2015.
[2] J. F. Bulzacchelli, “Equalization for Electrical Links: Current Design Techniques and Future Directions,” IEEE Solid-State Circuits Magazine, vol. 7, no. 4, pp. 23–31, Fall 2015
[3] A. Sanders and J. D’Ambrosia, “Designcon 2004 channel compliance testing utilizing novel statistical eye methodology,” 2004.
[4] G. Balamurugan, B. Casper, J. Jaussi, M. Mansuri, F. O’Mahony, and J. Kennedy, “Modeling and Analysis of High-Speed I/O Links,” IEEE Transactions on Advanced Packaging, vol. 32, no. 2, pp. 237–247, May 2009.
[5] D. Oh, J. Ren, and S. Chang, “Hybrid Statistical Link Simulation Technique,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 5, pp. 772–783, May 2011
[6] W. Getsinger, “Microstrip Dispersion Model,” IEEE Transactions on Microwave Theory and Techniques, vol. 21, no. 1, pp. 34–39, Jan. 1973
[7] H. Wheeler, “Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane,” IEEE Transactions on Microwave Theory and Techniques, vol. 25, no. 8, pp. 631–647, Aug. 1977.
[8] E. Denlinger, “Losses of Microstrip Lines,” IEEE Transactions on Microwave Theory and Techniques, vol. 28, no. 6, pp. 513–522, Jun. 1980.
[9] E. Hammerstad and O. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” in MTT-S International Microwave Symposium Digest, vol. 80. MTT006, 1980, pp. 407–409.
[10] M. Kirschning and R. Jansen, “Accurate model for effective dielectric constant of microstrip with validity up to millimetre-wave frequencies,” Electronics Letters, vol. 18, no. 6, p. 272, 1982.
[11] T. Brazil, “Causal-convolution – a new method for the transient analysis of linear systems at microwave frequencies,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 2, pp. 315–323, Feb.1995.
[12] V. Stojanovic and M. Horowitz, “Modeling and analysis of highspeed links,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2003,pp. 589–594.
[13] D. Menin , A. De Prà, A. Bandiziol , W. Grollitsch, R. Nonis, P. Palestri, “A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully-Adaptive Equalization in High-Speed Serial Interfaces”, submitted to IEEE Transactions on components, packaging and manufacturing technology.
[14] PCI Express® Base Specification Revision 4.0 Version 0.3, 2014.
[15] A. Bandiziol, W. Grollitsch, F. Brandonisio, R. Nonis, and P. Palestri, “Design of a 8-taps, 10Gbps transmitter for automotive microcontrollers,” in Proc. IEEE Asia–Pac. Conf. Circuits Syst. (APCCAS), 2016, pp. 321–324.
Figure 9 Bathtub plot for the channel in Figure 5 using the same
equalization parameters as in Figure 8. Different jitter rms values
are specified.
120 MIPRO 2019/MEET