A Verification Methodology for Programmable and Reconfigurable ProcessorsSven Altmann, René BeckertFraunhofer Institute for Integrated CircuitsDesign Automation Division Dresden
[email protected]@eas.iis.fraunhofer.de
Initials, Presentation Title, March 20072
Agenda
■ Introduction■ Verification Methodology
— Verification Environment— Formal Verification— Functional Verification
■ Test-bench for Programmable Processors■ Hierarchical Test-bench Concept (Demonstration)■ Pattern Integration
■ Other Applications— Partial Dynamic Reconfiguration— Distributed Emulation Runs
Initials, Presentation Title, March 20073
IntroductionFraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Karlsruhe
DarmstadtWürzburg
Jena
Stuttgart
Duisburg
Oberhausen
Nuthetal
Dortmund
Oberpfaffenhofen
München
Saarbrücken
St. Ingbert
Erfurt
Magdeburg
Halle
Dresden
Leipzig
Ilmenau
Cottbus
Braunschweig
Berlin
PotsdamTeltow
Aachen
Schmallenberg
Sankt Augustin
Erlangen
FürthNürnberg
Freising
Holzkirchen
Pfinztal
Freiburg
Efringen-Kirchen
RostockItzehoe
Hannover
Bremen
Euskirchen Chemnitz
WertheimKaiserslautern
Schkopau
Paderborn
Locations in Germany
80 Locations worldwide
about 40 in Germany
5 in USA
3 in Asia
58 Research institutes
12.400 Staff member
Budget > 1 Billion Euro(per annum)
Fraunhofer Institute for
Integrated Circuits (IIS)
IIS Design AutomationDivision
Initials, Presentation Title, March 20074
Fraunhofer Institute for Integrated Circuitsthe .mp3-maker
- Audio and Multimedia
- Imaging Systems
- Digital Broadcasting
- Embedded Communication
- IC Design
- Medical Technology
- Optical Inspection Systems
- X Ray Technology
- Training
- Virtual ASIC Foundry
CineVision2006
5000x1500 dots@25m
Digital Cinema
Initials, Presentation Title, March 20075
- Audio and Multimedia
– Music player anywhere (MP3, AAC)– Development of coding algorithms for audio
und video signals– MPEG-2/4 AAC audio coding for Japanese
HDTV-television and future UMTS-Systems– Portable MPEG-4 AVC Audio/Video-Player– Development of content based (meta data)
technologies (e.g. Audio ID)
Fraunhofer Institute for Integrated Circuitsthe .mp3-maker
Initials, Presentation Title, March 20076
– Design of complex digital circuits– RF-circuits– Mixed-Signal ICs for sensor signal
processing– Analog/digital converter– ASIC-design (XM Satellite Radio
ReceiverChip – 4th Generation)
– Multi-Project Wafer Service
- IC Design
Fraunhofer Institute for Integrated Circuitsthe .mp3-maker
Source: XM Satellite Radio
Initials, Presentation Title, March 20077
Design Automation Division Dresden
Key Aspects
Design Automation for Electronic Systems
Prototyping- Digital Broadcast (DAB,DVB, …)DAB Ensemble MultiplexerDVB Satellite Ranging SystemEmbedded SW Set-Top-Box / Terminal
IC Design and Verification- Software Defined RadioA Flexible and Programmable Multi Standard Base Band Processor- Image ProcessingA 53-GOPS Programmable Vision ProcessorFor Processing, Coding-Decoding And Synthesizing Of Images
Initials, Presentation Title, March 20078
Modeling and Simulation of Heterogeneous Systems
Design Automation Division Dresden
Key Aspects
- System level simulation - Automated model generation for multi-
physics systems- 3D system integration:
parasitics and electro-thermal analysis - dedicated design environments for
sensors and actuators- model based design of control and
adaptive signal processing- modeling, performance analysis and
optimization of wireless sensor networks
- safety in mechatronics- robust design
Initials, Presentation Title, March 20079
Simulation of thermal-electrical interactions
Design Automation Division Dresden
Key Aspects
- FEM simulation of dies, packages and stacked silicon
- model generation for thermal subsystem for SPICE, VHDL-AMS, Verilog-AMS
- electrothermal simulation- design optimization and thermal
management
Initials, Presentation Title, March 200710
Design Automation Division Dresden
Key Aspects
Modeling of Inter-Cip Vias ( ICV )
R
G L
C
x
Rk,C
k,L
k(x)
R
L
R
GL
C
R
L
Inter-Chip Vias between two chip layers
Modeling for calculation of electric and magnetic fields
Simulation model for circuit design
Initials, Presentation Title, March 200711
Design Challenges in Wireless Applications
■ flexible and programmable architectures supporting various mobile radio and WLAN standards
■ On-Chip channel en-coding / decoding and special processors for filter operations
■ Clustering of Single Instruction Multiple Data (SIMD) DSP cores
Initials, Presentation Title, March 200712
Synthesis and Verification Environment
Synthesis Environment
VHDL-Compilervcom 1
SynthesisPrecision Synthesis 1 Design-Compiler 2
VHDL-Code
VHDL-SimulationModelSim / Questa 1
Requirement Specification
Schematic EntryHDL-Designer 1
Functional TestVTrac+ 4
Intent CheckOneSpin 360™ CC 3
Coding Style CheckRegatta 4
Equivalence CheckOneSpin 360™ EC 3
Verification Environment
Property CheckOneSpin 360™ MV 3
Properties
1 Mentor Graphics2 Synopsys3 OneSpin Solutions4 Fraunhofer IIS5 The Mathworks6 Other Vendors
Test Pattern
Netlist
Semi Formal TestQuesta (SVA) 1
System Design,ReferenceSimulation
Matlab/Simulink 5
SystemCOther Simulators 6
Initials, Presentation Title, March 200713
Why Formal Verification ?
■ Large number of test pattern needed for controller design requires formal verification methods
— Using OneSpin 360™ tool suite
■ Intent Check — Checks properties using a formal algorithm
(e.g. checks correct index accessing an array)
■ Property Check — Proves properties of a component for all possible vectors
(e.g. grant expected always after 12 clock cycle)
■ Equivalence Check— Compares RTL with gate net-list
Initials, Presentation Title, March 200714
Experiences using Formal Verification
■ Use of formal verification methods for blocks with a high percentage of combinational logic and complex state machines
■ Reduces number of test significantly:
— State machine with 8 states and 32 transitions■ Proved with 18 properties – calculation time 4 min
— Combination of address space and control signals■ Theoretical: 210 * 215 * 28 * 28
■ Proved with only 3 properties !
Initials, Presentation Title, March 200715
Assertion Based Verification
■ Assertion Based Verification bridges the gap between formal and functional verification
■ OneSpin 360™ - Assertion Based Check — Generates special assertion blocks
■ Questa - Assertion Based Verification— System Verilog Assertions
Initials, Presentation Title, March 200716
Dedicated Tests for Programmable Processors
Responses
Response Comparison
References
■ Instruction sequences■ written and read to/from controllers
■ Memory access sequences■ to/from shared memory■ to/from local memory
■ Memory contents■ shared and local memory
■ Computation results■ written into FIFOs
Initials, Presentation Title, March 200717
Reference Simulation and VHDL Test-bench
VHDL test-benchMicro program
Binary code
Micro compiler
Core reference simulator
01100101010110111101011101001110
0110010101011011110101110100111011010101
Memory models
Response Comparison
FIFOs
VHDL simulation
References
Stimuli
Instructions, Parameters
Memory content
VHDL model -Core
Responses
Initials, Presentation Title, March 200718
Build up a Test-bench – Step by Step
■ Extend reference simulator— Insert special pattern output routines— Prepare micro programs (address range, …)
■ Prepare VHDL test-bench — Insert memory models— Insert special components for pattern input
■ Build up checker environment— Using Perl and Tcl for pattern matching and
test automation■ Build up regression test suite
Initials, Presentation Title, March 200719
Challenges during Verification■ Complex architectures with sub-controllers
designed by several engineers■ Data processing tasks (algorithms) are
distributed on several modules On-Chip■ Errors in modules are hardly detectable by
simulation on top level■ Re-Use of test pattern is strongly necessary
Our solution- Using hierarchical test-benches- Generation of test pattern for module verification during simulation of algorithms on top level
Initials, Presentation Title, March 200720
Generation of Module Test Pattern
■ Recording of traces in a top level test-bench
Traces
Initials, Presentation Title, March 200721
Injection of Module Test Pattern
■ Inject top level traces as stimuli into a module test-bench
Stimuli Responses
Responses
Stimuli
Responses
Initials, Presentation Title, March 200722
Requirements for Hierarchical Test-benches
■ Well defined module interface— Done by specification
■ Module interface is a pin compatible section of top level test-bench
— Done by design rules / coding style■ Efficient technology for pattern transfer
— Done by
Initials, Presentation Title, March 200723
Efficient Technology for Pattern Transfer
■ VTrac+ is an universal and efficient solution for pattern integration into VHDL simulation
— VTrac+ = Verification Trace and more— Add-on-Tool for ModelSim/Questa— Available for Solaris, Linux, Windows
■ VTrac+ enables Trace, Stimulate, and Compare signals in any design hierarchy
— Unrestricted access to VHDL signals without wiring
— Handled like a common VHDL procedure
Initials, Presentation Title, March 200724
VTrac+ - How it works
VTrac+
Control file- Control information
trace eval stimVHDL Simulation ModelSim / Questa
Signal_1 <Format>
Signal_2 <Format>
...
Pattern file- List of pattern (ASCII)
Initials, Presentation Title, March 200725
VTrac+ - Supported Data Types
— std_logic, std_logic_vector— std_ulogic, std_ulogic_vector— bit, bit_vector— integer, natural— bool— array of integer, natural, bool— string— enumeration
Initials, Presentation Title, March 200726
VTrac+ - Trace Signal Values into Files
ModelSim/Questa and VTrac+
Trace file
Control file trace sim/monitor_file.curr/clk_gen/rst %c/clk_gen/clk_300 %c 300MHz-Clock/clk_gen/int %5d /clk_gen/inta %2,6x IntegerArray/clk_gen/bool %c/clk_gen/boolvec %c /clk_gen/stlv %c Bus
# Verification Pattern generated by vtrac, called by /clk_gen,# /clk_gen/rst# | 300MHz-Clock# | | /clk_gen/int# | | | IntegerArray# | | | | /clk_gen/bool# | | | | | /clk_gen/boolvec# | | | | | | Bus# | | | | | | | 000000: X 0 1 80 0c 03 04 05 06 T TTFT XULHW-01ZXULHW-01ZX000003: X 1 2 0c 03 04 05 06 07 F TFFT 0010XX10XXU10XX10XX...
Initials, Presentation Title, March 200727
VTrac+ - Stimulate Signal Values
ModelSim/Questa and VTrac+
Trace files= Stimuli
Control files
000000: X 0 1 80 0c 03 04 05 06 T TTFT W-01ZXULHW-01ZX000003: 1 1 2 0c 03 04 05 06 80 F TFFT XX10XXU10XX10XX000006: 1 0 3 03 04 05 06 80 0c T FFFT 011010010001001000009: 0 1 4 04 05 06 80 0c 03 F FFTF 000000000000000000012: 0 0 5 05 06 80 0c 03 04 T FTFF 000000000000001000015: 0 1 6 06 80 0c 03 04 05 F TFFF 000000000000010...
■ VTrac+ drives signals to values read from trace files
Initials, Presentation Title, March 200728
VTrac+ - Compare Signal Values
ModelSim/Questa and VTrac+
Trace files= References
Control files
?
#* eval.dmp: Pattern deviation detected at 1275 ns, call 425#* file : 1 0 0101010101010111 1010101010101 F TFTF release #* model: 1 0 0101010101010101!1010101010101 F TFTF release
■ VTrac+ checks correctness of design changes automatically and reports errors
Initials, Presentation Title, March 200729
Demonstration
■ Using VTrac+
Initials, Presentation Title, March 200730
Automating Simulation
■ Using Tcl scripts in Do-files simplifies handling of ModelSim/Questa and increases verification efficiency
■ Extended ModelSim-GUI with own functions
■ Automated execution of simulator commands — add wave signals / variables— force dedicated signals / variables— ...
■ Automated execution of more complex simulation scenarios
■ Customizing simulation environment■ Automated comparison of results
Initials, Presentation Title, March 200731
Set up Regression Tests■ Regression test means the automated repetition
of test cases after every design change
Prog 1
…Prog n
Load Program Context
Run Simulation
Store Program Context
Compare resultswith references - offline
Prog 2
- Shared memory- Parameter / Instruction FiFos- Local Memory
proc run_prog1 { waves } {...loadContext prog1if $waves {
destroy .wavesetStatus all "-" reddo scr/waves.do
}setReadContentsrun 20 ussetWriteContents "HEX"storeContext prog1ckeckResults prog1
}
VTrac+ compare results with references - online
Initials, Presentation Title, March 200732
Controlling Regression Tests by Tcl
■ Extended ModelSim/Questa – GUI
■ Visualize results— Go/NoGo
Initials, Presentation Title, March 200733
Pattern Integration from External Tools■ Recording test pattern inside external tools
and devices— Matlab/Simulink, SystemC— Logic analyzer— …
External Traces (various file formats)
#include "systemc.h" #include "systemc.h" SC_MODULE(adder) { SC_MODULE(adder) {
sc_in<int> a, b; sc_in<int> a, b; sc_out<int> sum; sc_out<int> sum; void do_add() { void do_add() {
sum = a + b;sum = a + b;cout << sum; cout << sum;
} } SC_CTOR(adder) { SC_CTOR(adder) {
SC_METHOD(do_add); SC_METHOD(do_add); sensitive << a << b; sensitive << a << b;
} }; } };
Initials, Presentation Title, March 200734
Pattern Integration from External Tools
External Traces VTrac+ Stimuliconvertconvert
■ Inject pattern using VTrac+
Initials, Presentation Title, March 200735
Applications
■ Simulator Coupling for Functional Verification of pRTR-Designs
■ Assembly of Distributed Emulation Runs
Initials, Presentation Title, March 200736
• pRTR attributes
• Problems of pRTR HW Simulation
- One-on-One Simulation• Our Approach using VTrac+
- Joining the Simulation Tasks
• Implementation and Results
Overview
Initials, Presentation Title, March 200737
p - partialRT - run-timeR - reconfigurable
staticpart
dynamicpart
Modul - A
I/OI/O
I/O
I/O
I/O
I/O
pRTR system
dynamicPart
Modul - B
pRTR Attributessingle or several parts of a design
other parts stay active during exchange
different functionality of the parts
Initials, Presentation Title, March 200738
Different behavior in different times at different partitions of HW
schedule of different parts
static scheduling
dynamicscheduling
• schedule is specified by the designer,
• time and sequence are constant,
• schedule depends on internal or external signals, events, data, time,
• different parts at the same area,
Types of Scheduling
Initials, Presentation Title, March 200739
Problem:modification of the HW-behavior during a simulation-run is not possible
Common Solution:implementation of all HW-parts switched by a multiplexer
Validation:HW and runtime behavior (internal signals) are not in the correct ordervery complex in the case of >1 dynamic. part
Common pRTR-Simulation
Initials, Presentation Title, March 200740
Workflow:
• different configurations cycles are calculated in closed and compiled simulations
• several simulations are stimulated by previous simulation results or by test-bench values
• several results are joined to a final simulation of all
• the design is partitioned into several parts depending on the possible configurations
An Approach by Simulator Coupling
Initials, Presentation Title, March 200741
HW-utilization
runtime
reconfig. area
static part
A B C
static
reconfiguration cycle
static reconfig. area A
BC
reconfigurable HW Design • example: 1 static part and 3
independent configurations
• hence, 5 single simulations are necessary
Specifying of the Simulation Chain
Initials, Presentation Title, March 200742
A B C
static static static static static
HW-utilization
reconfig. area
static part
A B C
static
reconfiguration cycle
reconfig. area
static part
register transfer
VTrac+ traces the registers after the last delta-cycle and stimulates the registers of the next simulation with it
Partitioning of the Simulation
Initials, Presentation Title, March 200743
• VTrac+ is placed at the output wires of the dynamic part
• signal trace of the dynamic module activity
• values are stored in a trace file
• samples at clk/2
• In our special case, we utilize the bus macros of the FPGA implementation
VTrac+ Trace Mode
Initials, Presentation Title, March 200744
• trace file contains the logical signal values
• file can be manipulated very easily (i.e. additional reconfiguration cycles)
• signal values {0,1,U} are possible
Trace File
Initials, Presentation Title, March 200745
• VTrac+ is placed as signal driver in a new design containing the static part only
• the full functionality of the simulator can be used
• thereby, a complete and closed simulation run of the entire design is possible
• the output can be depicted in a single wave diagram
Assembly of the Several Simulations
Initials, Presentation Title, March 200746
• the design example exchange an adder by a multiplier module
• VTrac+ is placed at the Bus-Macros of the design synthesized for a Virtex I FPGA
Wave form
Example ADD/Mult Exchange
Initials, Presentation Title, March 200747
• Implemented reconfigurable data-path on a Virtex-I FPGA
• every ALU (vertical slice) is reconfigured by Mult, ADD, Sh_L, Sh_R,
• as an example application, we scheduled a sequence of the DVB-T Syndrome calculation
architecture # reconfigurations
#simulations
data path(pipelined)
data path(fully reconfigured) 544
1632
1089
3265
Results of Reed Solomon Syndrome Calculation
Initials, Presentation Title, March 200748
optimal
typical
aim
pRTR
1
gateu
t E
t
gate
1
1
A
E
Common emulator systems distribute the DuT net-list within constraint resources.
New approach:- use a third dimension (time)- design partitioning into several
HW-tasks (blue, yellow, green)- scheduling of the tasks
task 1
task 2task 3
whole designnet-list
Aims:- supply virtual emulator gates- improve the gate utilization of the
single FPGAs- reduce the number of FPGAs
Optimization of HW-emulation by pRTR Methods
Initials, Presentation Title, March 200749
Assembly of Distributed Emulation Runs
designnet-list
design partitioning
task 1 task 2
task 3 task 4
scheduling
VTrac+ assembles the several emulation parts into an entire simulation on the host system
host systemThereby, coupling of a common simulator and an emulator platform is possible
Initials, Presentation Title, March 200750
Summary
■ Formal verification methods— Reduce simulation effort significantly
■ VHDL test-bench for dedicated tests— Get golden values from a reference simulator— Compares memory contents and instruction sequences— Automated regression test using Tcl
■ Hierarchical test-bench— Transferring top level scenarios into module test-bench— VTrac+ enables efficient pattern transfer
■ Pattern integration— Interaction of tools at different design levels using VTrac+
■ Other Applications— Coupling of several simulations (pRTR-simulator)— Assembly of distributed signal sources (emulator, Co-Simulation)
Initials, Presentation Title, March 200751