Advanced VLSI Design
Unit 05: Datapath Units
Slide 2
Outline Adders Comparators Shifters Multi-input Adders Multipliers
Slide 3
Single-Bit AdditionHalf Adder Full Adder
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A B C Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Cout
out
S A B
C A B
out ( , , )
S A B C
C MAJ A B C
Slide 4
Full Adder Design Brute force implementation from eqns
out ( , , )
S A B C
C MAJ A B C
ABC
S
Cout
MA
J
ABC
A
B BB
A
CS
C
CC
B BB
A A
A B
C
B
A
CBA A B C
Cout
C
A
A
BB
Slide 5
Layout Clever layout circumvents usual line of diffusion
– Use wide transistors on critical path– Eliminate output inverters
Slide 6
Carry Propagate Adders N-bit adder called CPA
– Each sum bit depends on all previous carries– How do we compute all these carries quickly?
+
BN...1AN...1
SN...1
CinCout
11111 1111 +0000 0000
A4...1
carries
B4...1
S4...1
CinCout
00000 1111 +0000 1111
CinCout
Slide 7
Carry-Ripple Adder Simplest design: cascade full adders
– Critical path goes from Cin to Cout– Design full adder to have fast carry delay
CinCout
B1A1B2A2B3A3B4A4
S1S2S3S4
C1C2C3
Slide 8
Inversions Critical path passes through majority gate
– Built from minority + inverter– Eliminate inverter and use inverting full adder
Cout Cin
B1A1B2A2B3A3B4A4
S1S2S3S4
C1C2C3
Slide 9
Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits
– Decision based on n-bit propagate signal
Cin+
S4:1
P4:1
A4:1 B4:1
+
S8:5
P8:5
A8:5 B8:5
+
S12:9
P12:9
A12:9 B12:9
+
S16:13
P16:13
A16:13 B16:13
CoutC4
1
0
C81
0
C121
0
1
0
Slide 10
Carry-Lookahead Adder Carry-lookahead adder computes Gi:0 for many bits
in parallel.
Cin+
S4:1
G4:1P4:1
A4:1 B4:1
+
S8:5
G8:5P8:5
A8:5 B8:5
+
S12:9
G12:9P12:9
A12:9 B12:9
+
S16:13
G16:13P16:13
A16:13 B16:13
C4C8C12Cout
Slide 11
Carry-Select Adder Trick for critical paths dependent on late input X
– Precompute two possible outputs for X = 0, 1– Select proper output when X arrives
Carry-select adder precomputes n-bit sums– For both possible carries into n-bit group
Cin+
A4:1 B4:1
S4:1
C4
+
+
01
A8:5 B8:5
S8:5
C8
+
+
01
A12:9 B12:9
S12:9
C12
+
+
01
A16:13 B16:13
S16:13
Cout
0
1
0
1
0
1
Slide 12
Tree Adder If lookahead is good, lookahead across lookahead!
– Recursive lookahead gives O(log N) delay Many variations on tree adders
Slide 13
Comparators 0’s detector: A = 00…000 1’s detector: A = 11…111 Equality comparator: A = B Magnitude comparator: A < B
Slide 14
1’s & 0’s Detectors 1’s detector: N-input AND gate 0’s detector: NOTs + 1’s detector (N-input NOR)
A0
A1
A2
A3
A4
A5
A6
A7
allones
A0
A1
A2
A3
allzeros
allones
A1
A2
A3
A4
A5
A6
A7
A0
Slide 15
Equality Comparator Check if each bit is equal (XNOR, aka equality gate) 1’s detect on bitwise equality
A[0]B[0]
A = B
A[1]B[1]
A[2]B[2]
A[3]B[3]
Slide 16
Magnitude Comparator Compute B-A and look at sign B-A = B + ~A + 1 For unsigned numbers, carry out is sign bit
A0
B0
A1
B1
A2
B2
A3
B3
A = BZ
C
A B
N A B
Slide 17
Signed vs. Unsigned For signed numbers, comparison is harder
– C: carry out– Z: zero (all bits of A-B are 0)– N: negative (MSB of result)– V: overflow (inputs had different signs, output sign B)
Slide 18
Shifters Logical Shift:
– Shifts number left or right and fills with 0’s• 1011 LSR 1 = 0101 1011 LSL1 = 0110
Arithmetic Shift:– Shifts number left or right. Rt shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110 Rotate:
– Shifts number left or right and fills with lost bits• 1011 ROR1 = 1101 1011 ROL1 = 0111
Slide 19
Funnel Shifter A funnel shifter can do all six types of shifts Selects N-bit field Y from 2N-bit input
– Shift by k bits (0 k < N)
B C
offsetoffset + N-1
0N-12N-1
Y
Slide 20
Funnel Shifter Operation
Computing N-k requires an adder
Slide 21
Simplified Funnel Shifter Optimize down to 2N-1 bit input
Slide 22
Funnel Shifter Design 1 N N-input multiplexers
– Use 1-of-N hot select signals for shift amount
– nMOS pass transistor design (Vt drops!)k[1:0]
s0s1s2s3Y3
Y2
Y1
Y0
Z0Z1Z2Z3Z4
Z5
Z6
left Inverters & Decoder
Slide 23
Funnel Shifter Design 2 Log N stages of 2-input muxes
– No select decoding needed
Y3
Y2
Y1
Y0Z0
Z1
Z2
Z3
Z4
Z5
Z6
k0k1
left
Slide 24
Multi-input Adders Suppose we want to add k N-bit words
– Ex: 0001 + 0111 + 1101 + 0010 = 10111 Straightforward solution: k-1 N-input CPAs
– Large and slow
+
+
0001 0111
+
1101 0010
10101
10111
Slide 25
Carry Save Addition A full adder sums 3 inputs and produces 2 outputs
– Carry output has twice weight of sum output N full adders in parallel are called carry save adder
– Produce N sums and N carry outsZ4Y4X4
S4C4
Z3Y3X3
S3C3
Z2Y2X2
S2C2
Z1Y1X1
S1C1
XN...1 YN...1 ZN...1
SN...1CN...1
n-bit CSA
Slide 26
CSA Application Use k-2 stages of CSAs
– Keep result in carry-save redundant form Final CPA computes actual result
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
10110101_
0001 0111+1101 10110101_
XYZSC
0101_ 1011 +0010
XYZSC
ABS
Slide 27
CSA Application Use k-2 stages of CSAs
– Keep result in carry-save redundant form Final CPA computes actual result
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
10110101_
01010_ 00011
0001 0111+1101 10110101_
XYZSC
0101_ 1011 +0010 0001101010_
XYZSC
01010_+ 00011
ABS
Slide 28
CSA Application Use k-2 stages of CSAs
– Keep result in carry-save redundant form Final CPA computes actual result
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
10110101_
01010_ 00011
0001 0111+1101 10110101_
XYZSC
0101_ 1011 +0010 0001101010_
XYZSC
01010_+ 00011 10111
ABS
10111
Slide 29
Multiplication Example:
M x N-bit multiplication– Produce N M-bit partial products– Sum these to produce M+N-bit product
1100 : 1210 0101 : 510 1100 0000 1100 000000111100 : 6010
multiplier
multiplicand
partialproducts
product
Slide 30
General Form Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
Multiplier: X = (xN-1, xN-2, …, x1, x0)
Product:
1 1 1 1
0 0 0 0
2 2 2M N N M
j i i jj i i j
j i i j
P y x x y
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
y5 y4 y3 y2 y1 y0
x5 x4 x3 x2 x1 x0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p0p1p2p3p4p5p6p7p8p9p10p11
multiplier
multiplicand
partialproducts
product
Slide 31
Dot Diagram Each dot represents a bit
partial products
multiplier x
x0
x15
Slide 32
Array Multipliery0y1y2y3
x0
x1
x2
x3
p0p1p2p3p4p5p6p7
B
ASin Cin
SoutCout
BA
CinCout
Sout
Sin
=
CSAArray
CPA
critical path BA
Sout
Cout CinCout
Sout
=Cin
BA
Slide 33
Rectangular Array Squash array to fit rectangular floorplan
y0y1y2y3
x0
x1
x2
x3
p0
p1
p2
p3
p4p5p6p7
Slide 34
Fewer Partial Products Array multiplier requires N partial products If we looked at groups of r bits, we could form N/r
partial products.– Faster and smaller?– Called radix-2r encoding
Ex: r = 2: look at pairs of bits– Form partial products of 0, Y, 2Y, 3Y– First three are easy, but 3Y requires adder
Slide 35
Booth Encoding Instead of 3Y, try –Y, then increment next partial
product to add 4Y Similarly, for 2Y, try –2Y + 4Y in next partial product
Slide 36
Booth Hardware Booth encoder generates control lines for each PP
– Booth selectors choose PP bits
Mi
yj
Xi
yj-1
2Xi
PPij
BoothSelector
BoothEncoder
x2i+1
x2i
x2i-1
Slide 37
Sign Extension Partial products can be negative
– Require sign extension, which is cumbersome– High fanout on most significant bit
multiplier x
x0
x15
0
00
x-1
x16x17
ssssssssssssssss
ssssssssssssss
ssssssssssss
ssssssssss
ssssssss
ssssss
ssss
ss
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PP8
Slide 38
Simplified Sign Ext. Sign bits are either all 0’s or all 1’s
– Note that all 0’s is all 1’s + 1 in proper column– Use this to reduce loading on MSB
s111111111111111s
s1111111111111s
s11111111111s
s111111111s
s1111111s
s11111s
s111s
s1s
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PP8
Slide 39
Even Simpler Sign Ext. No need to add all the 1’s in hardware
– Precompute the answer!
ssss
ss1
ss1
ss1
ss1
ss1
ss1
ss
PP0PP1PP2PP3PP4PP5PP6PP7PP8
Slide 40
Advanced Multiplication Signed vs. unsigned inputs Higher radix Booth encoding Array vs. tree CSA networks