Building smart, adaptive and efficient Building smart, adaptive and efficient systems for networked applicationssystems for networked applications

Rajesh K. GuptaRajesh K. GuptaDepartment of Computer Science and Engg.Department of Computer Science and Engg.

University of California, San DiegoUniversity of California, San Diego

http://www-cse.ucsd.edu/~guptahttp://www-cse.ucsd.edu/~gupta

Architecting Embedded Architecting Embedded MicrosystemsMicrosystems

Courtesy: Paul Gray, UC Berkeley (ISSCC97)

1. GaAs, Si Bipolar 2. Si Bipolar, BiCMOS 3. CMOS

Semiconductor “System Semiconductor “System Chips”Chips”

• Trend 2: increasing use of “embedded intelligence”Trend 2: increasing use of “embedded intelligence”– variety of (multiple) compute engines available on-chipvariety of (multiple) compute engines available on-chip

Graphics ControllerGraphics ControllerCellphone BasebandCellphone Baseband

• Trend 3: Networking of embedded intelligenceTrend 3: Networking of embedded intelligence– multiple comm. front-ends, networking available on-chipmultiple comm. front-ends, networking available on-chip

The consequence: The consequence: – smart “spaces”, intelligent interfaces, sensor networkssmart “spaces”, intelligent interfaces, sensor networks Integrated circuit chips are driving capability increases with cost reductions.Integrated circuit chips are driving capability increases with cost reductions.

• Trend 1: Process technology migration to CMOS Trend 1: Process technology migration to CMOS – relentless digitization of signals and systemsrelentless digitization of signals and systems

Integrated Circuit & System Integrated Circuit & System DesignDesign

SYSTEMPEL2

MEMMath

RouterController

IO

Graphics

TechnologyIndependentDesign

SYSTEMPEL2

MEMMath

RouterController

IO

Graphics

TechnologyIndependentDesign

PEL2

MEMMath

RouterController

IO

Graphics

TechnologyIndependentDesign

PEL2

MEM

Controller

Router Math

IO

Graphics

SYSTEMSYSTEM--ONON--AA--CHIPCHIP

PEL2

MEM

Controller

Router Math

IO

Graphics

SYSTEMSYSTEM--ONON--AA--CHIPCHIP

PEL2

MEM

Controller

Router Math

IO

Graphics

PEL2

MEM

Controller

Router Math

IO

Graphics

SYSTEMSYSTEM--ONON--AA--CHIPCHIP

TechnologyDependentDesignIC/CHIP

TechnologyDependentDesign

TechnologyDependentDesignIC/CHIP

Silicon systems engineering: needs a framework for architectural design, subsystem tradeoffs

“Real” Component

“Virtual” Component

Board-on-chip does not work!

SOC Challenges & SOC Challenges & OpportunitiesOpportunities

• Inferior CMOS components compared to discrete Inferior CMOS components compared to discrete counterparts using bipolar, GaAs technologiescounterparts using bipolar, GaAs technologies

• Power, size, bandwidth limitations for on-chipPower, size, bandwidth limitations for on-chipNeed an extremely tight control of chip, package Need an extremely tight control of chip, package

parasitic effects on on-chip signalsparasitic effects on on-chip signals

• And yet the system-level capabilities and performance And yet the system-level capabilities and performance due todue to• architectural design that is less sensitive to architectural design that is less sensitive to

device/technology limitationsdevice/technology limitations• system optimizations that include the entire system optimizations that include the entire

software, networking (and even communications) software, networking (and even communications) stackstack

The requires ability to carry out the architectural design The requires ability to carry out the architectural design and exploration for SOCsand exploration for SOCs

Systems Engineering for Systems Engineering for SOCsSOCs

Example Problem: How to achieve high Example Problem: How to achieve high throughput in a SOC for wireless applications?throughput in a SOC for wireless applications?

• Can select a modem sub-systemCan select a modem sub-system– that packs more bits/Hz, but it will tolerate less noise and be that packs more bits/Hz, but it will tolerate less noise and be

less robust so that link throughput may not improveless robust so that link throughput may not improve

• Can increase transmit power in RF subsystem Can increase transmit power in RF subsystem – to improve robustness but this increases energy cost, to improve robustness but this increases energy cost,

reduces network capacity, and requires more expensive reduces network capacity, and requires more expensive analog circuits (power amps)analog circuits (power amps)

• Can reduce bits/frame Can reduce bits/frame – to tolerate higher bit error rates (BER) and provide more to tolerate higher bit error rates (BER) and provide more

robustness, but this may increase overhead and queuing robustness, but this may increase overhead and queuing delaysdelays

• Can increase precision in digital modem Can increase precision in digital modem – to reduce noise, but this leads to wider on-chip busses and to reduce noise, but this leads to wider on-chip busses and

more power consumptionmore power consumption The design technology must support right sub-system option and The design technology must support right sub-system option and

parametric determination.parametric determination.

MultipleAccessMultiplex

SourceCoder

SourceCoder

ChannelCoder Modulator Power

Amplifier

Radio

Channel

MultipleAccessDemultiplex

SourceDecoder

SourceDecoder

ChannelDecoder

Demodulator& Equalizer

RFFilter

So

urc

eD

esti

nat

ion

Carrier fc

Carrier fc

“Highly variable b/w”“Random & Noisy”

“Limited b/w”

“Spurious disconnections”

transmittedsymbol stream

received (corrupted)symbol stream

antenna

antenna

Platform Based DesignPlatform Based Design

• A platform is a realized A platform is a realized design patterndesign pattern– provides a well-defined abstraction of the underlying provides a well-defined abstraction of the underlying

architecture for the application developerarchitecture for the application developer– a restriction on the implementation space, captures good a restriction on the implementation space, captures good

solutionssolutions– uses components and their reuse within architectural constraintsuses components and their reuse within architectural constraints

• IP design needs a framework consisting ofIP design needs a framework consisting of– component libraries, composition glue, validation, component libraries, composition glue, validation,

synthesissynthesis– complete system simulations, composability and reusecomplete system simulations, composability and reuse

• Key elements for composabilityKey elements for composability– identification of useful models of computationidentification of useful models of computation

» FSMD, DE, DF, CSP, ..FSMD, DE, DF, CSP, ..

– a flexible, extensible language platform for capturea flexible, extensible language platform for captureComponent Composition Framework (CCF)Component Composition Framework (CCF)

ComponentIntegration, CIL

Split-Level Interface/BIDL

C++, SystemC

System designerC

ompiled

Interpreted

BALBOA Component BALBOA Component CompositionComposition

• A layered development and runtime environmentA layered development and runtime environment

– FunctionalityFunctionality: describe & synthesize: describe & synthesize– StructureStructure: capture & simulate: capture & simulate

• Use an interpreted language for Use an interpreted language for

– Architecture description Architecture description – Component integrationComponent integration

• Use compiled models for Use compiled models for

– behavioral description, simulationbehavioral description, simulation• Automatically link the two domainsAutomatically link the two domains

– through a “split-level” interfacethrough a “split-level” interface• Automatic code “wrapper” generation Automatic code “wrapper” generation

– for component reuse.for component reuse.

Software architecture that enablesSoftware architecture that enables

– composition of structural and composition of structural and functional info.functional info.

– type inference for polymorphic portstype inference for polymorphic ports– modeling of the application and the modeling of the application and the

platformplatform

DefinitionsDefinitions

• Component:Component:– A unit of re-use with an interface and an A unit of re-use with an interface and an

implementationimplementation

• Meta-information:Meta-information:– Information about the structure and Information about the structure and

characteristics of an objectcharacteristics of an object

• Reification:Reification:– A data structure to capture the meta-A data structure to capture the meta-

information about the structure and the information about the structure and the properties of the programproperties of the program

• Reflection:Reflection:– An architectural technique to allow a An architectural technique to allow a

component to provide the meta- component to provide the meta- information to himselfinformation to himself

• Introspection:Introspection:– The capability to query and modify the The capability to query and modify the

reified structures by a component itself reified structures by a component itself or by the environmentor by the environment

5 portsadder

BALBOA Language & Run-BALBOA Language & Run-timetime

Interpreter

BIDL Compiler

Split Level Interfaces

GCC Compiled objects

Language Tools Run-time structure

GCC

Introspection

BIDL

C++

CIL

SLI/Type system

extension

Reflection

Introspective Interfaces for Introspective Interfaces for AnalysisAnalysis

Design Example: Design Example: Adaptive Cache ControllerAdaptive Cache Controller

CIL Script ExampleCIL Script Example

#load the AMRM component library#load the AMRM component library

load ./libamrm.soload ./libamrm.so

Entity mem_sysEntity mem_sys

Cache mem_sys.L1Cache mem_sys.L1

Memory mem_sys.MemMemory mem_sys.Mem

Queue mem_se.r_q Queue mem_se.r_q

L1.upper_request link_to ms.r_qL1.upper_request link_to ms.r_q

Mem.request_in link_to ms.r_qMem.request_in link_to ms.r_q

Tb add_stimuli 100 read 0x399Tb add_stimuli 100 read 0x399

Tb add_tcl_callback ms.r_q.activity Tb add_tcl_callback ms.r_q.activity { simulator.do_something; }{ simulator.do_something; }

simulator run 200simulator run 200

mem_sys

L1

Mem

r_q

Design Example: Cache Design Example: Cache ControllerController

1437/8801437/880

(1.63)(1.63)

8787< 150< 1507 C++ 7 C++

with SystemCwith SystemC

1512/10021512/1002

(1.51)(1.51)

8484< 40< 408 C++8 C++

with SystemCwith SystemC

812/809812/809

(1.01)(1.01)

6060< 30< 307 C++7 C++

IP vs Generated IP vs Generated C++ code size C++ code size ratioratio

Number of BIDL Number of BIDL lineline

Number of CIL Number of CIL lineslines

Number of C++ Number of C++ classesclasses

Script size vs C++ ratio: 1 is to 10

Manipulate only the script!

Composition FrameworkComposition Framework

• Dynamically adapt, control and debug complete Dynamically adapt, control and debug complete system modelssystem models– Using “script-like” interfaces and mixed Using “script-like” interfaces and mixed

compiled and interpreted programming compiled and interpreted programming componentscomponents

– Component introspection through the Component introspection through the reflection enables IP reusereflection enables IP reuse

• Create “Virtual” System ArchitecturesCreate “Virtual” System Architectures– Include application and system software in the Include application and system software in the

modelmodel

• Exploit full potential of SOC architectural platforms Exploit full potential of SOC architectural platforms – by exploring runtime system services suitable by exploring runtime system services suitable

for SOC applicationsfor SOC applications– example: dynamic power managementexample: dynamic power management

ExtendedSystemC

Custom OS Generation

HW WrapperGeneration

Virtual Architecture

RTL Architecture

RTL Synthesisand Compilation

Emulation platform

Co-simulationWrapper Generation

ExecutableCo-simulation

Model

APIs

Communicationand System

Services

DeviceDrivers

OS librariesProcessorlibraries

Protocollibraries

HW wrapperlibraries

Simulatorlibraries

Channellibraries

Co-simulationlibraries

Cesario, et al, IEEE D&T 11/02

Virtual System ArchitecturesVirtual System Architectures

OS-directed Power Management OS-directed Power Management for SOCsfor SOCs

• Significant opportunities in power Significant opportunities in power management lie with application-specific management lie with application-specific “knobs”“knobs”

– quality of service, timing quality of service, timing criticality of various functionscriticality of various functions

• CCollaboration between applications and the ollaboration between applications and the OS in setting “energy use policy”OS in setting “energy use policy”

– OS helps resolve conflicts and OS helps resolve conflicts and promote cooperationpromote cooperation

• The enable OS-directed dynamic power The enable OS-directed dynamic power management, we need:management, we need:

OS should incorporate OS should incorporate application information in application information in DPM policyDPM policy

OS should expose power state OS should expose power state and events to applications for and events to applications for these to adapt.these to adapt.

Application

PA-API

PA-Middleware

POSIX PA-OSL

OperatingSystem

OperatingSystem

ModifiedOS Services

Hardware Abstraction Layer

PA-HAL

Hardware

Power Aware Software Power Aware Software ArchitectureArchitecture

• PA-API (Power Aware API) PA-API (Power Aware API)

– interfaces applications and interfaces applications and OS making the power aware OS making the power aware OS services available to the OS services available to the application writer.application writer.

• PA-OSL (Power Aware Operating PA-OSL (Power Aware Operating System Layer)System Layer)

– implements modified OS implements modified OS services and active services and active components such as a DPM components such as a DPM manager. manager.

• PA-HAL (Power Aware Hardware PA-HAL (Power Aware Hardware Abstraction Layer)Abstraction Layer)

– interfaces OS and Hardware interfaces OS and Hardware making the power control making the power control knobs available to the OS knobs available to the OS programmer.programmer.

Current StatusCurrent Status

• API available from http://www.ics.uci.edu/~cpereira/padsAPI available from http://www.ics.uci.edu/~cpereira/pads

• Implementation on eCOS RTOS andImplementation on eCOS RTOS and

– Hardware platforms we are currently working Hardware platforms we are currently working with:with:

» Linux-synthetic (emulation of eCos over Linux - debugging Linux-synthetic (emulation of eCos over Linux - debugging purposes only)purposes only)

» Compaq iPaq Pocket PC - StrongARM SA1110 based platformCompaq iPaq Pocket PC - StrongARM SA1110 based platform

» Accelent IDP (Integrated Development Environment) - also Accelent IDP (Integrated Development Environment) - also StrongARM SA1110 based. StrongARM SA1110 based.

» LRH Intel evaluation board 80200EVB - Intel Xscale2 basedLRH Intel evaluation board 80200EVB - Intel Xscale2 based

OS-directed DVS ResultsOS-directed DVS Results

Energy Consumption for each scheme

0

0.2

0.4

0.6

0.8

1

1.2

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Scheme

Ra

tio

of

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erg

y c

on

su

mp

tio

n

be

twe

en

No

rma

l an

d S

ch

em

e

Taskset A

Taskset B

Taskset C

8008001360013600FFT FFT (gaussian distribution)(gaussian distribution)T5T5

001590015900FFTFFTT4T4

3300330093009300ADPCMADPCMT3T3

210021002630026300MPEG2 MPEG2 (wg_cs_1.mpg)(wg_cs_1.mpg)T2T2

310031003070030700MPEG2 MPEG2 (wg_gdo_1.mpg)(wg_gdo_1.mpg)T1T1

Std Dev (us)Std Dev (us)WCET (us)WCET (us)ApplicationApplicationTaskTask

Using Application-level Using Application-level “knob”“knob”

• Example: Image Compression AlgorithmExample: Image Compression Algorithm– tradeoff image quality against energy tradeoff image quality against energy

available by varying the compression available by varying the compression parameters such as BPP (bits per parameters such as BPP (bits per pixel)pixel)

– The image compression algorithm is The image compression algorithm is ran in a continuous loop with battery ran in a continuous loop with battery polling every 10 secs.polling every 10 secs.

– A simple power tradeoff policy is A simple power tradeoff policy is added to adapt the quality of the added to adapt the quality of the image against the battery voltage left. image against the battery voltage left.

– Whenever the battery drops 30mV the Whenever the battery drops 30mV the application adjusts the image BPP by application adjusts the image BPP by -0.5 starting at 1.5.-0.5 starting at 1.5.

For a cut-off of 4020mV, the For a cut-off of 4020mV, the battery life is extended from 290 battery life is extended from 290 seconds to 340 seconds.seconds to 340 seconds.

Summary: Computers with Summary: Computers with Radios are Leading to New Radios are Leading to New

“Spaces”“Spaces”

• Generational shift in computing devicesGenerational shift in computing devices– lot more of everything: computing, networking, lot more of everything: computing, networking,

communicationscommunications– lot less of power, energy, volume, weight, patiencelot less of power, energy, volume, weight, patience– Application is everything, the possibilities are Application is everything, the possibilities are

limitless limitless

• System architectures are due for an overhaulSystem architectures are due for an overhaul– the architectures are (radically) the architectures are (radically)

changed/challengedchanged/challenged– the programming context is changedthe programming context is changed– the system software the system software contractcontract is changed is changed

» new awareness: location, power, timing, reactivity, stabilitynew awareness: location, power, timing, reactivity, stability

power

Instrumented wide-area spaces

Personal area spaces

Internet end-points

In-body, in-cell, in-vitro spaces

SOC Architectural Design SOC Architectural Design ParadigmsParadigms

SpecializedAmbitious (and never finished)

The sacrificial altar

Engineered

“Organically grown”The IP Basket

The Planned Community