BGA’s, LGA’s, QFN/DFN’s – Oh My, Can Traditional DFM Survive
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Low Stand-off Components Cover A Wide Range Of Package Styles And Types Including DFN, QFN, LGA, Leadless Chip Carriers and some BGA’s (Ball and Bump Grid Arrays)
Lack Of Package Standardization Increases Inconsistency In Assembly Processes,Stencil Tooling Designs And Cleanability
Low Stand-Off Components
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IPC: Magnification Aids Shall Be Appropriate For Item Being Inspected.Is 20X Magnification Strong Enough? What About 40X?
Where Is The Component?
Source: IPC-A-610, Section 1.10
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IPC-7351 recognizes the requirements of higher component density applications and provides information on land pattern geometry used for specific product categories.
Level A: Maximum Land Protrusion — For low-density product applications
Level B: Median Land Protrusion — Products with a moderate level of component density
Level C: Minimum Land Protrusion — Products with high component density
Note: Smaller visible fillets impacts AOI ability to determine if there is a fillet. Post reflow position also impacts this ability. Increased false call rate.
Land Pattern Design Inspection Impacts
Level A Level B Level C
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Spacing Limitations Are Not A Driven By The Manufacturing/Assembly Process
SMT PadsMinimum Or No Visible Solder (Toe) Fillets
Potential AOI/Inspection IssueComponent Spacing
Minimum Component to Component Spacing
Limited/No ReworkLimited AOI/Test Point Access
High Design Density
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The PCB layout design for the … requires a couple of considerations. The design of the cutout to allow light to illuminate the sensor is a critical part of this design.The device layout is also critical for optimal SMT assembly.
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Solder Mask Via Tenting Options
Atmel Application Note
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Solder Mask Via Cap
Solder Mask Via Plug
Solder Mask Via Fill
Via Fill & Over Plate
Via Filling Types
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Exposed Via In Pad• Ensure Solder Mask Is Not Applied On
Opposite Side Of PCB.• If Applied, Ensure Via Hole Is Small
Enough To Restrict Solder Mask Flow Through To Solder Attach Side Of PCB
• If Top Side Via Plugging Is Required, Especially Is Under BTC Components, A Note Should Be Added To Fabrication And Assembly Drawing Referencing This Condition Especially If Solder Mask Is Designed To The Same Size As The PCB Pad Size
Solder Mask Design
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Pad Geometries• Non-Solder Mask Defined (NSMD)
• Size of Pad Defined By Copper Pad and Interconnections (Variable Size)
• Solder Encapsulates Pad• Limited to Components With Lead Pitch Greater Than
0.4mm
• Solder Mask Defined (SMD)• Size of Pad Defined By Solder Mask Opening (Uniform
Size)• Solder Covers Exposed Pad (Fills Opening)• Required For Components With Lead Pitch 0.4mm or
Less.• Preferred for Leadless Array Devices Like LGA’s, Multi-
row QFN’s, etc.
Solder Mask Opening Design
PLEXUS CONFIDENTIAL
PCB fabricator reduced solder mask openings greater than 0.002” resulting in solder paste being printed on top of solder mask.
Results was a slight excess of solder paste on top of solder mask resulting in solder balls under component package.
Solder Mask Defined Pads
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Problem:IPC requirement for measurement of etch size tolerance is taken from the located of widest point (dimension “B”).
Solution:Develop fabrication note that will specify tolerance.
Example: Non-solder mask defined land/pad size tolerance measured at crest shall be +/-0.001”.
Copper Etching Of Pads
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Copper pads when measured at the top surface may be significantly smaller than at widest point.
Potential issue where solder stencil openings are too large to rest on top of pad and insufficient solder paste may be applied for reliable solder connection formation.
Copper Etching Of Pads
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Over etching of top of copper pad can create issue with:1. Decreased solder paste printed volume2. Shifted component placement3. Test probe missing pad (false failure – open
connection)
Over Etching Of Mounting Surface
Stencil
Solder Paste
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Very Small Copper Features• Shown is a 0.4mm pitch 8 ball CSP
with 0.2mm nominal pads.
• NSMD on left, SMD on right using LDI
• Note NSMD no connects are smaller due to 360°etching
• Etching accuracy can have a huge impact on features 0.3mm (12mils)
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Combined Copper Etching and Solder Mask Effects
Image: Benchmark Upper Midwest SMTA Chapter Presentation, April 2016
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Problem:IPC specifications do not have a size tolerance requirement for solder mask defined pads. IPC tolerances only address solder mask clearances around non-solder mask defined pads. For BGA components only, the tolerances are for registration (encroachment) only, not for opening size.
Solution:Develop fabrication note that will specify tolerance of solder mask openings on solder mask defined pads. This tolerance may be limited to opening dimensions less than a maximum dimension
Solder Mask Defined Pads
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IPC-6012D Section 3.6.2.18 shall fill a minimum of 60% (voids of up to 40%) for Class 2 and Class 3 assemblies. When cap plating is not specified, fill material shall encapsulate internal voids and be planar.
Conductive/Non-Conductive Fill
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Per IPC-6012 Section 3.6.2.11.3, voids are acceptable provided they are completely encapsulated and in total do not exceed 25% of viewable area of filled microvia.But does the trapped chemistry create a potential reliability issue during soldering process or in end use environment?
Plated Copper Filled Microvias
PLEXUS CONFIDENTIAL
With plated closed buried via holes, there can be plating chemistry still trapped in the close via that may create excessive stress on barrel/wrap plating that could lead to corrosive chemical leakage after soldering process or in end use applications
Buried Plated Close Via
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Fine Pitched BGA With Micro-Via-In-Pad Design.PCB Design Was A 1-6-1 ConstructionUnbalanced Copper Density On Layer Directly Beneath Package
Localized PCB Thickness Variation
Unbalanced Copper Density Under Package
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Fine Pitched BGA With Micro-Via-In-Pad Design.PCB Design Was A 1-6-1 ConstructionUnbalanced Copper Density On Layer Directly Beneath Package
Localized PCB Thickness Variation
Unbalanced Copper Density Under Package
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Silk Screen Should Not Be Placed Under Body Of Low Standoff Components
• Increased Gap For Solder To Bridge During Solder Reflow Process
• Potential Tilting Of Components (Open Connection)
• Potential Latent Field Failure With Partial Solder Connection
Silk Screen Design - Low Standoff Packages
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Silk Screen Design - Low Standoff Packages
Low Component Stand-off HeightExcessive PCB to Component Standoff Height – Open JointTilted ComponentOpen Joints (one edge or center standoff from PCB)Misalignment
Component TypesLeadless• QFN, DFN, LCC
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Reference: QFN/DFN Inspection of Solder Joints, Linear Technology Application Note
With BTC’s, Not All Pads Are Equal
Packages That Are Singulated By Saw Or Punch Cut Are Not Solderable Per IPC-A-610 Section 8.3.13 Notes 2 And 5
PLEXUS CONFIDENTIAL
Some Packages Have Solderable Edge TerminationsRequires additional pad length for solder fillet formation.
With BTC’s, Not All Pads Are Equal
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Solder Mask Defined Non-Solder Mask Defined
Solder wicking around NSMD pads produce significantly lower molten solder height.Solder mask defined pads should be used for LGA and 0.4mm & smaller pitch BGA/CSP packages.
LGA Pad Design
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Trace Routing Under Component Create Localized Height Variations• Standoff Height Variation
Leadless Devices Are More Sensitive To PCB/Component Flatness/Warpage • Received Condition
• In-process Condition (During Reflow/Rework Solder Process)
LGA Package
BGA Package
LGA/QFN Package Assembly
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EFFECTIVE PAD SIZE ANALYSIS
0
10
20
30
40
50
60
4 10 15 20WIDTH OF TRACE
% P
AD S
IZE
INCR
EASE
10 Mil Nom 15 Mil Nom 20 Mil Nom
10 Mil Max 15 Mil Max 20 Mil Max
Trace Routing And Solder Mask Opening Impacts Solder Joint
Increased Mounting Pad Size Affected By:• Number Of Trace Connections To Each Pad• Width Of Trace Connections To Each Pad• Size of Pad
– Small Pads Have Less Margin• Uniformity Of Trace Egress Direction
– Some Package Types Are More Sensitive Than Others
• Uniformity Of Trace Sizes
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Combination Of Component And PCB Thermal Expansion Differences Can Increase Opportunity For Z-axis Expansion Induced Defects
Component and PCB Warpage
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Warpage Created Issues
INEMI Roadmap 2013.
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Example Of Uniform Component Warpage Over Assembly Temperature Range
Component Warpage
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Example Of Non-Uniform Component Warpage Over Assembly Temperature Range
Component Warpage
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Bigger Aperture Is Recommended To Outer Region Where Head In Pillow Is Observed JEITA ED-7306 Allowed Warpage For BGA And FBGA Packages
Component Warpage
Cypress Application Datasheet
PLEXUS CONFIDENTIAL
Increase in aperture opening may not be the only method to address component warpage. It can be a decrease in aperture opening or a combination of increased, 1 to 1, and decreased aperture openings on the same package.
Component Warpage
Intel Board Design Guideline for Intell Programmable Device Pacakges, AN-114
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Offset Paste – Normal Placement
Video Courtesy of Juki Automation
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Matched Offset – Paste & Part
Video Courtesy of Juki Automation
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Placement And Types Of ViasIn Pad Can Affect Assembly Solder Joint Formation
More Of An Impact On Smaller Components And/Or Lower I/O Count
Impacts of Via Design on Assembly
Design and Construction Affects on PWB Reliability, Paul Reid, IPC Apex Proceedings 2012.
PLEXUS CONFIDENTIAL
Placement And Types Of ViasIn Pad Can Affect Assembly Solder Joint Formation
More Of An Impact On Smaller Components And/Or Lower I/O Count
Impacts of Via Design on Assembly
Design and Construction Affects on PWB Reliability, Paul Reid, IPC Apex Proceedings 2012.
PLEXUS CONFIDENTIAL
Increased Solder Process Thermal Variability • PCBA Level• Component To Component• Pad To Pad
Via-In-Pad Design Impacts
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Examples Of Via-In-Pad Types
Filled & Over Plate Thru Via
Stacked Micro-via, Multiple Copper Thicknesses
Stacked Micro-via On Buried Via’s
PLEXUS CONFIDENTIAL
Placement Of Stacked Vias Or Through Via In Pad Under Devices May Create Mounting Pad Height Differences During Solidification Process
Z-Axis Expansion/Contraction Impacts Of Via In Pad
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More Of An Impact On Smaller And/Or Lower I/O Count or Leadless (No Solder Ball/ Solder Bump) Component Packages
Z-Axis Expansion/Contraction Impacts Of Via In Pad
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Board Warpage Within IPC Assembly Workmanship Standards (0.75%) May Not Be Adequate For Some Component Packages To Obtain High Assembly Yields.Warpage can be impacted by both CTE mismatch and localize temperatures from localized component density, component/printed board size, and vertical heating/cooling differences. Reflow profile to bridge component warpage gap: Decrease thermal rate of change and delta T vertically in component package – reduce surface to cooler location temperature delta - TCE induced warpage
Board Warpage
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It is recommended that the via diameter be 0.30 to 0.33 mm with 1.0 ounce copper via barrel plating. This is desirable to avoid any solder-wicking inside the via during the soldering process, which may result in voids in solder between the exposed pad and the thermal land.
Exposed Via Impact
Freescale Semiconductor, Inc. Application Note
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Smaller Via Hole Size In Thermal Pad Reduce Solder Flow Into Via Hole
Via Hole Size
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Exposed Via Holes Provide Path For Flux Volatiles And Solder To Escape From Under Component Body
Note: Solder In Via Is Not Continuous.
Exposed Via Impact
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Exposed Via Impact
Exposed Via Holes Provide Path For Flux Volatiles And Solder To Escape From Under Component Body
Note: Solder In Via Is Not Continuous.
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Void Size and Quantity Decrease With Increased Number Of Exposed Via Holes In Thermal Pad Per Unit Area
Voids In Thermal Pad
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During Reflow Process, The Large Surface Area Of The Thermal Pad Creates A Large Volume Of Nonvolatilized Residue Around The Perimeter Of The Pad.
As Pad Area Increases, The Residue Volume To Pad Perimeter Length Ratio Increases At A Linear Rate (The Residue Volume Is Increasing At A Greater Rate Than The Area Around The Pad To Clean)
Thermal Pad Residue Impacts
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With Increased Use Of Low Stand-Off Packages And With Or Without Thermal Pads Restricts Cleaning Solutions Access To Soldering Residues
Why Cleaning Is Important!
Fully Cleaned Partially Cleaned No CleaningSource: Reactivity of No-Clean Flux Residues Trapped Under BTCs, M.Bixenman, et.al., SMTA-I 2016 Proceedings
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Impacts of PCB Design on Ability to Remove Soldering Process Residues• Solder Mask
• Component Size
• Cleaning Exposure Time
Cleaning
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Beware Of What You Cannot See
Courtesy of Kester
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Intellectuals solve problems, Geniuses prevent them.
Questions?
Albert Einstein
And when you thought it could not get any worse.
Here it comes!