Download - C4 Digital Transmission
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Digital Transmission
Chapter 4
Typical pulse response of a band-limited channel.
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Pulse Transmission Perfect Square wave can be reconstructed
only if all the harmonic components are added together.
Thus, Transmission of a square wave requires transmission of all the frequency components. This implies that the channel must have infinite bandwidth.
Pulse Transmission Also, the amplitudes of harmonics
decrease exponentially.
As a result, if channel has an adequate bandwidth to pass the fundamental frequency and few harmonics, the square wave can reconstructed with slight ambiguity.
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Pulse Transmission 90% power in contained within first null
(f = 1/T). Thus, signal can be confined to a BW = 1/T and still pass most of the energy from the original waveform.
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Pulse Transmission In theory, only the amplitude at the middle
of each pulse interval needs to be preserved.
If the BW is confined to BW = 1/2T, the max. signaling rate achievable is given as the Nyquist rate and is equal to twice the BW, R = 2BW
Pulse Transmission Most of the pulse trains are not square
waves and have dc component. Hence the transmission channel must be capable of transmitting dc components as well.
Alternatively, techniques may be adopted to remove dc components from the waveforms before transmission.
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Pulse Transmission Apart from the adequate BW, channel
must offer equal attenuation and equal delay for all the frequencies within the BW.
When it is not, certain frequencies may get delayed so much they result in what is known as Intersymbol Interference.
ISI ISI is an important consideration in the
transmission of pulses over circuits with a limited bandwidth and a non-linear phase response.
Simply stated, rectangular pulses will not remain rectangular in less than an infinite bandwidth.
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ISI Each transmitted pulse reaches its full
value at precisely the center of each sampling interval.
Due to band limitation, the signal does not attain always the full value at the sampling instants at output end.
Overlapped ringing tails interfere with major pulse lobe.
ISI ISI causes crosstalk between channels
that occupy adjacent time slots in TDM carrier system.
Equalizers are used to remove distortions.
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Four primary causes of ISI Timing inaccuracies. Insufficient Bandwidth. Amplitude distortions. Phase distortions.
Timing Inaccuracies If the rate of transmission does not confirm
to the ringing frequency designed into the communications channel.
Receiver clocking information is derived from the received signals, inaccurate sample timing is more likely to occur in receivers than in transmitters.
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Insufficient Bandwidth As the bandwidth of communication
channel is reduced, ringing frequency is reduced, and ISI is more likely to occur.
Amplitude distortion When the frequency characteristics of a
communications channel depart from the normal or expected values, pulse distortion results.
Pulse distortion occurs when the peaks of pulses are reduced, causing improper ringing frequencies in time domain.
Compensation for such impairments is called amplitude equalization.
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Phase distortion If the relative phase relations of individual
harmonics are altered, phase distortionoccurs.
Frequency components undergo different amounts of time delay while propagating through transmission medium.
Delay equalizers are used to compensate phase distortion.
Asynchronous vs. SynchronousTransmission
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Asynchronous Transmission Asynchronous without synchronism
without a specific time reference. Start-Stop (Ping-Pong) transmission. The start and stop bits identify the
beginning and end of the character. A high-to-low transition is used for start bit. All stop bits are logic 1s. Idle line or dead time is identified by
continuous string of 1s.
Asynchronous Transmission
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Asynchronous Transmission The main attraction of asynchronous
transmission is the ease with which it determines the sample times in the receiver.
In addition, asynchronous transmission automatically provides character framing and is inherently flexible in the range of average data rates that can be accommodated.
An asynchronous system is naturally suited to applications where the data rate varies.
Asynchronous Transmission In practice, sampling time departs from ideal
depending on how much the start bit is corrupted by noise and distortion.
Since the sample time for each information bit is derived from a single start bit, asynchronous systems do not perform well in high-noise environments.
More than one start bit could improve accuracy but would complicate receiver and add more overhead for timing information.
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Asynchronous Transmission Frequencies of transmit and receive clocks
should be close and synchronized at beginning of each character.
Clock slippage occurs when there is difference in transmit and receive clocks.
Under-slipping transmit clock is lower than the receive clock.
Over-slipping transmit clock is higher than the receive clock.
Synchronous Transmission Digital signals are sent continuously at a
constant rate.
Receiving terminal must establish and maintain a sample clock that is synchronized to the incoming data for an indefinite period of time.
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Synchronous Transmission Synchronous Transmission systems can support
variable rates, but the adjustment of information rate requires inserting null codes into the bit stream.
The null codes are used as a filler when a source has nothing to send.
This form of transmission is sometimes referred to as isochronous.
An isochronous mode is required whenever a synchronous line carries data from an asynchronous source.
Synchronous Transmission The synchronization requirements imply
that a certain minimum density of signal transitions is required to provide continuous indication of signaling boundaries.
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Synchronous Transmission The synchronization requirements imply
that a certain minimum density of signal transitions is required to provide continuous indication of signaling boundaries.
Six techniques to recover timing information
Source code restriction Dedicated timing bits Bit insertion Data scrambling Forced bit errors Line coding
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Source code restriction Restrict the code set or data patterns of
the source so that long-transition-free data sequences do not occur.
00000000 or 11111111
Dedicated Timing Bits Transition-bearing bits are periodically
inserted into data stream.
Only 7 out of 8 bits are available for user. The unused bit provides an assurance that all 8 bits are not 0.
The density of timing pulses ranges from 1 in 5 bits to 1 in 20 bits.
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Bit Insertion Another possibility for precluding
unwanted line patterns is to use bit-insertions only when necessary.
A line could be monitored for all 0s in the first 7 bits of a time slot. Whenever the 0s occur, a 1 could be inserted into the data stream as the eight bit of the time slot.
Data Scrambling Data scramblers randomize data patterns
on their transmission links.
Scrambling is not used on lower rate systems.
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Forced Bit Errors Force an occasional bit error in order to
interrupt a long, transition-free data pattern.
Intentional errors are less frequent than random channel errors if transition-free sequences are long and uncommon.
Not recommended with ARQ facility on link.
Line Coding
Chapter 4
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Purpose of line coding Extract the DC content from the message Add synchronization information into line signal Increase information data rate through the
channel Change the spectral shape of the message so
that it suits the channel better Improve performance (error detection and
correction) Compress data
Line Coding Level encoding Bipolar encoding BNZS Pair selected Ternary Ternary coding Digital Biphase Differential encoding Coded Mark inversion Multilevel signaling Partial response signaling
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Unipolar and polar (NRZ) line codes
DC wander
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Bipolar (AMI) Coding
Spectral Density of Bipolar Coding
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Digital Biphase (Manchester)
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Differential Encoding
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Coded Mark Inversion CMI encodes 1s as an NRZ level opposite
to the level of the previous one and 0s as a half cycle square wave of one particular phase
CMI
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BNZS: Binary N-Zero Substitution A major limitation of bipolar (AMI) coding
is its dependence on a minimum density of 1s in the source code to maintain timing information.
BNZS augments a basic bipolar by replacing all strings of N 0s with a special N-length code containing several purposes that purposely produce bipolar violations.
B3ZS Three 0s encoded as 00V or B0V
The decision to substitute with 00V or B0V is made so that the number of B pulses (unviolated) between violations is odd.
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B3ZS If an odd number of 1s has been transmitted
since last substitution, 00V is chosen to replace three 0s.
If the intervening number of 1s is even, B0V is chosen.
In this manner, all purposeful violations contain an odd number of intervening bipolar pulses.
Example Determine B3ZS code for the following
data sequence: 101000110000000010001
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Solution
HDB3 (high density bipolar 3)
B6ZS
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B8ZS
nBmT codes Another class of ternary codes are known
as alphabet codes. In this coding scheme, n binary digits
taken together are coded into m-digit ternary character.
2n binary characters 3m ternary characters
Generally described as nBmT codes
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Pair Selected Ternary (PST)2B2T codes
A balance between positive and negative pulses and a strong timing component are maintained by switching between the modes appropriately.
2B2T codes As the ternary digits are transmitted, sum of
positive and negative pulses is kept. If the sum is zero, the mode remains
unchanged, if a single pulse has been transmitted & if
the sum is positive, -mode is selected and if the sum is negative, +mode is selected.
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Example (PST) Encode the following binary data stream into a
PST line code: 01001110101100 (assume initial sum = 0).
Solution Case1 (+Mode) [0+ -+ +- -0 +0 +- -+] Case 1 (- Mode) [0- -+ +- +0 -0 +- -+]
Spectrum of Bipolar, B6ZS, and PST line codes
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4B3T code
4B3T Ternary words in the middle column are dc
balanced. Codes from first and third columns are
selected alternatively to maintain dc balance.
All 0s code is not selected to maintain timing component.
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Line Coding Unipolar, Polar NRZ Bipolar (AMI) Digital Biphase (Manchester) Differential encoding CMI BNZS nBmT (PST)
Other Line Codes
Multilevel signaling Partial response signaling
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Example of line coding
Multilevel signaling In applications, where the BW is limited
but higher data rates are desired, the number of levels can be increased while maintaining the same signaling rate.
Specifically, if the signaling rate or baud rate is Rs and the number of levels used is L, the equivalent transmission bit rate Rb is given by
)(log2 LRR sb =
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Multilevel signaling Signaling rate is referred to as symbol rate and
is measured in bauds.
Bit rate is equal to baud rate if I bit per signaling interval is used
One aspect of wire line transmission that favors multilevel line coding is the lower baud rate for a given data rate, which in turn reduces the cross talk.
Multilevel signaling Multilevel transmission systems achieve
greater data rates within a given band-width but require much greater signal to noise ratios for a given error rate.
In crosstalk limited systems, the SNR penalty of a multilevel line code is not as significant.
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8-level (3 bits per baud)
The primary factors that led to selecting a multilevel line code in above example are:
Near-end crosstalk that cannot be eliminated by pair isolation as in T1 systems, and
High levels of intersymbol interference caused by bridged tap reflections.
Both these factors are easier to control when lower frequency signals are used.
A four level signaling scheme at 80-kBaud is used to achieve 160 kb/s as a basic rate in a digital subscriber loop (DSL) for ISDN.
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Partial Response Signaling A class of signaling techniques variously
referred to as duo-binary, correlative-level encoding or partial-response signaling, purposely introduces a prescribed amount of ISI that is accounted for in the detection circuitry of the receivers.
Partial Response Signaling By over-filtering the encoded signal, the
bandwidth is reduced for a given signaling rate, but the overlapping pulses produce multiple levels that complicate the detection process and increase the signal power requirements for a given error rate.
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Pulse response of a typical partial response-system
If the channel is excited by a pulse duration T, channel filters limit the spectrum such that the main part of pulse extends across three signal intervals and contributes equally to two sample times.
PRS The reason for the term partial response is
now apparent: The output responds to one-half the amplitude of the input.
If the input pulse is followed by another pulse of the same amplitude, the output will reach full amplitude by virtue of the overlap between pulses.
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PRS A partial response system with two level
(binary) inputs (+1, -1) produce an ternaryoutput with three levels (+1, 0, -1).
In a similar fashion, a PRS with four level inputs(+3, +1, -1, -3) produce an output with seven levels(+3, +2, +1, 0, -1, -2, -3).
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Correlative Level Encoding It is convenient to introduce a delay
operator D to denote delay equal to one signal interval T.
Physically, D can be thought of as a delay line of length T.
Two units of delay is implemented with two delay lines in series and denoted as D2.
1+D PRS
The output represents the superposition of the input with a delayed version of the same input.
The T1D system of AT&T uses 1+D signaling with precoding, referred to as duobinary signaling, to convert binary (two level) data into ternary (three level) data at the same rate.
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Duo-binary Bit stream 1101100010111
Bipolar coding => 11-111-1-1-11-1111
1+D = 120020-2-200022 Sample values of same polarities are
separated by even number of zeros and sample values of opposite polarities are separated by odd number of zeros.
Find error if any 1+D = 12000-200-20200-20220-2
1+D = 12000-200-20200-20220-2
Possible sequences are: 1100, 1000, 0100, 1010
Solution
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1-D PRS
1- D2 PRS A 1-D2 system can be implemented by
concatenating a 1-D encoder with a 1+D channel response: (1-D)(1+D) = 1-D2.
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Spectra of unfiltered 1+D, 1-D, 1-D2correlative encoded signals
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Given the input sequence +1, -3, +1, -1, +3, +3, -3 of signal levels, determine the sequence of output signal levels for each of the following correlative encodings.(a) 1 + D encoder(b) 1 - D encoder(c) 1 D2 encoder
+1 -3 +1 -1 +3 +3 -31+D -2 -2 0 +2 +6 01-D -4 +4 -2 +4 0 -61-D2 0 +2 +2 +4 -6