Download - Calibrating Achievable Design (C.A.D.) Theme
GSRC Annual Review, 020610 abk 1
Calibrating Achievable Design (C.A.D.) ThemeCalibrating Achievable Design (C.A.D.) Theme
This Theme solves Design Technology productivity gapsThis Theme solves Design Technology productivity gaps
Specification GapSpecification Gap What will be the critical design problem? = FOCUSWhat will be the critical design problem? = FOCUS GSRC Technology Extrapolation (GTX) System GSRC Technology Extrapolation (GTX) System
and “Living ITRS” and “Living ITRS” http://vlsicad.ucsd.edu/GTX
Development and Delivery GapDevelopment and Delivery Gap How to deploy DT better and faster? = TTM, QORHow to deploy DT better and faster? = TTM, QOR
GSRC Bookshelf for CAD-IP ReuseGSRC Bookshelf for CAD-IP Reuse http://vlsicad.eecs.umich.edu/BK
Measurement and Improvement GapMeasurement and Improvement Gap Did envelope of achievable design grow? = METRICSDid envelope of achievable design grow? = METRICS
GSRC METRICS System for Design Process GSRC METRICS System for Design Process OptimizationOptimization http://vlsicad.ucsd.edu/METRICS
GSRC Annual Review, 020610 abk 2
Other Roles of the C.A.D. ThemeOther Roles of the C.A.D. Theme
Repository of best known methods, Repository of best known methods, models, metricsmodels, metrics Connects applications and drivers (e.g., Connects applications and drivers (e.g.,
ITRS MPU, SOC) to technology roadmapITRS MPU, SOC) to technology roadmap Connects algorithm (e.g., Fabrics) and Connects algorithm (e.g., Fabrics) and
design technology (e.g., Power-Energy) design technology (e.g., Power-Energy) within GSRC and to designs, interconnects, within GSRC and to designs, interconnects, devices, and materials (= other FRCs)devices, and materials (= other FRCs)
Agent of culture changeAgent of culture change Measurement & characterization of EDAMeasurement & characterization of EDA Open-source CAD-IP; vertical benchmarkingOpen-source CAD-IP; vertical benchmarking New vectors: e.g., reusable curriculum IP New vectors: e.g., reusable curriculum IP
for VLSI, VLSI design, VLSI design for VLSI, VLSI design, VLSI design technology educationtechnology education
Identify best opportunities for “sharing of red bricks” between EDA Identify best opportunities for “sharing of red bricks” between EDA and other semiconductor supplier industriesand other semiconductor supplier industries GTX studies + Manufacturing Calibration: Is low-k worth the development cost? GTX studies + Manufacturing Calibration: Is low-k worth the development cost?
What is the best interconnect process architecture for 65nm? What FEOL and What is the best interconnect process architecture for 65nm? What FEOL and BEOL variabilities can designers tolerate? What is the most cost-effective BEOL variabilities can designers tolerate? What is the most cost-effective memory-logic integration?memory-logic integration?
C.A.D. Theme
Other FRCs
Other GSRC
Themes
EDA Industry & Academia
ITRSSemi
Industry
Design Houses
METRICS & Design Process Opt
Models and Calibrations
Open-Source CAD-IP
Living ITRS
What is the design problem?
VLSI Design EducationManufacturing Calibration
How should Design help solve ITRS red bricks?