Download - chap 2 isa part b
-
8/17/2019 chap 2 isa part b
1/47
CPU R EGISTERS
• Registers are faster than other type ofmemories
• Shorter instructions: – The number of registers is smaller (e.g. 32 bitregisters need 5 bits)
• Minimize the frequency with which data ismoved back and forth between the memoryand processor registers
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 66
-
8/17/2019 chap 2 isa part b
2/47
INSTRUCTION EXECUTION
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
R0,CB,R0A,R0
Movei + 8
Begin execution here Movei
ContentsAddress
C
B
A
the programData for
Addi + 4
A program for C = [A] + [B].
Assumptions:- One memory operandper instruction
- 32-bit word length- Memory is byte
addressable- Full memory addresscan be directly specifiedin a single-word instruction
Two-phase procedure-Instruction fetch-Instruction execute
3-instructionprogram segment
67
-
8/17/2019 chap 2 isa part b
3/47
BRANCHING
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
NUMn
NUM2
NUM1
R0,SUMNUMn ,R0
NUM3,R0
NUM2,R0
NUM1,R0
A straight-lineprogram for adding n numbers.
Add
Add
Move
SUM
i
MoveAdd
i 4n +i 4n 4-+
i 8+
i 4+
•••
•
••
•••
68
-
8/17/2019 chap 2 isa part b
4/47
BRANCHING
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Programloop
N,R1Move
NUMn
NUM2
NUM1
R0,SUM
R1
"Next" number to R0
LOOP
Decrement
Move
LOOPDetermine address of"Next" number and add
N
SUM
n
R0Clear
Branch>0
•••
•••
Using a loop to add n numbers.
Branch targetConditional branch
69
-
8/17/2019 chap 2 isa part b
5/47
CONDITION CODES
• To describe processor status • Also called status flags
• Condition codes refer to the informationabout most recently executed instruction • Different instructions affect different flags• Example of flags:
– N (negative)
– Z (zero) – V (overflow) – C (carry)
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 70
-
8/17/2019 chap 2 isa part b
6/47
CONDITIONAL BRANCH INSTRUCTION
• Example of condition code flags: – A: 11110000 – B: 00010100
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
A: 1 1 1 1 0 0 0 0
+(−B): 1 1 1 0 1 1 0 0
1 1 0 1 1 1 0 0
C = 1
N = 1
V = 0
Z = 0
71
-
8/17/2019 chap 2 isa part b
7/47
S TATUS BITS: BLOCK DIAGRAM
• Interconnection of an ALU to the status bitsregister
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
ALU
V Z S C
Zero Check
Cn
Cn-1
Fn-1
A B
F
72
-
8/17/2019 chap 2 isa part b
8/47
ADDRESSING MODES
-
8/17/2019 chap 2 isa part b
9/47
ADDRESSING MODES
• A method to specify the location of anoperand
• Various addressing modes provided fordifferent purposes and different trade-offs – in terms of instructions length, etc.
• Effective address – the actual address of theoperand after all address computations ofthe addressing mode have been performed
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 74
-
8/17/2019 chap 2 isa part b
10/47
ADDRESSING MODES
• Implied : – AC ( accumulator ) is implied in “ADD M[AR]” in
“One-Address” instruction
– TOS ( stack ) is implied in “ADD” in “Zero-Address” instruction
• Immediate : – The use of a constant in “MOV R1, 5” – i.e. R1 ← 5
• Direct Address (absolute) : – Use the given address to access a memory
location, “MOV R1, 110”
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 75
-
8/17/2019 chap 2 isa part b
11/47
ADDRESSING MODES
• Register (or register direct): – Indicate which register holds the operand
• Register indirect : – Indicate the register that holds the number of theregister that holds the operand
• Displacement addressing : – Relative, indexing, base
• Autoincrement/autodecrement : – Access and update in 1 instruction
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 76
-
8/17/2019 chap 2 isa part b
12/47
REGISTER INDIRECT
• Indicate the memory location that holds theaddress of the memory location that holdsthe data
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
AR = 101
100101102103104
0 1 0 4
1 1 0 A
AR – address register
77
-
8/17/2019 chap 2 isa part b
13/47
RELATIVE ADDRESSING
• Relative mode – the effective address isdetermined by the index mode using theprogram counter in place of the general-purpose register.
• X(PC) – note that X is a signed number
• This location is computed by specifying it asan offset from the current value of PC .
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 78
-
8/17/2019 chap 2 isa part b
14/47
RELATIVE ADDRESS
• Example: – EA = PC + relative address
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
100101102103104
012
AR = 100
1 1 0 A
PC = 2
+
Could be Positive orNegative
(2’s Complement)
PC – program counter
79
-
8/17/2019 chap 2 isa part b
15/47
INDEXING (1/2)
• Index mode – the effective address of theoperand is generated by adding a constantvalue to the contents of a register
• Using index register • X(Ri): EA = X + [R i]• The constant X may be given either as an
explicit number or as a symbolic namerepresenting a numerical value.
• If X is shorter than a word, sign-extension isneeded.
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 80
-
8/17/2019 chap 2 isa part b
16/47
INDEXING (2/2)
• In general, the index mode facilitates accessto an operand whose location is definedrelative to a reference point within the datastructure in which the operand appears.
• Several variations:
– (R i, R j): EA = [R i] + [R j] – X(R i, R j): EA = X + [R i] + [R j]
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 81
-
8/17/2019 chap 2 isa part b
17/47
INDEXED ADDRESS
• EA = index register + relative address
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
100101102
103104
AR = 100
1 1 0 A
XR = 2
+
Could be Positive orNegative
(2’s Complement)
Useful with“Autoincrement” or
“Autodecrement”
XR – index register
82
-
8/17/2019 chap 2 isa part b
18/47
BASE ADDRESS
• EA = base register + relative address
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
100101102103104
BR = 100
0 0 0 A
AR = 2
+
Could be Positive orNegative
(2’s Complement)
Usually points tothe beginning of
an array
0 0 0 50 0 1 2
0 1 0 70 0 5 9
BR – base register
83
Memory
-
8/17/2019 chap 2 isa part b
19/47
AUTOINCREMENT /AUTODECREMENT
• Autoincrement mode – the effective addressof the operand is the contents of a register specified in the instruction.
• After accessing the operand, the contents ofthis register are automatically incremented topoint to the next item in a list.
• (R i)+ = the increment is 1 for byte-sizedoperands, 2 for 16-bit operands, and 4 for32-bit operands.
• Autodecrement mode: -(R i) – decrement first
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 84
-
8/17/2019 chap 2 isa part b
20/47
AUTOINCREMENT ADDRESS EXAMPLE
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
R0Clear
R0,SUM
R1
(R2)+,R0
The Autoincrement addressing mode example
Initialization
Move
LOOP Add
Decrement LOOP
#NUM1,R2N,R1Move
Move
Branch>0
85
-
8/17/2019 chap 2 isa part b
21/47
ADDRESSING MODES S UMMARY
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Addressing Mode AssemblySyntaxAddressingFunction
Example inAssembly Example in RTN
Immediate #value Operand = value Add R4, #3 R4
-
8/17/2019 chap 2 isa part b
22/47
ASSEMBLY LANGUAGE
-
8/17/2019 chap 2 isa part b
23/47
TYPES OF INSTRUCTION
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Name Mnemonic
Load LDStore STMove MOV
Exchange XCH
Input INOutput OUTPush PUSHPop POP
Data value isnot modified
88
-
8/17/2019 chap 2 isa part b
24/47
DATA TRANSFER INSTRUCTIONS
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Mode Assembly Register Transfer
Direct address LD ADR AC ← M [ADR ]
Indirect address LD @ ADR AC ← M [M [ADR ]]
Relative address LD $ ADR AC ← M [PC +ADR ]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M [ADR +XR ]
Register LD R1 AC ← R1
Register indirect LD ( R1) AC ←
M [R1 ]Autoincrement LD ( R1)+ AC ← M [R1 ], R1 ← R1 +1
89
-
8/17/2019 chap 2 isa part b
25/47
ARITHMETIC INSTRUCTIONS
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Name MnemonicIncrement INCDecrement DEC
Add ADDSubtract SUB
Multiply MULDivide DIVAdd with carry ADDC
Subtract with borrow SUBBNegate NEG
90
-
8/17/2019 chap 2 isa part b
26/47
LOGICAL /BIT MANIPULATION
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Name MnemonicClear CLR
Complement COMAND ANDOR OR
Exclusive-OR XORClear carry CLRCSet carry SETC
Complement carry COMCEnable interrupt EI
Disable interrupt DI
91
-
8/17/2019 chap 2 isa part b
27/47
S HIFT INSTRUCTIONS
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Name Mnemonic
Logical shift right SHRLogical shift left SHL
Arithmetic shift right SHRAArithmetic shift left SHLA
Rotate right RORRotate left ROLRotate right through carry RORCRotate left through carry ROLC
92
-
8/17/2019 chap 2 isa part b
28/47
P ROGRAM CONTROL INSTRUCTIONS
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Name Mnemonic
Branch BR
Jump JMPSkip SKP
Call CALL
Return RETCompare(Subtract) CMP
Test (AND) TST
Subtract A – B butdon’t store the result
1 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0Mask
93
-
8/17/2019 chap 2 isa part b
29/47
CONDITIONAL BRANCH INSTRUCTIONS
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
Mnemonic Branch Condition Tested Condition
BZ Branch if zero Z = 1BNZ Branch if not zero Z = 0BC Branch if carry C = 1
BNC Branch if no carry C = 0BP Branch if plus S = 0BM Branch if minus S = 1BV Branch if overflow V = 1
BNV Branch if no overflow V = 0
94
-
8/17/2019 chap 2 isa part b
30/47
ADDITIONAL INSTRUCTIONS
-
8/17/2019 chap 2 isa part b
31/47
LOGICAL S HIFTS
• Logical shift – shifting left (LSHIFTL) andshifting right (LSHIFTR)
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
CR00
before:
after:
0
1
0 0 01 1 1 . . . 11
0 0 1 1 1 000
(b) Logical shift right LShiftR #2,R0(a) Logical shift left LShiftL #2,R0
C R0 0
before:
after:
0
1
0 0 01 1 1 . . . 11
1 10 . . . 00101 . . .
96
-
8/17/2019 chap 2 isa part b
32/47
ARITHMETIC S HIFT
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
C
before:
after:
0
1
1 1 00 0 1 . . . 01
1 1 0 0 1 011
(c) Arithmetic shift right AShiftR #2,R0
R0
. . .
97
-
8/17/2019 chap 2 isa part b
33/47
ROTATE
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 98
-
8/17/2019 chap 2 isa part b
34/47
MULTIPLICATION /DIVISION
• Not very popular (especially division)• Multiply Ri, R j:
– R j
← [Ri] х [R
j]
• 2n-bit product case: high-order half in R(j+1)• Divide R i, R j:
– R j ← [Ri] / [R j], Quotient is in Rj, remainder maybe placed in R(j+1)
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 99
-
8/17/2019 chap 2 isa part b
35/47
ENCODING OF MACHINE
INSTRUCTIONS
M I E (1/5)
-
8/17/2019 chap 2 isa part b
36/47
MACHINE INSTR . E NCODING (1/5)
• Assembly language program needs to beconverted into machine instructions (binaryformat): – ADD (assembly) = 0100 (in binary) in ARM
instruction set• In the previous section, an assumption was
made that all instructions are one word inlength.
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 101
MACHINE INSTR E NCODING (2/5)
-
8/17/2019 chap 2 isa part b
37/47
MACHINE INSTR . E NCODING (2/5)
• Suppose 32-bit word length, 8-bit opcode(how many instructions can we have?), 16registers in total (how many bits?), 3-bitaddressing mode indicator.
– Add R1, R2 – Move 24(R0), R5 – LshiftR #2, R0 – Move #$3A, R1 – Branch>0 LOOP
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
OP code Source Dest Other info
8 7 7 10
(a) One-word instruction format
102
MACHINE INSTR E NCODING (3/5)
-
8/17/2019 chap 2 isa part b
38/47
MACHINE INSTR . E NCODING (3/5)
• What happens if we want to specify amemory operand using the absoluteaddressing mode?
• Move R2, LOC• 14-bit for LOC memory address – insufficient
bit to include in the instruction• Solution – use two words
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA
(b) Two-word instruction format
Memory address/Immediate operand
OP code Source Dest Other info
103
MACHINE INSTR E NCODING (4/5)
-
8/17/2019 chap 2 isa part b
39/47
MACHINE INSTR . E NCODING (4/5)
• Then what if an instruction in which twooperands can be specified using theabsolute addressing mode?
• Move LOC1, LOC2• Solution – use two additional words
• This approach results in instructions ofvariable instruction length . Complexinstructions can be implemented, closelyresembling operations in high-levelprogramming languages – CISC
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 104
MACHINE INSTR E NCODING (5/5)
-
8/17/2019 chap 2 isa part b
40/47
MACHINE INSTR . E NCODING (5/5)
• If we insist that all instructions must fit into asingle 32-bit word, it is not possible toprovide a 32-bit address or a 32-bitimmediate operand within the instruction.
• It is still possible to define a highly functional
instruction set, which makes extensive useof the processor registers.• Add R1, R2 ----- yes• Add LOC, R2 ----- no• Add (R3), R2 ----- yes
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 105
-
8/17/2019 chap 2 isa part b
41/47
EXERCISES
EXERCISE 1
-
8/17/2019 chap 2 isa part b
42/47
EXERCISE 1
• Produce the following arithmetic expressionsinto Reverse Polish Notation (RPN): – A*B+C*D – (A-B+C)/(G+H) – A+B+C
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 107
EXERCISE 1 S OLUTION
-
8/17/2019 chap 2 isa part b
43/47
EXERCISE 1 – S OLUTION
• Solution: – AB*CD*+ – AB-C+GH+/ – AB+C+
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 108
EXERCISE 2
-
8/17/2019 chap 2 isa part b
44/47
EXERCISE 2
• Write the instructions to computeX=(B+A)*[D*(E-C)+G] usingmicroprocessors that use the following
instruction formats. If necessary, usetemporary location T to store intermediateresults.
• Instruction formats: – Three-address – Two-address – Zero-address – RISC format
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 109
EXERCISE 2 – S OLUTION (1/3)
-
8/17/2019 chap 2 isa part b
45/47
EXERCISE 2 S OLUTION (1/3)
• Three-address instruction: – SUB R1, E, C – MUL R1, R1, D – ADD R1, R1, G – ADD R2, B, A
– MUL X, R2, R1
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 110
EXERCISE 2 – S OLUTION (2/3)
-
8/17/2019 chap 2 isa part b
46/47
EXERCISE 2 S OLUTION (2/3)
• Two-address instruction: – MOV R1, E – SUB R1, C – MUL R1, D – ADD R1, G
– MOV R2, B – ADD R2, A – MUL R1, R2
– MOV X, R1
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 111
EXERCISE 2 – S OLUTION (3/3)
-
8/17/2019 chap 2 isa part b
47/47
EXERCISE 2 S OLUTION (3/3)
• Zero-address instruction: – PUSH E – PUSH C – SUB – PUSH D – MUL – PUSH G
– ADD – PUSH B – PUSH A
– ADD – MUL – POP X
Computer Architecture and Organization (BEC30303) | Chapter 2: ISA 112