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Chap 7. Chap 7.
Register Transfers and DatapathsRegister Transfers and Datapaths
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7.1 Datapaths and Operations7.1 Datapaths and Operations
Two types of modules of digital systems– Datapath
• perform data-processing operations– control unit
• determines the sequence of those operations
control signals – binary signals that activate the various data-processing operation
s Status signals
– aspects of the state of the datapath
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7.1 Datapaths and Operations7.1 Datapaths and Operations
Datapaths– Defined by the registers & operations that are performe
d on binary data stored in the registers– Register operations
• shift, count, clear & load, …– Register Transfer
• information flow and processing task on data
Basic components of register transfer operations1. Set of registers2. Operations that are performed on the data in registers
micro-operations3. Control that supervises the sequence of operations
Main topic
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7.1 Datapaths and Operations7.1 Datapaths and Operations
Microoperations– elementary operations performed on the data in register
s– examples
• loading the contents of one register into another
• adding the contents of 2 registers
• & incrementing the contents of a register
– usually performed in parallel during one clock-pulse period
Control unit – provides signals that sequence the microoperations
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7.2 Register Transfer Operations7.2 Register Transfer Operations
little endian
– Designated by capital letters• Ex) PC, IR, R1, R2
– flip-flops in an n-bit register are numbered in sequence from 0 to n-1
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7.2 Register Transfer Operations7.2 Register Transfer Operations
Replace operator: R2 R1– a transfer of the contents of R1 (source) into R2
(destination)– conditional statement
If ( K1 = 1 ) then ( R2 R1 ) , K1 : R2 R1
; K1 is a control signal generated in CU
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7.2 Register Transfer Operations7.2 Register Transfer Operations
Basic symbols for register transfer
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7.3 Microoperations7.3 Microoperations
4 categories: 1) Transfer microoperations
2) Arithmetic microoperations
3) Logic microoperations
4) Shift microoperations
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7.3 Microoperations7.3 Microoperations
Arithmetic Microoperations– basic: add, subtract, increment, decrement, & complement
– multiplication (*) & division (/) are not included in basic operations implemented by a special combinational circuit
AdderSubtractor
Binary up-downcounter
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7.3 Microoperations7.3 Microoperations
– X' K1 : R1 R1 + R2– X K1 : R1 R1 + R2' + 1
• timing variable K1 activates an operation to add or subtract• control variable X determines the operation• the output is loaded into R1 on any positive clock edge
X' K1 + X K1 = (X' + X) K1 = K1• X selects the operation (add or subtract) & K1 loads the result into R1
* Implementation of Add and Subtract micro-operations
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7.3 Microoperations7.3 Microoperations
Logic Microoperations– useful for manipulating the bits stored in a register
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7.3 Microoperations7.3 Microoperations
– NOT (bar(-) or ', same as 1's complement)
– AND (), OR ()
(ex) K1+K2: R1 R2+R3, R4 R5 R6
(or) (add) (or)
Logic Arithmetic Logic
– Easily implemented with a group of gates• NOT, AND, OR, XOR gates
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7.3 Microoperations 7.3 Microoperations – Bit manipulation– Bit manipulation
– AND microoperation• Used to delete all 1's from a selected portion of a register: masking out
10101101 1010 1011 R1 00000000 1111 1111 R2
00000000 1010 1011 R1 R1 R2
– OR microoperation• Used to set one or more bits in a register
10101101 10101011 R111111111 00000000 R2
11111111 10101011 R1 R1 R2
– XOR microoperation• Used to complement one or more bits in a register
10101101 10101011 R1 11111111 00000000 R2
01010010 10101011 R1 R1 R2
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7.3 Microoperations7.3 Microoperations
Shift microoperations– used in serial transfer of data– also used for manipulating contents of registers in arithmetic,
logic and control operations– (logical) shift
• R0 sr R0, R1 sl R2• incoming bit : assuming 0• outgoing bit : discarded
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7.4 Multiplexer-Based Transfer7.4 Multiplexer-Based Transfer Load from two or more different so
urces– If-then-else form
If(K1=1) then (R0 R1) else if(K2=1) then (R0 R2)
– Control conditions:
K1=1: R0 R1, K1’ K2: R0 R2
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer Bus system
– Shared transfer path
– control signals select a source register & destination register(s)
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer
Single-bus system– Simultaneous transfer with different sources in a
single clock cycle is impossible
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer
Hardware cost– Dedicated multiplexers
• 2n AND & n OR gates per multiplexer (total 9n gates)– 3 n-bit 2-to-1 multiplexers
• Input connections to MUX– 2n * 3
– Single bus• 3n AND & n OR gates (total 4n gates)
– 3-to-1 multiplexer and parallel load registers
• Input connections to MUX– 3n
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer Three-State Bus
– A bus system can be constructed with three-state buffers (instead of MUX) – form a bit line of bus, & bus is implemented using only one level of logic gates– signals can travel in two directions on a three-state bus
Bi-directional input-output lines
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer
Comparison with MUX-based BUS system– The number of logic gate
• MUX-based BUS: # of sources = # of input of OR– Multiple levels of OR gates– Increasing delay
• 3 state buffer BUS– Only one level of logic gates
– Data connection to registers• MUX-based BUS: 2*n per register
• 3 state buffer BUS: n per register– Bi-directional input-output lines
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer
Memory Transfer– a memory word is symbolized by the letter M
– Read: DR M[AR] (DR: data register, AR: address register)
– Write: M[AR] DR
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7.5 Bus-Based Transfer7.5 Bus-Based Transfer write operation: M[A1] D2
– select input for addr. bus decoder: 01 (A1)– select input for data bus source decoder: 10 (D2)– select input for data bus destination decoder:
11(Write)
read operation: D1 M[A2]– select input for address decoder: 10 (A2)– select input for data bus source decoder: 11 (Read)– select input for data bus destination decoder: 01 (D1)
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7.6 Datapaths7.6 Datapaths
Datapath – combination of a set of register
s with a shared ALU and interconnecting paths
simple bus-based datapath with 4 registers, an ALU & a shifter
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7.6 Datapaths7.6 Datapaths
Registers interact by a direct transfer of data, as well as perform various microoperations– each register is connected to two sets of multiplexers to form input
buses A and B– selection inputs select one register for the corresponding bus– A & B buses are applied to the inputs of a common ALU– select inputs of the ALU determine the particular operation– destination register is selected by a decoder with destination select– a number of status bits in ALU
• useful for checking certain relationships after ALU operation
• carry C, overflow V, zero status Z, sign status S
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7.6 Datapaths7.6 Datapaths
– Ex) R1 R2 + R3
1. A select: contents of R2 onto bus A 2. B select: contents of R3 onto bus B 3. G select: ALU operation A + B 4. MF select: ALU output to MUX F output 5. MD select: MUX F output onto bus D 6. Destination select: select R1 7. Load enable of R1
When the next positive clock edge arrives, the binary data on Bus D is loadedinto the destination register.
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
– ALU is a combinational circuit that performs a set of basic arithmetic & logic microoperations
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
– a typical 4-bit ALU• 4 data inputs from A & B, and 4 data outputs to F
– mode select input S2 distinguishes between arithmetic & logic operations• 2 function select inputs S1 & S0 specify the particular operations• possible to specify 4 arithmetic & 4 logic operations
– input & output carries have meaning only during an arithmetic operation• input carry Cin is used as a 4th selection variable for arithmetic ops
– Three stages in the design of a typical ALU1) design of arithmetic section2) design of logic section3) combined to form the ALU
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU) Arithmetic Circuit
– basic component of an arithmetic circuit is "Parallel Adder"
– G = X + Y + Cin
• X: the n-bit binary number at the A inputs• Y: the n-bit binary number at the B inputs
• Cin: input carry
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
– 2 select lines S1 & S0
• obtain a variety of arithmetic operations
– the combinational circuit can be implemented with n MUXes0, Bi, Bi', & 1
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
4-bit Arithmetic circuit– Y = Bi S0 + Bi' S1
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
Logic Circuit– 4 basic operaitons: AND, OR, XOR, & complement
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
Arithmetic/Logic Unit– ALU = arithmetic circuit + logic circuit– one stage of ALU
• repeat n times for an n-bit ALU
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7.7 Arithmetic Logic Unit (ALU)7.7 Arithmetic Logic Unit (ALU)
8 arithmetic & 4 logic operations
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7.8 The Shifter7.8 The Shifter
What to do
– shift the value on Bus B, placing the result on an input of MUX F
– provide the shift operations not available in ALU
• right shift & left shift
– a bidirectional shift register with parallel load
Procedure
– 1st clock: loads the output of Bus A into the shift register
– 2nd clock: performs the shift
– 3rd clock: transfers the data to the selected destination
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7.8 The Shifter 7.8 The Shifter – 4bit basic shifter– 4bit basic shifter
– selection variable S
S=0, right shift (IR: serial input)
S=1, left shift (IL: serial input)
– to shift an operand by M>1 bit positions• perform m 1-bit position shifts taking m clock cycles
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7.8 The Shifter 7.8 The Shifter – Barrel shifter– Barrel shifter
Barrel Shifter– data are shifted more than once during a single operation– shift input data bits by a number of positions – a cyclic rotation
– consist of 4 multiplexers with 2 common selection lines S1 & S0– a barrel shifter with 2*n input & output lines
• requires 2*n multiplexers• each having 2*n data inputs and n selection inputs
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7.8 The Shifter 7.8 The Shifter – Barrel shifter– Barrel shifter
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7.9 Datapath Representation7.9 Datapath Representation
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7.9 Datapath Representation7.9 Datapath Representation
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7.10 The Control Word7.10 The Control Word
– The selection variables for the datapath• control the microoperations
executed within the datapath for any given clock pulse
• control the buses, the ALU, the shifter, & the destination register
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7.10 The Control Word7.10 The Control Word Register file of seven registers R1 through R7;
– Outputs go through two sets of multiplexers to select input to ALU– Input data from an external source are selected by the same MUXes– Output of ALU goes through a shifter & into output bus;– Output from the shifter is transferred to any one of the registers & can also be
directed to an external destination ALU provides the binary data for the four status bits: C, Z, S, V Control words of 16 binary selection inputs
– 3 bits in DA: select a destination register;– 3 bits in AA & BA: select source registers for input of ALU;– 1 bit in MB: register or constant;– 5 bits in FS: select one of 14 operations in ALU;– 1 bit in MD: function unit output or the data on DATA– 1 bits in RW: select register is written or not;
17-bit control word specifies a particular microoperation
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7.10 The Control Word7.10 The Control Word specified functions
– functions of all selection variables
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7.10 The Control Word7.10 The Control Word
(ex1) R1 R2 + R3' + 1 - DA: R1 001 - AA: R2 010 - BA: R3 011 ==> 001 010 011 0 00101 0 1 - MB: register 0 - FS: A+B'+1 00101 - MD: Function 0 - RW: Write 1
(ex2) R4 sr R6 - DA: R4 100 - AA: R6 110 - BA: - 000 ==> 100 110 000 0 10001 0 1 - MB: register 0 - FS: sl A 10001 - MD: Function 0 - RW: Write 1
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7.10 The Control Word7.10 The Control Word
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7-11 Pipelined Datapath7-11 Pipelined Datapath
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7-11 Pipelined Datapath7-11 Pipelined Datapath
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7-11 Pipelined Datapath7-11 Pipelined Datapath
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7.10 The Control Word7.10 The Control Word
many microoperations can be generated in the processor unit– most efficient way to generate control words
“store them in memory unit”• Control memory
• Microprogramming (Chap 8)