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Slide 2 COMP375 Computer Architecture and Organization Senior Review Slide 3 Goals for COMP375 Apply knowledge of computing and mathematics to solve problems of design and performance analysis Understand how the architecture affects program performance Explain the design decisions of RISC and advanced architectures Make informed decisions in the selection of computers Understand the basics of computer hardware and how software interacts with computer hardware Slide 4 Intel Performance Architectural Improvements Slide 5 So What? When you buy a computer, processor clock speed is not the sole determining factor of processing capability. Recently processor clock speeds have decreased while potential performance has continued to increase. Slide 6 Basic Computer Components CPU I/O Controller I/O Device Memory Bus Cache Slide 7 Instruction Cycle Fetch the instruction from the memory address in the Program Counter register Increment the Program Counter Decode the type of instruction Fetch the operands Execute the instruction Store the results Slide 8 Simple CPU Slide 9 Instruction Fetch bu s IR IR adr bus res ult bus A L U res ult A L U fun bus opr nd bus PC PC bus bus R1 R1 bus bus R2 R2 bus bus M A R bus M B R M B R bu s Mem func XXread wait XX Slide 10 Memory Hierarchy Caching Virtual Memory Slide 11 Locality of Reference Temporal Locality A memory location that is referenced is likely to be accessed again in the near future. Spatial Locality Memory locations near the last access are likely to be accessed in the near future. Slide 12 So What? User programs do not directly control processor cache or virtual memory, but they have a big impact on their efficiency. Programs that access memory with similar addresses will run faster than programs that have unpredictable varying accesses. Slide 13 Address Translation Slide 14 Steps in Accessing Memory Compute effective address Split effective address into page number and offset Use page number as an index into the page table. (Check if too big.) If Resident bit is clear, generate a page fault. if Resident bit is set, get page address from the page table. Slide 15 Steps in Accessing Memory Concatenate page address with offset to create the physical address. For direct L1 cache, get the middle bits of the physical address to determine which line to check. Check the tag value of the specified line to see if it matches the upper bits of the physical address. If there is a match, return the specified value from the cache. Slide 16 Steps in Accessing Memory If the tag field does not match, check the second level cache. For n-way set associative L2 cache, get the middle bits of the physical address to determine which set to search. Search the tag values of all n lines in the specified set to see if any match the upper bits of the physical address. If there is a match, return the specified value from the cache. Slide 17 Steps in Accessing Memory If none of the n tag fields for the set match the upper bits of the physical then determine which of the lines in the specified set of the L2 cache is the oldest. This line will hold the new data. If this line is dirty, write this block to RAM. Get the physical address data from RAM. Copy the block of data from RAM into the L1 and L2 caches. Send the CPU the data requested. Slide 18 So What? All programs think they start at address zero, but they dont. The OS can fit lots of big programs in tiny memory, although performance may suffer. An Execute Disable bit in the page table prevents many stack overflow exploits. Slide 19 Disk Performance Parameters Disk read or write involves three factors 1.Seek time time it takes to position the head at the desired track 2.Rotational delay or rotational latency time its takes for the beginning of the sector to reach the head 3.Transfer time time required for the data to move under the head Slide 20 Performance Example How long does it take to read two consecutive 512 byte blocks from the disk? Average Seek time8.9 ms Average Rotational Delay 4.2 ms Transfer time Total13.4 ms Slide 21 So What? The seek time is long compared a simple block transfer time. It is more efficient to read and write large blocks. One track or cylinder at a time is best. CDs are slow for small files even if you have a 1,000,000X CD drive Slide 22 RISC Processor Features Pipelined Simple instructions Few instructions No microcode Few addressing modes Load/Store architecture Sliding register stack Delayed branches Fast Slide 23 Pipelining Slide 24 Hazards A hazard is a situation that reduces the processors ability to pipeline instructions. Resource When different instructions want to use the same CPU resource. Data When the data used in an instruction is modified by the previous instruction. Control When a jump is taken or anything changes the sequential flow. Slide 25 COMP375 Senior Exam The senior exam questions are very similar to COMP375 exam questions. You will probably want to bring a calculator to the exam.