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Multiprocessors and Thread-Level Parallelism
Symmetric Shared-Memory Architectures
“The use of large, multilevel caches can substantially reduce the memory bandwidth
demands of a processor.”
Hennessy and Patterson
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Hardware Designers Motivation
• The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.
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Multiprocessors Cache Coherence
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Basic Schemes for Enforcing Coherence
Directory Based
Snooping
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The Snooping Protocols
Write Invalidate Protocol
Write Broadcast Protocol
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Write Invalidate Protocol
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An Example Protocol
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An Example Protocol
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An Example Protocol
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SSM and Snooping Limitations
• As the number of processors in a multiprocessor grows, or as the memory demands of each processor grow, any centralized resource in the system can become a bottleneck.
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SSM and Snooping Limitations
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Implementing Snoopy Cache Coherence
Race Situation: Have a winner is more important than who wins.
Broadcast for all misses and some basic properties of the interconnection network.
Ability to restart the miss handling of the loser in a race.
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Thank you!
Author: Prof. Sergio Takeo, Marcelo Arbore.
Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4th Ed. Morgan Kaufmann Publishers.
“The use of large, multilevel caches can substantially reduce the memory bandwidth
demands of a processor.”
Hennessy and Patterson