Niloy Ganguly Biplab K Sikdar P Pal Chaudhuri
Presented byPresented by
Niloy GangulyNiloy Ganguly
Indian Institute of Social Welfare and Business Indian Institute of Social Welfare and Business Management. Calcutta 700 073Management. Calcutta 700 073
Email : [email protected] : [email protected]
Design of An On-Chip Test Design of An On-Chip Test Pattern Generator Without Pattern Generator Without
Prohibited Pattern Set (PPS)Prohibited Pattern Set (PPS)
ASP-DAC/VLSI Design 2002 2
• Introduction and OverviewIntroduction and Overview• Cellular Automata PreliminariesCellular Automata Preliminaries• Proposed Design of TPG Proposed Design of TPG • Experimental Results Experimental Results • Concluding RemarksConcluding Remarks
The Coverage
ASP-DAC/VLSI Design 2002
Problem Definitions
• Prohibited Pattern Set (PPS) – A set of Prohibited Pattern Set (PPS) – A set of patterns input of which sents the system patterns input of which sents the system into an unstable state.into an unstable state.
• Example : Toggle State of a flip flopExample : Toggle State of a flip flop• Design a TPG with the following featuresDesign a TPG with the following features
– It avoids the generation of such PPS It avoids the generation of such PPS – It maintains the randomness and fault It maintains the randomness and fault
coverage of a Pseudo Random Pattern coverage of a Pseudo Random Pattern Generator Generator
– Side by side it doesn’t add to any Side by side it doesn’t add to any hardware costhardware cost
ASP-DAC/VLSI Design 2002
Problem Definitions
• Non Max Length GF(2) Cellular Automata Non Max Length GF(2) Cellular Automata is employed to obtain the design criteriais employed to obtain the design criteria
• Design the CA in such a way so that it Design the CA in such a way so that it has large cycles free from PPShas large cycles free from PPS
• Design a TPG with the following featuresDesign a TPG with the following features– It avoids the generation of such PPS It avoids the generation of such PPS – It maintains the randomness and fault It maintains the randomness and fault
coverage of a Pseudo Random Pattern coverage of a Pseudo Random Pattern Generator Generator
– Side by side it doesn’t add to any Side by side it doesn’t add to any hardware costhardware cost
ASP-DAC/VLSI Design 2002
Clock
Combinational logic
CL
DFlip - Flop Q
From
left neighborFrom right neighbor
Cellular Automata MachineA powerful computing and modeling toolA powerful computing and modeling tool• 50’s - J von Nuemann50’s - J von Nuemann80’s - Wolfram80’s - Wolfram• A CA consists of an array of cellsA CA consists of an array of cells• A CA cell is essentially a memory element A CA cell is essentially a memory element
(D Flip flop) with some combinational (D Flip flop) with some combinational logic - an XOR and/or XNOR Gate logic - an XOR and/or XNOR Gate (additive) (additive)
ASP-DAC/VLSI Design 2002
Clock
Combinational logic
CL
DFlip - Flop Q
From
left neighborFrom right neighbor
Cellular Automata MachineA powerful computing and modeling toolA powerful computing and modeling tool• The cell is updated at every clock cycle The cell is updated at every clock cycle • The state of the cell is dictated by the The state of the cell is dictated by the
immediate neighborsimmediate neighbors• Typically termed as Two State Three Typically termed as Two State Three
neighborhood Cellular Automataneighborhood Cellular Automata
ASP-DAC/VLSI Design 2002
• The operation of XOR and XNOR rules can be The operation of XOR and XNOR rules can be conceived as mod two multiplication and conceived as mod two multiplication and additionaddition
• The operations thus can be mapped to The operations thus can be mapped to operations of Galois Field(2) giving rise to operations of Galois Field(2) giving rise to GF(2) GF(2) Cellular AutomataCellular Automata..
• The CA is characterized by a T matrix which is The CA is characterized by a T matrix which is essentially the dependency matrixessentially the dependency matrix
GF(2) Cellular Automata
1 0 0 0 01 0 0 0 00 1 1 0 00 1 1 0 0
T T = = 0 1 1 1 0 0 1 1 1 0 F =F = [1 0 1 0 1][1 0 1 0 1]0 0 0 1 1 0 0 0 1 1
0 0 0 0 10 0 0 0 1
ASP-DAC/VLSI Design 2002
• For 3-neighborhood CA, we have a band For 3-neighborhood CA, we have a band matrix matrix
• An XNOR CA is characterized by a An XNOR CA is characterized by a inversion vector F indicating the cells inversion vector F indicating the cells where XNOR operation has been where XNOR operation has been performed performed
GF(2) Cellular Automata
1 0 0 0 01 0 0 0 00 1 1 0 00 1 1 0 0
T T = = 0 1 1 1 0 0 1 1 1 0 F =F = [1 0 1 0 1][1 0 1 0 1]0 0 0 1 1 0 0 0 1 1
0 0 0 0 10 0 0 0 1
ASP-DAC/VLSI Design 2002
State Transition Behavior
• Group CA - All states lie on some CycleGroup CA - All states lie on some Cycle
0
9 15
613
7 12
3 14
11
5
2 8
1 4
10Non Maximum Length CA
1
21163 135
12 15 14 4 810 7
9
0
Maximum Length CA
Our TPG Design is based on this type of CA
ASP-DAC/VLSI Design 2002
2943
1112110
0151413
5678
Equal Length CA
State Transition Behavior
• Additive variant of Group CAAdditive variant of Group CA
Non Group CA : Cyclic/ Non cyclic and Non Reachable States
5
15
10
0
4
14
11
1
2
7
13
8
3
6
12
9
Our TPG Design is based on this type of CA
ASP-DAC/VLSI Design 2002
Overview of Design
Given PPSGiven PPS00001100000110
00000100000010
00010010001001
00001110000111
PPS = 0001111PPS = 0001111
00101000010100
11011011101101
10110011011001
01001000100100
00100010010001
Choose a Non Choose a Non Maxlength CAMaxlength CA
ASP-DAC/VLSI Design 2002
Overview of DesignCriterion for choosing Criterion for choosing
Non-Max Length CANon-Max Length CA• Large cycle of Large cycle of
length close to a length close to a Max length CycleMax length Cycle
• All members of PPS All members of PPS fall in smaller cyclesfall in smaller cycles
Target Cycle(TC)
Redundant Cycle(RC)
Choose a Non Choose a Non Maxlength CAMaxlength CA
ASP-DAC/VLSI Design 2002
Overview of DesignCriterion for choosing Criterion for choosing
Non-Max Length CANon-Max Length CA• Large cycle of Large cycle of
length close to a length close to a Max length CycleMax length Cycle
• All members of PPS All members of PPS fall in smaller cyclesfall in smaller cycles
Target Cycle(TC)
Redundant Cycle(RC)
In Practical In Practical Situation all Situation all members of PPS members of PPS don’t fall in RC.don’t fall in RC.
Then Sacrifice a Then Sacrifice a small part of TCsmall part of TC
Dmax
ASP-DAC/VLSI Design 2002
Design of TPG without PPS
•C1: Find n-cell CA having RCs and TC
•C2: Let most of the members of PPS fall in RC
•C3: Find Dmax in TC to avoid remaining PPSAcceptable Criteria•TC 2n-1 for n > 16
•TC .75 x 2n for n 16
•Dmax 10% of TC
ASP-DAC/VLSI Design 2002
Method of selecting RC
Design Simplification : Form CA with 2 RCs besides the all zero cycle
Value of RCs to form big TC
CA Size n 7
Divide n = n1 + n2 7
= 4 + 3
n1 and n2 are mutually
prime
Cycle Length RC1 = 2n1 –1
15
Cycle Length RC2 = 2n2 –1
7
Cycle Length TC = 2n1 –1 x
2n2 –1
105
ASP-DAC/VLSI Design 2002
Selection of n1 and n2• Each RC forms a vector subspaceEach RC forms a vector subspace• Evolve strategy to partition PPS in two Evolve strategy to partition PPS in two
vector subspacevector subspace• Randomly partition PPS into two sets S1 Randomly partition PPS into two sets S1
and S2 and S2 • Calculate rank of S1(r1) and S2(r2) Calculate rank of S1(r1) and S2(r2) • Select a partition where Select a partition where
– r1 + r2 r1 + r2 n n – r1 and r2 are mutually primer1 and r2 are mutually prime– The acceptable criterion of TC is metThe acceptable criterion of TC is met
• Set n1 = r1 and n2 = r2Set n1 = r1 and n2 = r2• T matrix can be designed with maximum T matrix can be designed with maximum
member of PPS falling in smaller cyclesmember of PPS falling in smaller cycles
ASP-DAC/VLSI Design 2002
Heuristic to Design the TPG
ProblemProblem
Since a CA forms a Band Matrix all linear Since a CA forms a Band Matrix all linear transform is not supported by CAtransform is not supported by CA
Randomly Synthesize a non-maximal length group CA
Method - illustrated in paper CA Toolkit - http://ppc.becs.ac.inMaximum member of PPS falls in RCs
•Find Dmax of rest of PPS covered by TC
•Select CA with acceptable criteria
ASP-DAC/VLSI Design 2002
Heuristic to Design the TPG
Acceptable CriteriaAcceptable Criteria
Dmax – 10% of TCDmax – 10% of TC
Randomly Synthesize a non-maximal length group CA
Method - illustrated in paper CA Toolkit - http://ppc.becs.ac.inMaximum member of PPS falls in RCs
•Find Dmax of rest of PPS covered by TC
•Select CA with acceptable criteria
ASP-DAC/VLSI Design 2002
Experimental Observation-I• Real data of PPS is not available• PPS randomly generated, no. of prohibited
patterns assumed 25• For a particular n, 10 different PPS are
considered
# Cell
PPS TC RCs PPS(%) in RCs
Dmax Avg # iteration
9 9 465 15, 31 75 48 25 14 15 8191 1,8191 95 106 23 24 25 223-1 1, 223-1 84 18121 14 32 25 * (215-1), (217-1) 89 33571 16 43 25 * (221-1), (222-1) 93 20211 15
* Indicates that the cycle length approx. 2n – 2n/2
ASP-DAC/VLSI Design 2002
Experimental Observations -II
Study of randomness property
Platform used is DiehardC
Compared with corresponding maximal length CA
Random TestRandom Test n=24n=24
Max TPGMax TPGn=32n=32
Max TPGMax TPGn=48n=48
Max TPGMax TPG
Overlap SumOverlap Sum pass passpass pass pass passpass pass pass passpass pass
3D Sphere3D Sphere pass passpass pass pass passpass pass fail failfail fail
B’day SpacingB’day Spacing fail failfail fail fail failfail fail fail failfail fail
Overlap 5-Overlap 5-permutpermut
fail failfail fail fail failfail fail pass passpass pass
DNADNA fail failfail fail fail failfail fail pass failpass fail
SqueezeSqueeze fail passfail pass fail failfail fail pass failpass fail
ASP-DAC/VLSI Design 2002
Experimental Observations -III
Fault coverage of the proposed design (Compared with MaxLength CA)
Fault Simulator used : Cadence `verifault’
Circuit Name
PI Test Vector Max Len TPG
C432m C499m C432
36 41 36
4000 2000 400
83.57 97.78 98.67
83.96 97.22 99.24
S641 S1269 S1196 S1238 S1423 S3384 S3271 S5378 S35932
35 18 14 14 17 43 26 35 35
2000 1200 12000 10000 15000 8000 10000 8000 14000
85.63 99.18 94.85 89.67 56.50 91.78 98.99 67.63 61.91
85.08 99.48 94.04 89.08 53.60 91.60 98.99 67.72 59.82
ASP-DAC/VLSI Design 2002
Conclusion
• Based on analytical framework of CA theory, the real life problem of PPS is addressed
• Solution does not incur extra overhead
• Fault efficiency of the TPG is as good as the existing designs
ASP-DAC/VLSI Design 2002 23
Thank youThank you
Niloy GangulyNiloy Ganguly