![Page 1: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/1.jpg)
Device Interface Board for Wireless LAN Testing
TeamMay 06-15
ClientECpE Department
Faculty AdvisorDr. Weber
Team MembersMatthew Dahms – EEJustine Skibbe – EEJoseph Chongo – EESrisarath Patneedi – CprE
December 06, 2005
![Page 2: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/2.jpg)
Presentation Outline Project Overview
Introduction Problem Statement Assumptions and Limitations
System Considerations User Considerations
End-Product Description
Overview of Existing Work May 05-29 Team’s
Accomplishments Parallel-Serial Conversion Transmitters and Receivers FPGA
Project Activities Technology Considerations Present Accomplishments
Hardware Software
Planned Activities Design
Closure Materials Schedule Closing Summary
![Page 3: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/3.jpg)
Definitions ASK modulation – Amplitude shift keying. In this modulation scheme the
amplitude is varied to indicate logic 0’s and 1’s DUT – Device under test (positive edge D flip-flop) Header – Preamble bits sent prior to the sending of information in a data packet
time
1 0 1 0 D3 D2 D1 D0
Data Packet
Header
voltage
Data Packet and Header
![Page 4: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/4.jpg)
Definitions (cont.) NRZ – Non-return to zero. Using NRZ, a logic 1 bit is
sent as a high value and a logic 0 bit is sent as a low value.
PLL – Phase-locked loop RZ – Return to zero. This is the opposite of NRZ data.
The signal state is determined by the voltage during the first half of each data binary digit. The signal returns to a resting state (called zero) during the second half of each bit.
![Page 5: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/5.jpg)
Project Overview
![Page 6: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/6.jpg)
Acknowledgement
Dr. Weber Nathaniel Gibbs (GibbaHertz) Jason Boyd
![Page 7: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/7.jpg)
Introduction
Teradyne Integra J750Digital TesterDonated to Iowa State
Desire to test wireless chips using J750 May 05 project was first step toward that goal
Created send/receive network to test digital device remotely
Programmed FPGA for simple tests
Teradyne Integra J750
![Page 8: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/8.jpg)
Project Overview Problem Statement
S/R network exists but no method is available for clock recovery
Must develop a clock recovering circuit and integrate it with current system
Investigate realistic range of operation for the wireless interface
![Page 9: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/9.jpg)
Project Overview System Constraints
The Teradyne J750 must operate within +/- 3° C of calibrated temperature (30° C).
The maximum rate at which data may be sent is at 115.2 Kbps.
The Tx and Rx networks communicate at 916.5 & 916MHz. Nearby wireless signals at similar frequencies may disrupt the setup.
The IG-XL software shall be used in writing the test data sets for the Teradyne J750.
Only one FPGA will be provided.
![Page 10: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/10.jpg)
Project Overview Users Assumptions
The user has knowledge in electrical and/or computer engineering.
The user has previous experience testing circuits with the Teradyne J750.
The user has read the Teradyne J750 instruction manual and will observe all necessary safety precautions as prescribed in that manual.
Intended Uses Functional test of a digital device (Future) Wireless chipset test
![Page 11: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/11.jpg)
Project Overview End-Product and Other Deliverables
Wireless interface with clock recovery circuit Demonstration of wireless test Update the manual for wireless test operation
Cover page of wireless manual
![Page 12: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/12.jpg)
Overview of Existing Work
![Page 13: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/13.jpg)
Overview of Existing Work May 05-29 Accomplishments
Parallel-Serial Conversion Transmitters and Receivers Processing Device
![Page 14: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/14.jpg)
Overview of Existing Work
Parallel-Serial Conversion Needed to convert parallel test data into serial test
data Chose to use a shift register
Shift Register attached to daughterboard
![Page 15: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/15.jpg)
Overview of Existing Work
Transmitters and Receivers
TRM1
TRM2
RCV1
RCV2
![Page 16: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/16.jpg)
Overview of Existing Work
FPGAUsed to recognize header signal Identifies test dataPresents test data to DUTPresents reply to S/R network
![Page 17: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/17.jpg)
Final System Setup
![Page 18: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/18.jpg)
Project Activities
![Page 19: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/19.jpg)
Project Activities Project Definition
Part of the May 05 team’s project definition was to include a clock recovery circuit, but due to timing constraints was unable to do so.
May 06 goal is to integrate a PLL for clock recovery with the existing network.
![Page 20: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/20.jpg)
Project Activities
Design
![Page 21: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/21.jpg)
Project Activities
Technology ConsiderationsManchester vs. PLLNRZ to RZ ConversionSoftware
![Page 22: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/22.jpg)
Project Activities
Original Signal Value SentLogic 0 0 to 1 (upward transition at
bit centre)
Logic 1 1 to 0 (downward transition at bit centre)
The waveform for a Manchester encoded bit stream carrying the sequence of bits 110100
Manchester Encoding
![Page 23: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/23.jpg)
Manchester EncodingVery easy to implementClock phase and frequency are both present Too fast for current transmitters and
receivers!
Project Activities
![Page 24: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/24.jpg)
Project Activities
Phase Locked LoopMust be “trained” Test data must follow a training signalMore difficult to implementDon’t have to build new transmitters and
receivers
![Page 25: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/25.jpg)
Project Activities
Present AccomplishmentsHardware
Previous team’s project setup and tested PLL Monostable Multivibrators
Software Prototype control software for FPGA written IG-XL test template written
![Page 26: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/26.jpg)
Project Activities
Internal Components of a PLL
![Page 27: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/27.jpg)
Project Activities
Phase DetectorType I – XOR *Type II – Generates lead or lag pulses
Voltage Controlled Oscillator (VCO)Centered at 115.2 KHzFrequencies too far off of center frequency
will not lock
![Page 28: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/28.jpg)
Project Activities
![Page 29: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/29.jpg)
Project Activities
Monostable MultivibratorsChosen to convert NRZ data to RZ dataMust use an external RC combination to
specify pulse widths
![Page 30: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/30.jpg)
Project Activities
NRZ to RZ converter circuit with I/O waveforms
![Page 31: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/31.jpg)
Project Activities
SoftwareFPGA serves as “brains” of systemVerilog chosen to program FPGAPrototype code complete
![Page 32: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/32.jpg)
Project Activities
![Page 33: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/33.jpg)
![Page 34: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/34.jpg)
![Page 35: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/35.jpg)
![Page 36: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/36.jpg)
![Page 37: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/37.jpg)
Project Activities Planned Design/Test Activities
Build and Test NRZ to RZ Converter Build and Test PLL Circuitry Integrate Clock Recovering Circuitry Modify FPGA Code as Necessary Test Functional Range of Wireless Interface
![Page 38: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/38.jpg)
NRZ/RZ
PLL
![Page 39: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/39.jpg)
Closure Materials
![Page 40: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/40.jpg)
Closure MaterialsSchedule
Expected
Actual
Updated
![Page 41: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/41.jpg)
Closure Materials
Expected
Actual
Updated
Schedule (cont.)
![Page 42: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/42.jpg)
Closing Materials Lessons Learned
What technical knowledge was gained? FPGA implementation Teradyne Integra J750 usage Clock recovery methods System integration
![Page 43: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/43.jpg)
Closing Materials
Lessons Learned What went well?
May05 System still works! Teamwork Learned to work in arctic environments
(19 degrees C inside Teradyne lab)
What did not go well? Locating May05 equipment Initial Teradyne J750 setup and test Uploading program to FPGA FPGA inputs pins
![Page 44: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/44.jpg)
Closing Materials Closing Summary
Problem – Integrate clock recovery circuitry into current system
Solution Use PLL for clock recovery Modify FPGA program to incorporate new
components
![Page 45: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/45.jpg)
Questions?Questions???Questions???
![Page 46: Device Interface Board for Wireless LAN Testing](https://reader031.vdocuments.net/reader031/viewer/2022012919/568148a8550346895db5bb53/html5/thumbnails/46.jpg)
Thank You