ELEC1041 – Tut Sequential 1
Digital Electronics
Tutorial: Sequential Logic
Solutions
ELEC1041 – Tut Sequential 2
Problem #1
In lecture, we presented an R-S latch based on cross-coupled NOR gates. It is also possible to construct an R’-S’ latch using cross-coupled NAND gates.
(a) Draw the R’-S’ latch, labeling the R’ and S’ inputs and the Q and Q’ outputs.
(b) Show the timing behavior across the four configurations of R’ and S’. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R’ = S’ = 0.
(c) Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch.
(d) What is the characteristic equation of the R’-S’ latch.
(e) Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only.
ELEC1041 – Tut Sequential 3
Problem #1 Solution (1/5)
(a) Draw the R-S latch, labeling the R and S inputs and the Q and Q outputs.
Q
Q
S
R
ELEC1041 – Tut Sequential 4
Problem #1 Solution (2/5)
(b) Show the timing behavior across the four configurations of R and S. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R=S=0.
Reset Set ForbiddenRace
S
R
Q
Q
Reset HoldHold ForbiddenSet
Q
Q
S
R
ELEC1041 – Tut Sequential 5
Problem #1 Solution (3/5)
(c) Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch.
Q Q0 1
Q Q1 0
Q Q1 1
Q Q0 0
SR=00SR=11S'R'=11
SR=01
SR=10
SR=11SR=01
SR=11SR=10
SR=00 SR=00
SR=01SR=10
SR=10 SR=01
SR=00
possible oscillationbetween states 00 and 11
ELEC1041 – Tut Sequential 6
Problem #1 Solution (4/5)
(d) What is the characteristic equation of the R-S latch.
Q(t+)
S
R
Q(t)
S R Q(t) Q(t+)1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 10 0 0 X0 0 1 X
hold
reset
set
not allowed characteristic equationQ(t+) = S + R Q(t)
X 1
X 1
0 0
1 0Q(t)
R
S
Break feedback path
Q
Q
S
R
ELEC1041 – Tut Sequential 7
Problem #1 Solution (5/5)
(e) Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only.
Control when R and S inputs matter
The slightest glitch on R or S while enable is high could cause change in value stored
Q
Q
S
R
R
S
Enable
Q
Q
ELEC1041 – Tut Sequential 8
Problem #2
Consider a D-type storage element implemented in five different ways:
(a) D-latch (i.e., D wired to the S-input and D’ wired to the R-input of an R-S latch);
(b) Clock Enabled D-latch;
(c) Master-Slave Clock Enabled D-Flip-flop;
(d) Positive Edge-triggered Flip-flop;
(e) Negative Edge-triggered Flip-flop;
Complete the following timing charts indicating the behavior of these alternative storage elements. You can ignore set-up and hold time limitations (assume all constraints are meant):
ELEC1041 – Tut Sequential 9
Problem #2 Solution
(1) output from D-latch changes as D changes regardless of the clock.(2) output from clocked D-latch changes as D does only when the clock is high.(3) output from D M/S FF are the samples taken from the input at the falling edge of the clock.(4) output from positive edge FF changes relative to D at the rising edge of the clock.(5) output form negative edge FF are the samples taken from the input at the falling edge of the clock (same as part 3).
ELEC1041 – Tut Sequential 10
Problem #3
Complete the timing diagram for this circuit.
ELEC1041 – Tut Sequential 11
Problem #3 Solution
Complete the timing diagram for this circuit.
Toggles when T = 1 at the rising edge of the clock
ELEC1041 – Tut Sequential 12
Problem #4
Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101
ELEC1041 – Tut Sequential 13
Problem #4 Solution
Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101
EN
DCBALOADCLKCLR
RCOQDQCQBQA
"1"
"0"“1"“1"“1"
ELEC1041 – Tut Sequential 14
Problem #5
You as a designer at XILION Micro Devices, have been asked to redesign part of your system to run at double the clock frequency. However, to maintain the compatibility with other parts of the system you like to keep the same clock frequency. What would you do to impress your Boss?
Discuss all timing constraint in your design
ELEC1041 – Tut Sequential 15
Problem #5 Solution
One way is to double of the clock frequency locally, or put it in another way make your flip flop to be both positive and negative edged triggered.
CLOCK
B
CLK
1. High Width of “CLK” should be larger than that required by the Flip FlopThis can be controlled by the number of invertors (odd) before the XNOR gate. 2. Period of “CLK” should be larger than the (set up time + propagation Delay) of flip flop.
Conditions:Clk period
Flip flop sample on both edges BCLOCK
ELEC1041 – Tut Sequential 16
Problem #6
Complete the count sequence table for the following shift register circuit.
Q1 Q2 Q3
Q4 Q1 Q2Q3Q4
0 0 0 0
0 0 0 0
ELEC1041 – Tut Sequential 17
Problem #6 Solution
Complete the count sequence table for the following shift register circuit.
Q1 Q2 Q3
Q4 Q1 Q2Q3Q4
01110110
00111011
00011101
00001110
01010000
00101000
10010100
11001010
ELEC1041 – Tut Sequential 18
Problem #7
CLK
A
B
C
D
LOAD
CLR
P
T
Q A
Q B
Q C
Q D
RCO 12 13 14 15 0 1 2
Clear Load Count Inhibit
Consider the counter x74_163 from the xilinx library. Complete the timing diagram Below: (Note: LOAD and CLR are active low. P & T should be high to enable the counter
QAQB
QCQD
163RCO
PT
ABCD
LOAD
CLR
CLK
ELEC1041 – Tut Sequential 19
Problem #7 Solution
CLK
A
B
C
D
LOAD
CLR
P
T
Q A
Q B
Q C
Q D
RCO 12 13 14 15 0 1 2
Clear Load Count Inhibit
Indicates Undefined
P & T should be High to enable count
Clear
Load
ELEC1041 – Tut Sequential 20
Problem #8
Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000.
ELEC1041 – Tut Sequential 21
Problem #8 Solution (1/2)
Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000.
ELEC1041 – Tut Sequential 22
Problem #8 Solution (2/2)
ELEC1041 – Tut Sequential 23
Problem #9
Design the logic for a 3-bit counter that follows the following sequence: 001, 010, 100, 101, 110, 001, and repeat. Design the counter so that it is self-starting, i.e., whatever state it comes up in, it will eventually get into the sequence as shown above.
ELEC1041 – Tut Sequential 24
Problem #9 Solution
001
010
100
101
110
000
011
111 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 0 0 1
+ + +
Q2 = Q2 Q1 + Q2Q1
+
Q1 = Q1 Q0
+Q0 = Q1 Q0 + Q2Q1
+
ELEC1041 – Tut Sequential 25
Problem #10
Consider 3 bit Johnson Counter below. Derive it state transition table and diagrams
ELEC1041 – Tut Sequential 26
Problem #10 Solution
000
001
010
011
111
110
101
100
0 0 0 0 0 10 0 1 0 1 10 1 0 1 0 00 1 1 1 1 01 0 0 0 0 01 0 1 0 1 01 1 0 1 0 01 1 1 1 1 0
Q2Q1Q0 Q2Q1Q0
+ + +
ELEC1041 – Tut Sequential 27
Problem #11
ELEC1041 – Tut Sequential 28
Problem #11 Solution (1/2)
ELEC1041 – Tut Sequential 29
Problem #11 Solution (2/2)
1 0
0 1
0 x
1 xX
q1
q0D0
0 0
0 1
0 x
1 xX
q1
q0D1
0 1
1 0
1 x
1 xX
q1
q0Z
ELEC1041 – Tut Sequential 30
Problem #12
ELEC1041 – Tut Sequential 31
Problem #12 Solution (1/3)
ELEC1041 – Tut Sequential 32
Problem #12 Solution (2/3)
ELEC1041 – Tut Sequential 33
Problem #12 Solution (3/3)
0 0 x 00 0 x x0 0 x x0 1 x 0
q2D2
q1
q0
X
0 0 x 11 0 x x1 1 x x0 0 x 0
q2D1
q1
q0
X
0 1 x 00 1 x x1 0 x x1 0 x 0
q2D0
q1
q0
X
0 1 x 01 1 x x1 0 x x0 1 x 0
q2Z
q1
q0
X
ELEC1041 – Tut Sequential 34
Problem #13
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never beenseen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010…Z: 00010101000…
X: 11011010010…Z: 00000001000…
ELEC1041 – Tut Sequential 35
Problem #13 Solution (1/5)
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.
Moore State DiagramReset signal places FSM in S0
Outputs 1 Loops in State
S0 [0]
S1 [0]
S2 [0]
S3 [1]
S4 [0]
S5 [0]
S6 [0]
Reset
0 1
1
0
0
00,1
ELEC1041 – Tut Sequential 36
Problem #13 Solution (2/5)
Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2)
S0 [0]
S1 [0]
S2 [0]
S3 [1]
S4 [0]
S5 [0]
S6 [0]
Reset
0 1
1
0
0
00,1
10
ELEC1041 – Tut Sequential 37
Problem #13 Solution (3/5)
Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1
S0 [0]
S1 [0]
S2 [0]
S3 [1]
S4 [0]
S5 [0]
S6 [0]
Reset
0 1
1
0
0
00,1
1
01
0
ELEC1041 – Tut Sequential 38
Problem #13 Solution (4/5)
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!
Final State Diagram
S0 [0]
S1 [0]
S2 [0]
S3 [1]
S4 [0]
S5 [0]
S6 [0]
Reset
0 1
1
0
0
00,1
1
01
1
1
0
ELEC1041 – Tut Sequential 39
Problem #13 Solution (5/5)
Finite String RecognizerReview of Process:
• Write down sample inputs and outputs to understand specification
• Write down sequences of states and transitions for the sequences to be recognized
• Add missing transitions; reuse states as much as possible
• Verify I/O behavior of your state diagram to insure it functions like the specification
ELEC1041 – Tut Sequential 40
Problem #14
Finite String Pattern RecognizerA finite string recognizer has one input (X) and two output (Z1 & Z2).The output Z1 is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never beenseen. The output Z2 is asserted whenever the input sequence …100…has been observedNote that once Z2 = 1 has occurred, Z1 = 1 can never occur, but never vice versa
Step 1. Understanding the problem statement Sample input/output behavior:
X : 0010101001000…Z1: 0001010100000…Z2: 0000000010010…
X : 110110100100…Z1: 000000010000…Z2: 000000001001…
ELEC1041 – Tut Sequential 41
Problem #14 Solution (1/8)
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.
Moore State DiagramReset signal places FSM in S0
Output Z1= 1
S0 [00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
Output Z2= 1
0 1
1
0
0
0
ELEC1041 – Tut Sequential 42
Problem #14 Solution (2/8)
Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2)
S0 [00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
0 1
1
0 1
0
0
0
ELEC1041 – Tut Sequential 43
Problem #14 Solution (3/8)
Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1
S0 [00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
0 1
1
0
0
0
1
01
0
ELEC1041 – Tut Sequential 44
Problem #14 Solution (4/8)
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!
S0 [00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
0 1
1
0
0
0
1
01
1
1
0
ELEC1041 – Tut Sequential 45
Problem #14 Solution (5/8)
S6 = …100; If next input is 1, then string could be prefix of (100)1(00) S4 handles just this case!
Final State Diagram
S0 [00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
BUT IS IT? Remember S3 should never be entered again, so S5 should be avoided
0 1
1
0
0
0
1
01
1
1
0
1
ELEC1041 – Tut Sequential 46
Problem #14 Solution (6/8)
S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. S0
[00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
S7 [00]
S8 [00]
0 1
1
0
0
0
1
01
1
1
0 1
0 0
ELEC1041 – Tut Sequential 47
Problem #14 Solution (7/8)
S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. S0
[00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
S7 [00]
S8 [00]
0 1
1
0
0
0
1
01
1
1
0 1
0 0
S9 [00]
0
ELEC1041 – Tut Sequential 48
Problem #14 Solution (8/8)
S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. S0
[00]
S1 [00]
S2 [00]
S3 [Z1=1]
S4 [00]
S5 [00]
S6 [Z2=1]
Reset
S7 [00]
S8 [00]
0 1
1
0
0
0
1
01
1
1
0 1
0 0
S9 [00]
0 1
1
1
0
ELEC1041 – Tut Sequential 49
Problem #15
N + 2 converter
A sequential network has one input X and two outputs S and V. X represent a four bit binary number N, which is input least significantbit first. S represents a four bit binary number equal to N + 2, which is output least significant bit first. At the time the fourth input is sampled,V = 1, in N + 2 is too large to be represented by four bits; otherwise V = 0.
Derive a Mealy state graph and table with a minimum number of states
ELEC1041 – Tut Sequential 50
Problem #15 Solution (1/3)
Example: N +2 Serial ConverterAssume numbers are +ve (0N15)
(N) (N +2)0 0000 0010 01 0001 0011 02 0010 0100 03 0011 0101 04 0100 0110 05 0101 0111 06 0110 1000 07 0111 1001 08 1000 1010 09 1001 1011 010 1010 1100 011 1011 1101 012 1100 1110 013 1101 1111 014 1110 0000 115 1111 0001 1
Conversion Process
Bits are presented in bit serial fashionstarting with the least significant bit
Single input X, Two output S, V
X S V
XS
VFSM
N3N2N1N0
ELEC1041 – Tut Sequential 51
Problem #15 Solution (ver 1) (2/3)
Present State S0 S1S2 S3 S4 S5
Next StateOutput
SVX=0 S1 S2 S4 S4 S0 S0
X=1 S1 S3 S4 S5 S0 S0
X=0 00 10 00 10 00 10
X=1 10 00
10 00 10 01
Reset
S0
0/00,1/10
S10/10 1/00
S2
0/00,1/10
S3
1/000/10
S40/00,1/10
S50/10,1/01
ELEC1041 – Tut Sequential 52
Problem #15 Solution (ver 1) (3/3)
ROM-based Implementation
Circuit Level Realization74175 = 4 x positive edge triggered D FFs
In ROM-based designs, no need to consider state assignment
QA QA
QB QB
QC QC
QD QD
CLK
CLR1
converter ROMX Q2 Q1 Q0
V D2 D1 D0
15 14
10 11
7 6
2 3
D CB A
CLK
13 12
10 \Reset
X 175Z
9
5 4
S
Truth Table/ROM I/Os
10
X 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Q2 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1
Q1 0 0 1 1 0 0 1
0 0 1 1 0 0 1 1
Q0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 1
ROM AddressD2 0 0 1 1 0 0 X
0 0 1 1 0 0 X
X
D1 0 1 0 0 0 0 X
0 1 0 0 0 0 X X
D0 1 0 0 0 0 0 X
1 10 1 0 0 XX
ROM OutputsS 0 1 0 1 0 1 X
1 0 0 1 0 1 X X
V 0 0 0 0 0 0 X
0 0 0 0 0 0 X X
0 1 1 1 X X X X X
ELEC1041 – Tut Sequential 53
Problem #15 Solution (ver 2) (1/2)
N3N2N1N0 + 0 0 1 0---------------- N0
0Co
Sc Sb
FSM
A B
1 bit adder
S
Sb
1
MUX
0
X
CoQ
Co M
UX
Sc
0Cin
D QCoQCoD
V
Reset S0[0,0]
S2[0,1]
S3[0,1]
S1[1,0]
S0
S1
S0S1
Data pathController
PS NS OutputsQ1Q0 Q1
+ Q0+ Sb Sc
0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1
Q1+
= Q1 XOR Q0
Q0+
= Q0
Sb = Q1 Q0
Sc = Q1
S = A XOR B XOR CinCo = AB + (A + B) Cin
ELEC1041 – Tut Sequential 54
Problem #15 Solution (ver 2) (2/2)
Q1+
= Q1 XOR Q0
Q0+
= Q0
Sb = Q1 Q0
Sc = Q1
A B
1 bit adder
S
Sb
1
MUX
0
X
CoQ
Co
MU
X
Sc
0Cin
D QCoQ
CoD
VS0
S1
S0S1
D Q D QQ0 Q1
CLK
Sc
Sb
ELEC1041 – Tut Sequential 55
Problem #16
N - 2 converter
A sequential network has one input X and two outputs S and V. X represent a four bit binary number N, which is input least significantbit first. S represents a four bit binary number equal to N - 2, which is output least significant bit first. At the time the fourth input is sampled,V = 1, in N - 2 is too small to be represented by four bits; otherwise V = 0.
Derive a Mealy state graph and table with a minimum number of states
ELEC1041 – Tut Sequential 56
Problem #16 Solution (1/3)
Example: N -2 Serial Converter
Conversion Process
Bits are presented in bit serial fashionstarting with the least significant bit
Single input X, Two output S, V
(N) (N - 2)0 0000 1110 11 0001 1111 12 0010 0000 03 0011 0001 04 0100 0010 05 0101 0011 06 0110 0100 07 0111 0101 08 1000 0110 09 1001 0111 010 1010 1000 011 1011 1001 012 1100 1010 013 1101 1011 014 1110 1100 015 1111 1101 0
X S V
XS
VFSM
N3N2N1N0
Assume numbers are +ve (0N15)
ELEC1041 – Tut Sequential 57
Problem #16 Solution (ver 1) (2/3)
Present State S0 S1 S2 S3 S4 S5
Next StateOutput
SVX=0 S1 S2 S4 S5 S0 S0
X=1 S1 S3 S5 S5 S0
S0
X=0 00 10 10 00 11 00
X=1 10 00
00 10 00 10
Reset
S0
0/00,1/10
S10/10 1/00
S2
0/10
S3
0/00,1/10
1/00
S40/11,1/00
S50/00,1/10
ELEC1041 – Tut Sequential 58
Problem #16 Solution (ver 1) (3/3)
ROM-based Implementation
Truth Table/ROM I/Os
Circuit Level Realization74175 = 4 x positive edge triggered D FFs
In ROM-based designs, no need to consider state assignment
QA QA
QB QB
QC QC
QD QD
CLK
CLR1
converter ROMX Q2 Q1 Q0
V D2 D1 D0
15 14
10 11
7 6
2 3
D CB A
CLK
13 12
10 \Reset
X10
1759
5 4
X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ROM AddressD2 0 0 1 1 0 0 X X 0 0 1 1 1 0 X
X
D1 0 1 0 0 0 0 X X 0 1 0 0 1 0 X X
D0 1 0 0 1 0 0 X X 1 1 1 10 0 X X
ROM OutputsS 0 1 1 0 1 0 X X 1 0 0 1 0 1 X X
V 0 0 0 0 1 0 X X 0 0 0 0 0 0 X X
S
ELEC1041 – Tut Sequential 59
Problem #16 Solution (ver 2) (1/2)
N3N2N1N0 - 0 0 1 0---------------- X0
0Bo
Sc Sb
FSM
A B
1 bit subtractor
S
Sb
1
MUX
0
X
BoQ
Bo M
UX
Sc
0Bin
D QBoQCoD
V
Reset S0[0,0]
S2[0,1]
S3[0,1]
S1[1,0]
S0
S1
S0S1
Data pathController
PS NS OutputsQ1Q0 Q1
+ Q0+ Sb Sc
0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1
Q1+
= Q1 XOR Q0
Q0+
= Q0
Sb = Q1 Q0
Sc = Q1
S = A XOR B XOR BinBo = A’B + (A’ + B) Bin
ELEC1041 – Tut Sequential 60
Problem #16 Solution (ver 2) (2/2)
Q1+
= Q1 XOR Q0
Q0+
= Q0 Sb = Q1 Q0
Sc = Q1
A B
1 bit subtractor
S
Sb
1
MUX
0
X
CoQ
Co
MU
X
Sc
0Cin
D QCoQ
CoD
VS0
S1
S0S1
D Q D QQ0 Q1
CLK
Sc
Sb
ELEC1041 – Tut Sequential 61
Problem #17
ELEC1041 – Tut Sequential 62
Problem #17 Solution version 1 (1/4)
ELEC1041 – Tut Sequential 63
Problem #17 Solution version 1 (2/4)
+
ELEC1041 – Tut Sequential 64
Problem #17 Solution version 1 (3/4)
+
+ + +
ELEC1041 – Tut Sequential 65
Problem #17 Solution version 1 (4/4)
1 0
1 1
0 0
0 0
q1
D0
0 0
1 1
0 0
1 0
q1
D1
0 x
1 1
0 x
1 x
q1
Z0 0
0 1
0 0
1 0
q1
D2
ELEC1041 – Tut Sequential 66
Problem #17 Solution version 2 (1/5)
ELEC1041 – Tut Sequential 67
Problem #17 Solution version 2 (2/5)
+
We relax the requirement for undefined states toGo to zero, however, we still require them to go to
a valid state
ELEC1041 – Tut Sequential 68
Problem #17 Solution version 2 (3/5)
+
+ + +
ELEC1041 – Tut Sequential 69
Problem #17 Solution version 2 (4/5)
1 1
0 0
x 0
x x
q1
D0
0 1
1 0
x 0
x x
q1
D1
0 0
0 1
x 0
x x
q1
D2
0 1
1 1
x 0
x x
q1
D1
ELEC1041 – Tut Sequential 70
Problem #17 Solution version 1 (5/5)
1 1
0 0
x 0
x x
q1
D0
0 1
1 0
x 0
x x
q1
D1
0 0
0 1
x 0
x x
q1
D2
0 1
1 1
x 0
x x
q1
D1
+ + +
101 010110 010111 100undefined states end uo in valid states
ELEC1041 – Tut Sequential 71
Problem #18
Consider the design of a sequence detector finite state machine that will assert a 1 when the current input equals the just previously seen input.
(a) Draw as simple state diagrams for a MEALY MACHINE and a MOORE MACHINE implementation as you can (minimization is not necessary). The MEALY MACHINE should have fewer states. Briefly explain why.
(b) If the Mealy Machine is implemented as a SYNCHRONOUS MEALY MACHINE, draw the timing diagram for the example input/output sequence described above.
(c) If the timing behaviors are different for the MOORE, MEALY, and SYNCHRONOUS MEALY machines, explain the reason why.
ELEC1041 – Tut Sequential 72
Problem #18 Solution(1/4)
Sample input/output sequence:
001110101100
010110000101
ELEC1041 – Tut Sequential 73
Problem #18 Solution(2/4)
(a) Draw as simple state diagrams for a MEALY MACHINE and a MOORE MACHINE implementation as you can (minimization is not necessary). The MEALY MACHINE should have fewer states. Briefly explain why.
Since the output of Mealy Machines depend on both the current state and the current input, they don’t need as many states to represent input/output combinations.
S0S1
S2
0/0
1/0
0/1
1/0
1/1
0/0
Mealy
0
Moor
S0[0]
0
1 11
0
S1[0]
S2[0] S4
[1]
0S4[1]
11 0
ELEC1041 – Tut Sequential 74
Problem #18 Solution(3/4)
(b) If the Mealy Machine is implemented as a SYNCHRONOUS MEALY MACHINE, draw the timing diagram for the example input/output sequence described above.
001110101100
010110000101
ELEC1041 – Tut Sequential 75
Problem #18 Solution(4/4)
(c) If the timing behaviors are different for the MOORE, MEALY, and SYNCHRONOUS MEALY machines, explain the reason why.
The timing behaviors of a Moore Machine and a Synchronous Mealy Machine are the same.
The Mealy Machine will behave differently because the output changes as soon as the input changes rather than at the next clock cycle.
S0S1
S2
0/0
1/0
0/1
1/0
1/1
0/0
S1S0 S1 S2 S2 S2 S1 S2 S1 S2 S2 S1
ELEC1041 – Tut Sequential 76
Problem #19
Consider a 3-bit counter that behaves as follows. The counter has a mode input M. When M is true, the counter counts in the sequence 0, 2, 4, 6, 1, 3, 5, 7, 0 and repeat. When M is false, the counter counts in the sequence 0, 1, 6, 7, 2, 3, 4, 5, 0 and repeat. The M input can change at anytime to cause the counter to change into either mode.
(a) Complete the Encoded STATE TRANSITION TABLE for this counter.
(b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions.
ELEC1041 – Tut Sequential 77
Problem #19 Solution (1/4)
(a) Complete the Encoded STATE TRANSITION TABLE for this counter.
M = 0: 0, 1, 6, 7, 2, 3, 4, 5, 0 and repeat
M = 1: 0, 2, 4, 6, 1, 3, 5, 7, 0 and repeat
ELEC1041 – Tut Sequential 78
Problem #19 Solution (2/4)
(b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions.
D2
M’ Q0’ Q2 + M Q1 Q2’ + M’ Q0 Q2’ + M Q1’ Q2
ELEC1041 – Tut Sequential 79
Problem #19 Solution (3/4)
(b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions.
M Q1’ + Q0 Q1’ Q2’ + M’ Q1 Q2 + M’ Q0’ Q1
D1
ELEC1041 – Tut Sequential 80
Problem #19 Solution (4/4)
(b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions.
D0
M’Q0’ + Q0’ Q1 Q2 + M Q0 Q2’ + M Q0 Q1’
ELEC1041 – Tut Sequential 81
Problem #20
QAQBQCQD
163RCO
PT
ABCD
LOAD
CLR
CLK
+
CLK
switch
+
Figure below illustrates the use a Single-Pole Single-Throw (SPST) switch to increment the count value in the counter.Every throw of the switch causes a low-to-high transition on the clock input (CLK) which in turn causes the counter to increment by 1.However, we have noticed that each throw of the switch causesmultiple increments in the count value. Furthermore multipleincrements are equal to each other and changes from one throw of the switch to the next.a) Explain Why? b) How to do rectify the problem
ELEC1041 – Tut Sequential 82
Problem #20 Solution (1/2)
Switch
+
clk
Switch
Clk
a) This problem is due to bouncing effect in in a mechanical switch. The switch does not make a clean contact at-once. It bounces several times from its final position before coming to rest. This causes several low-to-high transition at the clk signal causing multiple count increments.
ELEC1041 – Tut Sequential 83
+
+
switch
\switch
clk
Problem #20 Solution (2/2)
/switch
clk
switch
b) This problem can be overcome by using a debouncing circuitry shown below. Here we use a Single-Pole Double-Throw (SPDT) switch to increment the count value in the counter. In spite of mechanical switch making several contacts, since the switch after the throw to one position never bounces back all the way to the opposite position the S-R latch will either be in set or hold state and its clk output stays constant after the first transition.
/S
/R
Initial position
Initial position