Digital System Design II II Peng Liu ( ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University 2 Lecture 2 MIPS Instruction Set Architecture 3 MIPS ISA Textbook reading Look at how instructions are defined and represented What is an instruction set architecture (ISA)? Interplay of C and MIPS ISA Components of MIPS ISA Register operands Memory operands Arithmetic operations Control flow operations 4 5 Components of any Computer Processor Computer Control (brain) Datapath (brawn) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) 5 Computer (All Digital Systems) Are At Their Core Pretty Simple Computers only work with binary signals Signal on a wire is either 0, or 1 Usually called a bit More complex stuff (numbers, characters, strings, pictures) Must be built from multiple bits Built out of simple logic gates that perform boolean logic AND, OR, NOT, And memory cells that preserve bits over time Flip-flops, registers, SRAM cells, DRAM cells, To get hardware to do anything, need to break it down to bits Stings of bits that tell hardware what to do are called instructions A sequence of instructions called machine language program (machine code) 6 Hardware/Software Interface The Instruction Set Architecture (ISA) defines what instructions do MIPS, Intel IA32 (x86), Sun SPARC, PowerPC, IBM 390, Intel IA64 These are all ISAs Many different implementations can implement same ISA (family) 8086,386, 486, Pentium, Pentium II, Pentium 4 implement IA32 Of course they continue to extend it, while maintaining binary compatibility ISA last a long time X86 has been in use since the 70s IBM 390 started as IBM 360 in 60s 7 Running An Application 8 MIPS ISA MIPS semiconductor company that built one of the first commercial RISC architectures Founded by J.Hennessy We will study the MIPS architecture in some detail in this class Why MIPS instead of Intel 80x86? MIPS is simple, elegant and easy to understand X86 is ugly and complicated to explain X86 is dominant on desktop MIPS is prevalent in embedded applications as processor core of system on chip (SOC) 9 C vs MIPS Programmers Interface CMIPS I ISA Registers 32 32b integer, R0= b single FP 16 64b double FP PC and special registers Memory local variables global variables2 32 linear array of bytes Data types int, short, char, unsigned, float, double, aggregate data types, pointers word (32b), byte (8b), half-word (16b) single FP (32b), double FP (64b) Arithmetic operators +, -, *, %, ++, 10Shift right by constant shift right arithm.sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logicalsllv $1,$2,$3$1 = $2 > $3 Shift right by variable shift right arithm.srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable Q: Can some multiply by 2 i ? Divide by 2 i ? Invert? 65 M I P S Reference Data : CORE INSTRUCTION SET (1) NAMEMNE- MON-IC FOR- MAT OPERATION (in Verilog)OPCODE/FU NCT (hex) AddaddRR[rd] = R[rs] + R[rt] (1)0 / 20 hex Add ImmediateaddiIR[rt] = R[rs] + SignExtImm (1)(2) 8 hex Branch On Equal beqIif(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4 hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2b0} 66 MIPS Data Transfer Instructions InstructionComment sw 500($4), $3Store word sh 502($2), $3Store half sb 41($3), $2Store byte lw $1, 30($2)Load word lh $1, 40($3)Load halfword lhu $1, 40($3)Load halfword unsigned lb $1, 40($3)Load byte lbu $1, 40($3)Load byte unsigned lui $1, 40Load Upper Immediate (16 bits shifted left by 16) Q: Why need lui? 0000 0000 LUI R5 R5 67 Multiply / Divide Start multiply, divide MULT rs, rt MULTU rs, rt DIV rs, rt DIVU rs, rt Move result from multiply, divide MFHI rd MFLO rd Move to HI or LO MTHI rd MTLO rd Registers HILO 68 MIPS Arithmetic Instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands; exception possible subtractsub $1,$2,$3$1 = $2 $33 operands; exception possible add immediateaddi $1,$2,100$1 = $ constant; exception possible add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions subtract unsignedsubu $1,$2,$3$1 = $2 $33 operands; no exceptions add imm. unsign.addiu $1,$2,100$1 = $ constant; no exceptions multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 $3,Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 $3,Unsigned quotient & remainder Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo Q: Which add for address arithmetic? Which add for integers? 69 Green Card: ARITHMETIC CORE INSTRUCTION SET (2) NAMEMNE- MON-IC FOR- MAT OPERATION (in Verilog)OPCODE/FMT / FT/ FUNCT (hex) Branch On FP True bc1tFIif (FPcond) PC=PC BranchAddr (4) 11/8/1/-- Load FP Singlelwc1IF[rt] = M[R[rs] + SignExtImm] (2) 11/8/1/-- DividedivRLo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 31/--/--/-- 70 When does MIPS Sign Extend? When value is sign extended, copy upper bit to full value: Examples of sign extending 8 bits to 16 bits: When is an immediate operand sign extended? Arithmetic instructions (add, sub, etc.) always sign extend immediates even for the unsigned versions of the instructions! Logical instructions do not sign extend immediates (They are zero extended) Load/Store address computations always sign extend immediates Multiply/Divide have no immediate operands however: unsigned treat operands as unsigned The data loaded by the instructions lb and lh are extended as follows (unsigned dont extend ) : lbu, lhu are zero extended lb, lh are sign extended Q: Then what is does add unsigned (addu) mean since not immediate? 71 MIPS Compare and Branch Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch BNE rs, rt, offset Compare to zero and Branch BLEZ rs, offset if R[rs] BLT < BGEZ >= BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >=! Remaining set of compare and branch ops take two instructions Almost all comparisons are against zero! 72 MIPS jump, branch, compare Instructions InstructionExampleMeaning branch on equalbeq $1,$2,100if ($1 == $2) go to PC Equal test; PC relative branch branch on not eq.bne $1,$2,100if ($1!= $2) go to PC Not equal test; PC relative set on less thanslt $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; 2s comp. set less than imm.slti $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; 2s comp. set less than uns.sltu $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns.sltiu $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jumpj 10000go to Jump to target address jump registerjr $31go to $31 For switch, procedure return jump and linkjal 10000$31 = PC + 4; go to For procedure call 73 Signed vs. Unsigned Comparison $1= 0 $2= 0 $3= 1 After executing these instructions: slt $4,$2,$1 ; if ($2 < $1) $4=1; else $4=0 slt $5,$3,$1 ; if ($3 < $1) $5=1; else $5=0 sltu $6,$2,$1 ; if ($2 < $1) $6=1; else $6=0 sltu $7,$3,$1 ; if ($3 < $1) $7=1; else $7=0 What are values of registers $4 - $7? Why? $4 = ; $5 = ; $6 = ; $7 = ; 74 MIPS Assembler Register Convention caller saved callee saved On Green Card in Column #2 at bottom 75 What C code properly fills in the blank in loop on right? 1: A[i++] >= 10 2: A[i++] >= 10 | A[i] = 10 || A[i++] = 10 || A[i] = 10 && A[i++] < 0 6 None of the above Peer Instruction: $s3=i, $s4=j, do j = j + 1 while (______); Loop:addiu $s4,$s4,1# j = j + 1 sll $t1,$s3,2# $t1 = 4 * i addu $t1,$t1,$s5# $t1 A[i] lw $t0,0($t1)# $t0 = A[i] addiu $s3,$s3,1# i = i + 1 slti $t1,$t0,10 # $t1 = $t0 < 10 beq $t1,$0, Loop # goto Loop slti $t1,$t0, 0 # $t1 = $t0 < 0 bne $t1,$0, Loop # goto Loop 76 What C code properly fills in the blank in loop on right? 1: A[i++] >= 10 2: A[i++] >= 10 | A[i] = 10 || A[i++] = 10 || A[i] = 10 && A[i++] < 0 6: None of the above Peer Instruction: $s3=i, $s4=j, do j = j + 1 while (______); Loop:addiu $s4,$s4,1# j = j + 1 sll $t1,$s3,2# $t1 = 4 * i addu $t1,$t1,$s5# $t1 A[i] lw $t0,0($t1)# $t0 = A[i] addiu $s3,$s3,1# i = i + 1 slti $t1,$t0,10 # $t1 = $t0 = 10) slti $t1,$t0, 0 # $t1 = $t0 < 0 bne $t1,$0, Loop # goto Loop if $t1 != 0 ($t0 < 0) 77 Green Card: OPCODES, BASE CONVERSION, ASCII (3) MIPS opcode (31:26) (1) MIPS funct (5:0) (2) MIPS funct (5:0) BinaryDeci- mal Hexa- deci-mal ASCII (1)slladd.f NUL jsrlmul.f STX luisyncfloor.w.f fSI lbuandcvt.w.f $ (1) opcode(31:26) == 0 (2) opcode(31:26) == 17 ten (11 hex ); if fmt(25:21)==16 ten (10 hex ) f = s (single); if fmt(25:21)==17 ten (11 hex ) f = d (double) Note: 3-in-1 - Opcodes, base conversion, ASCII! 78 Green Card green card /n./ [after the "IBM System/360 Reference Data" card] A summary of an assembly language, even if the color is not green. For example, "I'll go get my green card so I can check the addressing mode for that instruction."Image from Dave's Green Card Collection: 79 Peer Instruction Which instruction has same representation as 35 ten ? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F. Trick question! Instructions are not numbers Registers numbers and names: 0: $0, 8: $t0, 9:$t1,..15: $t7, 16: $s0, 17: $s1,.. 23: $s7 Opcodes and function fields (if necessary) add : opcode = 0, funct = 32 subu : opcode = 0, funct = 35 addi : opcode = 8 lw : opcode = 35 opcodersrtoffset rdfunctshamt opcodersrt opcodersrtimmediate rdfunctshamt opcodersrt rdfunctshamt opcodersrt 80 Peer Instruction Which instruction bit pattern = number 35? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F. Trick question! Instructions != numbers Registers numbers and names: 0: $0, 8: $t0, 9:$t1, ,16: $s0, 17: $s1, , Opcodes and function fields add : opcode = 0, function field = 32 subu : opcode = 0, function field = 35 addi : opcode = 8 lw : opcode = 81 Branch & Pipelines execute Branch Delay Slot Branch Target By the end of Branch instruction, the CPU knows whether or not the branch will take place. However, it will have fetched the next instruction by then, regardless of whether or not a branch will be taken. Why not execute it? ifetchexecute ifetchexecute ifetchexecute LL:slt$1, $3, $5 li $3, #7 sub $4, $4, 1 bz$4, LL addi $5, $3, 1 Time ifetchexecute 82 Delayed Branches In the Raw MIPS, the instruction after the branch is executed even when the branch is taken This is hidden by the assembler for the MIPS virtual machine allows the compiler to better utilize the instruction pipeline (???) Jump and link (jal inst): Put the return addr. Into link register ($31): PC+4 (logical architecture) PC+8 physical (Raw) architecture delay slot executed Then jump to destination address li $3, #7 sub $4, $4, 1 bz$4, LL addi$5, $3, 1 subi$6, $6, 2 LL:slt$1, $3, $5 Delay Slot Instruction 83 Filling Delayed Branches Inst FetchDcd & Op Fetch Execute Branch: Inst Fetch Dcd & Op Fetch Inst Fetch Execute execute successor even if branch taken! Then branch target or continue Single delay slot impacts the critical path Compiler can fill a single delay slot with a useful instruction 50% of the time. try to move down from above jump move up from target, if safe add $3, $1, $2 sub $4, $4, 1 bz$4, LL NOP... LL: add rd,... Is this violating the ISA abstraction? 84 Summary: Salient Features of MIPS I 32-bit fixed format inst (3 formats) bit GPR (R0 contains zero) and 32 FP registers (and HI LO) partitioned by software convention 3-address, reg-reg arithmetic instr. Single address mode for load/store: base+displacement no indirection, scaled 16-bit immediate plus LUI Simple branch conditions compare against zero or two registers for =, no integer condition codes Delayed branch execute instruction after a branch (or jump) even if the branch is taken (Compiler can fill a delayed branch with useful work about 50% of the time) 85 And in conclusion... Continued rapid improvement in Computing 2X every 1.5 years in processor speed; every 2.0 years in memory size; every 1.0 year in disk capacity; Moores Law enables processor, memory (2X transistors/chip/ ~1.5 ro 2.0 yrs) 5 classic components of all computers Control Datapath Memory Input Output } Processor 86 MIPS Machine Instruction Review: Instruction Format Summary 87 Addressing Modes Summary Register addressing Operand is a register (e.g. ALU) Base/displacement addressing (ex. load/store) Operand is at the memory location that is the sum of a base register + a constant Immediate addressing (e.g. constants) Operand is a constant within the instruction itself PC-relative addressing (e.g. branch) Address is the sum of PC and constant in instruction (e.g. branch) Pseudo-direct addressing (e.g. jump) Target address is concatenation of field in instruction and the PC 88 Addressing Modes Summary 89 HomeWork Readings: Read Chapter , then Appendix C and D. 90 Acknowledgements These slides contain material from courses: UCB CS152. Stanford EE108B