Download - Digital Transceiver Implementation
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Digital Transceiver Implementation
Characterization Presentation
Barak Shaashua Barak StraussmanSupervisor: Idan Shmuel
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Project GoalsImplementation of transceiver with Labview
on FPGA.
Project parts: 16 QAM Tranceiver 8 PSK Tranceiver
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I
Q
Serial /
Parallel
Constellation Mapping
DAC
ISIFilte
r
LPF
Up Convert
er
Channel Coder
Source Coder
CombinerSin(wt)
+π/2
LPF
I
Q
Transmitter Block Diagram
DAC
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Symbol Decision
Constellation
Mapping
Channel Decoder
RF
Parallel /
Serial
Receiver Block-Diagram
ADCSin(wt)
+π/2I
Q
I
Q +(
Source)
Timing &
Carrier Recover
yLPF
LPF
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Project Environment SoftwareLabView 2010 v.10
(FPGA, RF toolbox)Tabor – ArbConnection
HardwareFPGA – Virtex5, NI FlexRio BoardNI 5761 DigitizerTabor – wx2182Scope, Spectrum Analyzer
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Hardware Connection
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RatesFPGA – 400Mb/sTabor – 2.1GS/s, 16MB waveform memoryDigitizer – 250MS/sGPIB – 1.5MB/sLAN – Fast Ethernet 100Mb/sCoaxial cable – BW 4.2Ghz
Our IF frequency: 100MhzTabor Symbol Rate possible: 100Khz – 500Mhz
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Time Table
1.2 – 28.2 8.1 – 31.1 25.12 – 7.1 4.12 – 24.12 27.11– 3.12 3.11 – 26.11
Studying project material & work environment
Transmitter Block Design
Receiver Block Design
FPGA Simulation & debugging
Tests
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Channel CoderBlock Code – as Hamming Code:
Implementation with vectors and matrices representation
Able to detect up to 2 errors and correct one
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ISISymbol interference results of dispersion in
transmission mediumISI filter decreases this interferenceFilter: Root Raised Cosine
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Constellation MappingImplementation
with Lock Up Table
Symbols - according to Gray Code
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Timing & Carrier RecoveryRecovers 3 elements:
Symbol Timing – Grander Algorithm
Carrier FrequencyCarrier Phase
Makes use of Digital PLL
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Symbol DecisionNoise Sources: Channel,
Quantization, Aliasing…
Assumptions:Noise is AWGN, orthogonal
& i.i.dUniform symbol probability
Symbols decision according to Euclidian distance only.