Research ArticleDRV Evaluation of 6T SRAM Cell Using EfficientOptimization Techniques
Vinod Kumar Joshi and Chetana Nayak
Department of Electronics and Communication Engineering Manipal Institute of Technology Manipal Academy of Higher EducationManipal 576104 India
Correspondence should be addressed to Vinod Kumar Joshi vinodkumarjoshimanipaledu
Received 31 May 2018 Revised 11 July 2018 Accepted 12 July 2018 Published 25 July 2018
Academic Editor Gerard Ghibaudo
Copyright copy 2018 Vinod Kumar Joshi and Chetana Nayak This is an open access article distributed under the Creative CommonsAttribution License which permits unrestricted use distribution and reproduction in any medium provided the original work isproperly cited
An optimization based method which uses bisection search algorithm has been proposed to evaluate the accurate value of DataRetention Voltage (DRV) of a 6T Static Random Access Memory (SRAM) cell using 45 nm technology in the presence of processparameter variations Further we incorporate an Artificial Neural Network (ANN) block in our proposedmethodology to optimizethe simulation run time The highest values obtained from these two methods are declared as the DRV We noted an increase inDRV with temperature (119879) and process variations (PVs) The main advantage of the proposed technique is to reduce the DRVevaluation time and for our case we observe improvement in evaluation time of DRV by asymp 46 asymp 27 and asymp 8 times at 25∘C for 3 1205904 120590 and 5 120590 variations respectively using ANN block to without using ANN block
1 Introduction
Memory structures are now present not just as stand-alonememory chips but also an integral part of complex VLSIsystems [1] SRAMplays a major role in random access mem-ory design but its leakage currents reduction has become amajor concern in past decade Various architectures of SRAMcell have been also proposed in this regard [2 3] The moststraightforward and easier approach for reducing the leakagepower is to reduce the supply voltage (119881119889119889) of the SRAMcell Moreover reducing it below a certain limit may resultin the detrition of the stored data due to T and PVs InSRAM cell the critical 119881119889119889 above which a data-bit is retainedreliably is called the DRV of the cell Figure 1 shows thereduction of leakage current with the 119881119889119889 Hence operatingthe SRAM cell with the voltage higher than its DRV helpsin reducing leakage current in standby mode [4] Howeversome of the circuit mismatches result in the variation of the119881119905 of transistors which causes shifts in theDRV value Henceaccurate estimation of DRV is amajor challenge in low powerSRAM design [5 6]
Qin et al developed an analytical model for DRV to get asubstantial reduction in leakage current by suppressing the
119881119889119889 to DRV [7] The most straightforward method beingused to obtain the DRV is by running Monte-Carlo (MC)simulations until a desired failure probability level is reached[8] However this method has many disadvantages
Since obtaining the failure point is a rare event whichmakes MC simulation time-consuming [9] Another issueis the time to find a large number of samples to get theaccurate value of the tail of the DRV distribution as shown inFigure 2(a) Importance sampling (mixture importance andsequential importance) methods are developed to improvethe speed of simulation These methods have been proved tobe more effective than MC samples in obtaining the failurepoint [10ndash12] Wang et al proposed two methods to evaluateDRV [13] In the firstmethod they propose a statisticalmodelforDRV evaluationwhich uses the relationship betweenDRVand SNM Mean and variance of the SNM distribution havebeen obtainedusingMCsimulations andDRV is evaluated asthe value of the119881119889119889 at which SNM reaches zero In the secondmethod a generic tail model from recursive statistical block-age has been proposed Postfabrication methods are alsodeveloped which uses canary replica cells [14 15] and built-in self-test [16 17] to obtain DRV However the optimizationbased method proposed by G Huang et al [18] has been
HindawiActive and Passive Electronic ComponentsVolume 2018 Article ID 3457284 12 pageshttpsdoiorg10115520183457284
2 Active and Passive Electronic ComponentsLe
akag
e Cur
rent
(A
)
0 02 04 06 08 1
MeasuredDRV range
60
50
40
30
20
10
0
Supply Voltage (Vdd)
Figure 1 Graph showing leakage current versus 119881119889119889 [1 4]
claimed to be the fastest evaluationmethod to obtainDRVHeformulated DRV as a time domain worst performance boundproblem and then multistart point (MSP) optimization strat-egy is developed to evaluate the failure bound
We use MATLAB tool (version 2015b) to evaluate DRVusing optimization based method A MATLAB code iswritten for the node voltage equations (Q QB) of MOSFEToperating in the subthreshold region [19 20] Further weuse bisection search algorithm [21] to search the optimum119881119889119889 and SNM is evaluated using rotation algorithm [22] PVsare incorporated by generating 5000 quasirandom samplesfor the Gaussian distribution of 119881119905 To reduce the timetaken for evaluation an ANN block is incorporated whichpredicts the value of SNM for a particular sample pointA set of DRV values are evaluated and the correspondinghistogram is plotted The highest value of DRV obtained orthe tail point of the histogram is considered as the DRVThe procedure used by us has not been claimed so far asper our knowledge A basic 6T SRAM cell consists of twocross-coupled inverters and two access transistors (M5 andM6) are shown in Figure 2(b) M1 and M3 PMOS transistorsare pull-up transistors while M2 and M4 NMOS transistorsare known as pull-down transistors During read or writeoperation word line (WL) is raised high (transistors M5 andM6 become on) while in hold mode (or retention mode) WLismade low (transistorsM5 andM6 turn off) and SRAMstorethe data present in Q and QB nodesThe ability of the SRAMcell to hold the data in retention mode is determined by theSNMof the SRAM cellThe value of SNM is determined fromthe butterfly curve of the cell in hold mode Butterfly curveis a plot of voltages (Q versus QB and QB versus Q) whereQ and QB are the node voltages of SRAM cell as shown inFigure 3(a) SNM is evaluated as the length of the diagonal ofthemaximum square that can be incorporated in the butterflycurve Figure 3(a) shows the butterfly curve plotted at 119881119889119889= 1V and Figure 3(b) shows the butterfly curve drawn byvarying 119881119889119889 It can be observed from Figure 3(b) that thebutterfly curve shrinks as the 119881119889119889 is reduced and the SNMof the cell reduces to zero at 119881119889119889 = 0048 V
2 Proposed Method
The block diagram used for DRV evaluation has been shownin Figure 4 with different colors The evaluation procedurehas four major blocks
(1) Bisection search algorithm is used for optimizing thevalue of 119881119889119889 (blue color in Figure 4)
(2) Quasi MC sample generation block is used to incor-porate process parameter variation or variation of thethreshold voltage (119881119905) (red color in Figure 4)
(3) Seevinckrsquos rotation algorithm is used for SNM evalu-ation (green color in Figure 4)
(4) ANN block is used to optimize simulation time(yellow color in Figure 4)
21 Bisection Search Algorithm [21] This algorithm helpsto evaluate the accurate value of the DRV by searching anoptimum solution of 119881119889119889 at which the SRAM cell fails Firstwe define a rough range of 119881119889119889 from 0 to 1 V based on theinitial guess of the DRV Suppose if the range is definedas 1198811198891198891 and 1198811198891198892 the average between these two points isevaluated as119881119889119889119898 and this value is used in the analysis phaseto evaluate the SNM of the SRAM cell If the SNM point isevaluated as zero under PVs it means that the failure hasoccurred which implies that the DRV is situated above119881119889119889119898and the point1198811198891198891 is replaced with119881119889119889119898 On the other handif the failure has not occurred theDRV is located below119881119889119889119898and 1198811198891198892 is replaced with 119881119889119889119898 The process is repeated asthe 1198811198891198891 and 1198811198891198892 values get updated It is continued untilthe difference Δ = 1198811198891198892 - 1198811198891198891 evaluates to be less than adefined tolerance (Tol = 0001) Once this condition ismet theprocess ends and the final value of 1198811198891198892 (or 1198811198891198891) is declaredas theDRV If theDRV is not locatedwithin the defined rangethe process repeats for a new range Table 1 represents theMOSFET constants assumed during the evaluation of SNMwhich is taken from the 45 nm Predictive Technology Model(PTM) [24]
22 Quasi MC Sample Generation The value of DRV largelydepends on 119881119905 of the transistors T and channel length (L)Variation of these parameters affects the value of SNM andhence the DRVWe do the DRV evaluation only by varying119881119905of transistors M1 M2 M3 and M4 as shown in Figure 2(b)These values are defined in a Gaussian range with particularmean and variance and their samples are combined with theQuasi MC samples to obtain the seed points We take 5000Quasi MC samples for evaluation to get the better accuracyThe SNM is evaluated for each of these seed points generatedby Sobol sequence and failure analysis is done accordinglyThe variance of the Gaussian distribution is calculated byPelgrom model [25 26]
120590 = 18mV lowast 120583mradic119882119871 (1)
where 119882 is the width of MOSFET and 119871 can be used fromTable 1 Since during hold mode only transistors M1 M2 M3and M4 are active we have employed the variation only forthese transistors which is calculated in Table 2
Active and Passive Electronic Components 3
Table 1 MOSFET parameters used in MATLAB tool for SNM evaluation
Parameter (unit) NMOS value PMOS value1205830 Mobility (A1198812) 1205830119899 = 004398 1205830119901 = 00044119905119900119909 Thickness of oxide (nm) 119905119900119909119899 = 175 119905119900119909119901 = 185120576119903 Relative permittivity 39 39119899 Subthreshold slope factor 119899119899 = 1042 119899119901 = 1042119882 Channel width (120583m) 119882119899 = 012 119882119901 = 014119871 Channel length (nm) 45 45Mean of 119881119905 variation (V) 119881119905119899 = 0466 119881119905119901 = -04118V
Occ
urre
nces
DRV (mV)
(a)
BL
WL
M5
Q
M2
M1
Vdd
M3
M4
QBM6
WL
BLB
(b)
Figure 2 (a) DRV distribution obtained by statistical methods using 90 nm technology node for 10K-b SRAM [13] (b) Schematic ofconventional 6T SRAM cell [4]
Table 2 The variance of Vt variation (120590) is calculated using (1)
Transistors Variance of 119881119905 variation (120590)NMOS 002449 VPMOS 00226 V
23 SNM Evaluation We use theoretical equations devel-oped for node voltages (Q QB) to calculate the SNMusing butterfly curve These equations have been derivedby Calhoun et al which evaluate the node voltages byconsidering the characteristics of MOSFETS operating in thesubthreshold region The equation for QB is given by [19]
119876119861 = 119881119905ℎ 119899119899119899119901119899119899 + 119899119901 (ln(119868119904119901119868119904119899)
+ ln(1 minus exp ((minus119881119889119889 + 119876) 119881119905ℎ)1 minus exp (minus119876119881119905ℎ) )) + 119899119899119881119889119889119899119899 + 119899119901+ 119899119899119899119901119899119899 + 119899119901 (
119881119905119899119899119899 minus119881119905119901119899119901 )
(2)
where 119868119904119899and 119868119904119901 are given by [27]
119868119904119899 = 1205830119899119862119900119909119899119881119905ℎ2 (119882119899119871 ) (119899119899 minus 1) (3)
119868119904119901 = 1205830119901119862119900119909119901119881119905ℎ2 (119882119901119871 ) (119899119901 minus 1) (4)
where 119881119905ℎ = kTq thermal voltage 119899119899 119899119901 are subthresholdslope factor for NMOS and PMOS transistors respectively119868119904119899 119868119904119901are drain current (when VGS = Vt) for NMOS andPMOS transistors respectively 119881119889119889 is supply voltage 119881119905119899119881119905119901 are threshold voltage of NMOS and PMOS transistorsrespectively 1205830119899 1205830119901 are mobility of NMOS and PMOStransistors respectively 119862119900119909119899 119862119900119909119901are oxide capacitance ofNMOS and PMOS transistors respectively119882119899119882119901 are widthof polysilicon for NMOS and PMOS transistors respectivelyand L is length of polysilicon
The subthreshold slope factor n is evaluated using (5) byevaluating subthreshold slope (S) [27]
119878 = 119899119881119905ℎ ln (10) (5)
The value of S is found to be 60mVdecade at room T =25∘C Its value for typical bulk CMOS can range from 70 to120mVdecade [28]The value of n is evaluated as 1042 using(5) at room T The voltage at which node value Q equalsQB is known as tripping voltage (119881119898) It is the point wherecurves (Q versus QB and QB versus Q) intersect as shownin Figure 3(a) Here we assume the identical cross-coupledinverters to evaluate 119881119898 The relation of 119881119898 for an inverter isgiven by (6) (by ignoring theDrain Induced Barrier Lowering(DIBL) effects) as follows [29]
4 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QBQB vs Q
Vm
(a)
QB (V)
Q (V
)
minusminus
Vdd = 1V
Vdd = V
Vdd = VVdd = V
(b)
Figure 3 Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at 119881119889119889 = 1V (b) by varying 119881119889119889
119881119898 = 119881119889119889119899119899(119899119899 + 119899119901) +119899119901119881119905119899 minus 119899119899119881119905119901(119899119899 + 119899119901) + 119899119899119899119901119881119905ℎ ln (((119882119901119871) 119868119904119901) ((119882119899119871) 119868119904119899))(119899119899 + 119899119901)
+ 119899119899119899119901119881119905ℎ ln ((1 minus exp ((minus119881119889119889 + 119881119898) 119881119905ℎ)) (1 minus exp (minus119881119898119881119905ℎ)))(119899119899 + 119899119901)
(6)
All the notations used for (6) are same as mentioned for (2)(3) (4) and (5)
We use the graphical technique proposed by Seevinck[22] to calculate the SNM value as shown in Figure 5 Thesteps involved in this techniques are as follows
(1) Obtain Q and QB samples using (2) Figure 6 showsthe butterfly curve which is plotted using Q and QBsamples for 119881119889119889 = 05V
(2) Combine Q and QB set into a matrix X(3) Multiply Xwith rotationmatrix ie [U V1015840] = Rotlowast[Q
QB] where lowast indicates matrix multiplication and Rotis the rotational matrix
Rot = [[[cos(1205874 ) minus sin(1205874 )sin(1205874 ) cos(1205874 )
]]]
(7)
New axis for the rotated curve is (U V1015840) V1 is thematrix corresponding to V1015840
(4) Evaluate V2 as V2 = -V1 + (2radic2119881119898) where 119881119898 isobtained using (6) (U V1) is the rotated version of(Q QB) and (U V2) is the rotated version of (QB Q)Figure 7(a) shows the rotated version of Figure 6
(5) Take the difference between V2 and V1 samples ieZ = V2 - V1
(6) Plot (U Z) as shown in Figure 7(b) and obtain S1 =-min (Z) S2 = max (Z) and S3 = min (S1 S2)
(7) Finally SNM is evaluated as SNM = S3radic2For a particular value of 119881119889119889 and each and every sample ofQuasi MC seed the SNM is evaluated
24 ANN Block Artificial neural networks (ANNs) are afamily of learning models that are used to estimate func-tions that depend on a large number of inputs ANN isgenerally presented as system of interconnected ldquoneuronsrdquowhich exchange messages between each otherThis functionsapproximately as a brain It consists of three layers inputvariables hidden nodes and outputs Inputs can be of anynumber and are provided in the initial learning phaseOutputs are the ones which are obtained after the analysisDuring the process many intermediate hidden nodes arecreated that are essential for optimizing However the userdoes not have any control over them The optimizationprocess includes two important stages [23]
(i) Training or learning phase This phase uses all thedifferent input signals to predict the possible out-comes of outputs using cautious learning of previousexperiments These can be accomplished either byconducting a large number of experiments or by
Active and Passive Electronic Components 5
DEFINE SUPPLY RANGE
Generate Quasi MC samples inparameter space
ANN BLOCKPredict SNM for each m samples
SNM gt 002 Evaluate Accurate
SNM
SNMgt0V FAILURE=1
FAILURE=0lsquoBreakrsquo
FAILUREPOINT
OBTAINED
NO
YESDRV islocated
DRV is not located inthe range
YES
NO
YES
NO
USINGANN
WITHOUTUSINGANN
NOYES
All searches done
lsquoBreakrsquo
YES
NO
6>>1 and 6>>2 as (01V)Tol = 0001
6>>m = (6>>1 + 6>>2)2
DRV = 6>>2
(6>>1)
Δ= 6>>2 - 6>>1
Δlt Tol
Vdd1= Vddm Vdd2= Vddm
Figure 4 General block diagram for DRV evaluation using optimization based method
Obtain node voltageusing eq 2 Plot butterfly curve Rotate butterfly
curve using rotationmatrix
Get extreme pointsof plot
SNM = (Minimum of thetwo extreme points)2
Figure 5 General block diagram to evaluate the SNM using optimization method
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
2 Active and Passive Electronic ComponentsLe
akag
e Cur
rent
(A
)
0 02 04 06 08 1
MeasuredDRV range
60
50
40
30
20
10
0
Supply Voltage (Vdd)
Figure 1 Graph showing leakage current versus 119881119889119889 [1 4]
claimed to be the fastest evaluationmethod to obtainDRVHeformulated DRV as a time domain worst performance boundproblem and then multistart point (MSP) optimization strat-egy is developed to evaluate the failure bound
We use MATLAB tool (version 2015b) to evaluate DRVusing optimization based method A MATLAB code iswritten for the node voltage equations (Q QB) of MOSFEToperating in the subthreshold region [19 20] Further weuse bisection search algorithm [21] to search the optimum119881119889119889 and SNM is evaluated using rotation algorithm [22] PVsare incorporated by generating 5000 quasirandom samplesfor the Gaussian distribution of 119881119905 To reduce the timetaken for evaluation an ANN block is incorporated whichpredicts the value of SNM for a particular sample pointA set of DRV values are evaluated and the correspondinghistogram is plotted The highest value of DRV obtained orthe tail point of the histogram is considered as the DRVThe procedure used by us has not been claimed so far asper our knowledge A basic 6T SRAM cell consists of twocross-coupled inverters and two access transistors (M5 andM6) are shown in Figure 2(b) M1 and M3 PMOS transistorsare pull-up transistors while M2 and M4 NMOS transistorsare known as pull-down transistors During read or writeoperation word line (WL) is raised high (transistors M5 andM6 become on) while in hold mode (or retention mode) WLismade low (transistorsM5 andM6 turn off) and SRAMstorethe data present in Q and QB nodesThe ability of the SRAMcell to hold the data in retention mode is determined by theSNMof the SRAM cellThe value of SNM is determined fromthe butterfly curve of the cell in hold mode Butterfly curveis a plot of voltages (Q versus QB and QB versus Q) whereQ and QB are the node voltages of SRAM cell as shown inFigure 3(a) SNM is evaluated as the length of the diagonal ofthemaximum square that can be incorporated in the butterflycurve Figure 3(a) shows the butterfly curve plotted at 119881119889119889= 1V and Figure 3(b) shows the butterfly curve drawn byvarying 119881119889119889 It can be observed from Figure 3(b) that thebutterfly curve shrinks as the 119881119889119889 is reduced and the SNMof the cell reduces to zero at 119881119889119889 = 0048 V
2 Proposed Method
The block diagram used for DRV evaluation has been shownin Figure 4 with different colors The evaluation procedurehas four major blocks
(1) Bisection search algorithm is used for optimizing thevalue of 119881119889119889 (blue color in Figure 4)
(2) Quasi MC sample generation block is used to incor-porate process parameter variation or variation of thethreshold voltage (119881119905) (red color in Figure 4)
(3) Seevinckrsquos rotation algorithm is used for SNM evalu-ation (green color in Figure 4)
(4) ANN block is used to optimize simulation time(yellow color in Figure 4)
21 Bisection Search Algorithm [21] This algorithm helpsto evaluate the accurate value of the DRV by searching anoptimum solution of 119881119889119889 at which the SRAM cell fails Firstwe define a rough range of 119881119889119889 from 0 to 1 V based on theinitial guess of the DRV Suppose if the range is definedas 1198811198891198891 and 1198811198891198892 the average between these two points isevaluated as119881119889119889119898 and this value is used in the analysis phaseto evaluate the SNM of the SRAM cell If the SNM point isevaluated as zero under PVs it means that the failure hasoccurred which implies that the DRV is situated above119881119889119889119898and the point1198811198891198891 is replaced with119881119889119889119898 On the other handif the failure has not occurred theDRV is located below119881119889119889119898and 1198811198891198892 is replaced with 119881119889119889119898 The process is repeated asthe 1198811198891198891 and 1198811198891198892 values get updated It is continued untilthe difference Δ = 1198811198891198892 - 1198811198891198891 evaluates to be less than adefined tolerance (Tol = 0001) Once this condition ismet theprocess ends and the final value of 1198811198891198892 (or 1198811198891198891) is declaredas theDRV If theDRV is not locatedwithin the defined rangethe process repeats for a new range Table 1 represents theMOSFET constants assumed during the evaluation of SNMwhich is taken from the 45 nm Predictive Technology Model(PTM) [24]
22 Quasi MC Sample Generation The value of DRV largelydepends on 119881119905 of the transistors T and channel length (L)Variation of these parameters affects the value of SNM andhence the DRVWe do the DRV evaluation only by varying119881119905of transistors M1 M2 M3 and M4 as shown in Figure 2(b)These values are defined in a Gaussian range with particularmean and variance and their samples are combined with theQuasi MC samples to obtain the seed points We take 5000Quasi MC samples for evaluation to get the better accuracyThe SNM is evaluated for each of these seed points generatedby Sobol sequence and failure analysis is done accordinglyThe variance of the Gaussian distribution is calculated byPelgrom model [25 26]
120590 = 18mV lowast 120583mradic119882119871 (1)
where 119882 is the width of MOSFET and 119871 can be used fromTable 1 Since during hold mode only transistors M1 M2 M3and M4 are active we have employed the variation only forthese transistors which is calculated in Table 2
Active and Passive Electronic Components 3
Table 1 MOSFET parameters used in MATLAB tool for SNM evaluation
Parameter (unit) NMOS value PMOS value1205830 Mobility (A1198812) 1205830119899 = 004398 1205830119901 = 00044119905119900119909 Thickness of oxide (nm) 119905119900119909119899 = 175 119905119900119909119901 = 185120576119903 Relative permittivity 39 39119899 Subthreshold slope factor 119899119899 = 1042 119899119901 = 1042119882 Channel width (120583m) 119882119899 = 012 119882119901 = 014119871 Channel length (nm) 45 45Mean of 119881119905 variation (V) 119881119905119899 = 0466 119881119905119901 = -04118V
Occ
urre
nces
DRV (mV)
(a)
BL
WL
M5
Q
M2
M1
Vdd
M3
M4
QBM6
WL
BLB
(b)
Figure 2 (a) DRV distribution obtained by statistical methods using 90 nm technology node for 10K-b SRAM [13] (b) Schematic ofconventional 6T SRAM cell [4]
Table 2 The variance of Vt variation (120590) is calculated using (1)
Transistors Variance of 119881119905 variation (120590)NMOS 002449 VPMOS 00226 V
23 SNM Evaluation We use theoretical equations devel-oped for node voltages (Q QB) to calculate the SNMusing butterfly curve These equations have been derivedby Calhoun et al which evaluate the node voltages byconsidering the characteristics of MOSFETS operating in thesubthreshold region The equation for QB is given by [19]
119876119861 = 119881119905ℎ 119899119899119899119901119899119899 + 119899119901 (ln(119868119904119901119868119904119899)
+ ln(1 minus exp ((minus119881119889119889 + 119876) 119881119905ℎ)1 minus exp (minus119876119881119905ℎ) )) + 119899119899119881119889119889119899119899 + 119899119901+ 119899119899119899119901119899119899 + 119899119901 (
119881119905119899119899119899 minus119881119905119901119899119901 )
(2)
where 119868119904119899and 119868119904119901 are given by [27]
119868119904119899 = 1205830119899119862119900119909119899119881119905ℎ2 (119882119899119871 ) (119899119899 minus 1) (3)
119868119904119901 = 1205830119901119862119900119909119901119881119905ℎ2 (119882119901119871 ) (119899119901 minus 1) (4)
where 119881119905ℎ = kTq thermal voltage 119899119899 119899119901 are subthresholdslope factor for NMOS and PMOS transistors respectively119868119904119899 119868119904119901are drain current (when VGS = Vt) for NMOS andPMOS transistors respectively 119881119889119889 is supply voltage 119881119905119899119881119905119901 are threshold voltage of NMOS and PMOS transistorsrespectively 1205830119899 1205830119901 are mobility of NMOS and PMOStransistors respectively 119862119900119909119899 119862119900119909119901are oxide capacitance ofNMOS and PMOS transistors respectively119882119899119882119901 are widthof polysilicon for NMOS and PMOS transistors respectivelyand L is length of polysilicon
The subthreshold slope factor n is evaluated using (5) byevaluating subthreshold slope (S) [27]
119878 = 119899119881119905ℎ ln (10) (5)
The value of S is found to be 60mVdecade at room T =25∘C Its value for typical bulk CMOS can range from 70 to120mVdecade [28]The value of n is evaluated as 1042 using(5) at room T The voltage at which node value Q equalsQB is known as tripping voltage (119881119898) It is the point wherecurves (Q versus QB and QB versus Q) intersect as shownin Figure 3(a) Here we assume the identical cross-coupledinverters to evaluate 119881119898 The relation of 119881119898 for an inverter isgiven by (6) (by ignoring theDrain Induced Barrier Lowering(DIBL) effects) as follows [29]
4 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QBQB vs Q
Vm
(a)
QB (V)
Q (V
)
minusminus
Vdd = 1V
Vdd = V
Vdd = VVdd = V
(b)
Figure 3 Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at 119881119889119889 = 1V (b) by varying 119881119889119889
119881119898 = 119881119889119889119899119899(119899119899 + 119899119901) +119899119901119881119905119899 minus 119899119899119881119905119901(119899119899 + 119899119901) + 119899119899119899119901119881119905ℎ ln (((119882119901119871) 119868119904119901) ((119882119899119871) 119868119904119899))(119899119899 + 119899119901)
+ 119899119899119899119901119881119905ℎ ln ((1 minus exp ((minus119881119889119889 + 119881119898) 119881119905ℎ)) (1 minus exp (minus119881119898119881119905ℎ)))(119899119899 + 119899119901)
(6)
All the notations used for (6) are same as mentioned for (2)(3) (4) and (5)
We use the graphical technique proposed by Seevinck[22] to calculate the SNM value as shown in Figure 5 Thesteps involved in this techniques are as follows
(1) Obtain Q and QB samples using (2) Figure 6 showsthe butterfly curve which is plotted using Q and QBsamples for 119881119889119889 = 05V
(2) Combine Q and QB set into a matrix X(3) Multiply Xwith rotationmatrix ie [U V1015840] = Rotlowast[Q
QB] where lowast indicates matrix multiplication and Rotis the rotational matrix
Rot = [[[cos(1205874 ) minus sin(1205874 )sin(1205874 ) cos(1205874 )
]]]
(7)
New axis for the rotated curve is (U V1015840) V1 is thematrix corresponding to V1015840
(4) Evaluate V2 as V2 = -V1 + (2radic2119881119898) where 119881119898 isobtained using (6) (U V1) is the rotated version of(Q QB) and (U V2) is the rotated version of (QB Q)Figure 7(a) shows the rotated version of Figure 6
(5) Take the difference between V2 and V1 samples ieZ = V2 - V1
(6) Plot (U Z) as shown in Figure 7(b) and obtain S1 =-min (Z) S2 = max (Z) and S3 = min (S1 S2)
(7) Finally SNM is evaluated as SNM = S3radic2For a particular value of 119881119889119889 and each and every sample ofQuasi MC seed the SNM is evaluated
24 ANN Block Artificial neural networks (ANNs) are afamily of learning models that are used to estimate func-tions that depend on a large number of inputs ANN isgenerally presented as system of interconnected ldquoneuronsrdquowhich exchange messages between each otherThis functionsapproximately as a brain It consists of three layers inputvariables hidden nodes and outputs Inputs can be of anynumber and are provided in the initial learning phaseOutputs are the ones which are obtained after the analysisDuring the process many intermediate hidden nodes arecreated that are essential for optimizing However the userdoes not have any control over them The optimizationprocess includes two important stages [23]
(i) Training or learning phase This phase uses all thedifferent input signals to predict the possible out-comes of outputs using cautious learning of previousexperiments These can be accomplished either byconducting a large number of experiments or by
Active and Passive Electronic Components 5
DEFINE SUPPLY RANGE
Generate Quasi MC samples inparameter space
ANN BLOCKPredict SNM for each m samples
SNM gt 002 Evaluate Accurate
SNM
SNMgt0V FAILURE=1
FAILURE=0lsquoBreakrsquo
FAILUREPOINT
OBTAINED
NO
YESDRV islocated
DRV is not located inthe range
YES
NO
YES
NO
USINGANN
WITHOUTUSINGANN
NOYES
All searches done
lsquoBreakrsquo
YES
NO
6>>1 and 6>>2 as (01V)Tol = 0001
6>>m = (6>>1 + 6>>2)2
DRV = 6>>2
(6>>1)
Δ= 6>>2 - 6>>1
Δlt Tol
Vdd1= Vddm Vdd2= Vddm
Figure 4 General block diagram for DRV evaluation using optimization based method
Obtain node voltageusing eq 2 Plot butterfly curve Rotate butterfly
curve using rotationmatrix
Get extreme pointsof plot
SNM = (Minimum of thetwo extreme points)2
Figure 5 General block diagram to evaluate the SNM using optimization method
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
Active and Passive Electronic Components 3
Table 1 MOSFET parameters used in MATLAB tool for SNM evaluation
Parameter (unit) NMOS value PMOS value1205830 Mobility (A1198812) 1205830119899 = 004398 1205830119901 = 00044119905119900119909 Thickness of oxide (nm) 119905119900119909119899 = 175 119905119900119909119901 = 185120576119903 Relative permittivity 39 39119899 Subthreshold slope factor 119899119899 = 1042 119899119901 = 1042119882 Channel width (120583m) 119882119899 = 012 119882119901 = 014119871 Channel length (nm) 45 45Mean of 119881119905 variation (V) 119881119905119899 = 0466 119881119905119901 = -04118V
Occ
urre
nces
DRV (mV)
(a)
BL
WL
M5
Q
M2
M1
Vdd
M3
M4
QBM6
WL
BLB
(b)
Figure 2 (a) DRV distribution obtained by statistical methods using 90 nm technology node for 10K-b SRAM [13] (b) Schematic ofconventional 6T SRAM cell [4]
Table 2 The variance of Vt variation (120590) is calculated using (1)
Transistors Variance of 119881119905 variation (120590)NMOS 002449 VPMOS 00226 V
23 SNM Evaluation We use theoretical equations devel-oped for node voltages (Q QB) to calculate the SNMusing butterfly curve These equations have been derivedby Calhoun et al which evaluate the node voltages byconsidering the characteristics of MOSFETS operating in thesubthreshold region The equation for QB is given by [19]
119876119861 = 119881119905ℎ 119899119899119899119901119899119899 + 119899119901 (ln(119868119904119901119868119904119899)
+ ln(1 minus exp ((minus119881119889119889 + 119876) 119881119905ℎ)1 minus exp (minus119876119881119905ℎ) )) + 119899119899119881119889119889119899119899 + 119899119901+ 119899119899119899119901119899119899 + 119899119901 (
119881119905119899119899119899 minus119881119905119901119899119901 )
(2)
where 119868119904119899and 119868119904119901 are given by [27]
119868119904119899 = 1205830119899119862119900119909119899119881119905ℎ2 (119882119899119871 ) (119899119899 minus 1) (3)
119868119904119901 = 1205830119901119862119900119909119901119881119905ℎ2 (119882119901119871 ) (119899119901 minus 1) (4)
where 119881119905ℎ = kTq thermal voltage 119899119899 119899119901 are subthresholdslope factor for NMOS and PMOS transistors respectively119868119904119899 119868119904119901are drain current (when VGS = Vt) for NMOS andPMOS transistors respectively 119881119889119889 is supply voltage 119881119905119899119881119905119901 are threshold voltage of NMOS and PMOS transistorsrespectively 1205830119899 1205830119901 are mobility of NMOS and PMOStransistors respectively 119862119900119909119899 119862119900119909119901are oxide capacitance ofNMOS and PMOS transistors respectively119882119899119882119901 are widthof polysilicon for NMOS and PMOS transistors respectivelyand L is length of polysilicon
The subthreshold slope factor n is evaluated using (5) byevaluating subthreshold slope (S) [27]
119878 = 119899119881119905ℎ ln (10) (5)
The value of S is found to be 60mVdecade at room T =25∘C Its value for typical bulk CMOS can range from 70 to120mVdecade [28]The value of n is evaluated as 1042 using(5) at room T The voltage at which node value Q equalsQB is known as tripping voltage (119881119898) It is the point wherecurves (Q versus QB and QB versus Q) intersect as shownin Figure 3(a) Here we assume the identical cross-coupledinverters to evaluate 119881119898 The relation of 119881119898 for an inverter isgiven by (6) (by ignoring theDrain Induced Barrier Lowering(DIBL) effects) as follows [29]
4 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QBQB vs Q
Vm
(a)
QB (V)
Q (V
)
minusminus
Vdd = 1V
Vdd = V
Vdd = VVdd = V
(b)
Figure 3 Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at 119881119889119889 = 1V (b) by varying 119881119889119889
119881119898 = 119881119889119889119899119899(119899119899 + 119899119901) +119899119901119881119905119899 minus 119899119899119881119905119901(119899119899 + 119899119901) + 119899119899119899119901119881119905ℎ ln (((119882119901119871) 119868119904119901) ((119882119899119871) 119868119904119899))(119899119899 + 119899119901)
+ 119899119899119899119901119881119905ℎ ln ((1 minus exp ((minus119881119889119889 + 119881119898) 119881119905ℎ)) (1 minus exp (minus119881119898119881119905ℎ)))(119899119899 + 119899119901)
(6)
All the notations used for (6) are same as mentioned for (2)(3) (4) and (5)
We use the graphical technique proposed by Seevinck[22] to calculate the SNM value as shown in Figure 5 Thesteps involved in this techniques are as follows
(1) Obtain Q and QB samples using (2) Figure 6 showsthe butterfly curve which is plotted using Q and QBsamples for 119881119889119889 = 05V
(2) Combine Q and QB set into a matrix X(3) Multiply Xwith rotationmatrix ie [U V1015840] = Rotlowast[Q
QB] where lowast indicates matrix multiplication and Rotis the rotational matrix
Rot = [[[cos(1205874 ) minus sin(1205874 )sin(1205874 ) cos(1205874 )
]]]
(7)
New axis for the rotated curve is (U V1015840) V1 is thematrix corresponding to V1015840
(4) Evaluate V2 as V2 = -V1 + (2radic2119881119898) where 119881119898 isobtained using (6) (U V1) is the rotated version of(Q QB) and (U V2) is the rotated version of (QB Q)Figure 7(a) shows the rotated version of Figure 6
(5) Take the difference between V2 and V1 samples ieZ = V2 - V1
(6) Plot (U Z) as shown in Figure 7(b) and obtain S1 =-min (Z) S2 = max (Z) and S3 = min (S1 S2)
(7) Finally SNM is evaluated as SNM = S3radic2For a particular value of 119881119889119889 and each and every sample ofQuasi MC seed the SNM is evaluated
24 ANN Block Artificial neural networks (ANNs) are afamily of learning models that are used to estimate func-tions that depend on a large number of inputs ANN isgenerally presented as system of interconnected ldquoneuronsrdquowhich exchange messages between each otherThis functionsapproximately as a brain It consists of three layers inputvariables hidden nodes and outputs Inputs can be of anynumber and are provided in the initial learning phaseOutputs are the ones which are obtained after the analysisDuring the process many intermediate hidden nodes arecreated that are essential for optimizing However the userdoes not have any control over them The optimizationprocess includes two important stages [23]
(i) Training or learning phase This phase uses all thedifferent input signals to predict the possible out-comes of outputs using cautious learning of previousexperiments These can be accomplished either byconducting a large number of experiments or by
Active and Passive Electronic Components 5
DEFINE SUPPLY RANGE
Generate Quasi MC samples inparameter space
ANN BLOCKPredict SNM for each m samples
SNM gt 002 Evaluate Accurate
SNM
SNMgt0V FAILURE=1
FAILURE=0lsquoBreakrsquo
FAILUREPOINT
OBTAINED
NO
YESDRV islocated
DRV is not located inthe range
YES
NO
YES
NO
USINGANN
WITHOUTUSINGANN
NOYES
All searches done
lsquoBreakrsquo
YES
NO
6>>1 and 6>>2 as (01V)Tol = 0001
6>>m = (6>>1 + 6>>2)2
DRV = 6>>2
(6>>1)
Δ= 6>>2 - 6>>1
Δlt Tol
Vdd1= Vddm Vdd2= Vddm
Figure 4 General block diagram for DRV evaluation using optimization based method
Obtain node voltageusing eq 2 Plot butterfly curve Rotate butterfly
curve using rotationmatrix
Get extreme pointsof plot
SNM = (Minimum of thetwo extreme points)2
Figure 5 General block diagram to evaluate the SNM using optimization method
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
4 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QBQB vs Q
Vm
(a)
QB (V)
Q (V
)
minusminus
Vdd = 1V
Vdd = V
Vdd = VVdd = V
(b)
Figure 3 Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at 119881119889119889 = 1V (b) by varying 119881119889119889
119881119898 = 119881119889119889119899119899(119899119899 + 119899119901) +119899119901119881119905119899 minus 119899119899119881119905119901(119899119899 + 119899119901) + 119899119899119899119901119881119905ℎ ln (((119882119901119871) 119868119904119901) ((119882119899119871) 119868119904119899))(119899119899 + 119899119901)
+ 119899119899119899119901119881119905ℎ ln ((1 minus exp ((minus119881119889119889 + 119881119898) 119881119905ℎ)) (1 minus exp (minus119881119898119881119905ℎ)))(119899119899 + 119899119901)
(6)
All the notations used for (6) are same as mentioned for (2)(3) (4) and (5)
We use the graphical technique proposed by Seevinck[22] to calculate the SNM value as shown in Figure 5 Thesteps involved in this techniques are as follows
(1) Obtain Q and QB samples using (2) Figure 6 showsthe butterfly curve which is plotted using Q and QBsamples for 119881119889119889 = 05V
(2) Combine Q and QB set into a matrix X(3) Multiply Xwith rotationmatrix ie [U V1015840] = Rotlowast[Q
QB] where lowast indicates matrix multiplication and Rotis the rotational matrix
Rot = [[[cos(1205874 ) minus sin(1205874 )sin(1205874 ) cos(1205874 )
]]]
(7)
New axis for the rotated curve is (U V1015840) V1 is thematrix corresponding to V1015840
(4) Evaluate V2 as V2 = -V1 + (2radic2119881119898) where 119881119898 isobtained using (6) (U V1) is the rotated version of(Q QB) and (U V2) is the rotated version of (QB Q)Figure 7(a) shows the rotated version of Figure 6
(5) Take the difference between V2 and V1 samples ieZ = V2 - V1
(6) Plot (U Z) as shown in Figure 7(b) and obtain S1 =-min (Z) S2 = max (Z) and S3 = min (S1 S2)
(7) Finally SNM is evaluated as SNM = S3radic2For a particular value of 119881119889119889 and each and every sample ofQuasi MC seed the SNM is evaluated
24 ANN Block Artificial neural networks (ANNs) are afamily of learning models that are used to estimate func-tions that depend on a large number of inputs ANN isgenerally presented as system of interconnected ldquoneuronsrdquowhich exchange messages between each otherThis functionsapproximately as a brain It consists of three layers inputvariables hidden nodes and outputs Inputs can be of anynumber and are provided in the initial learning phaseOutputs are the ones which are obtained after the analysisDuring the process many intermediate hidden nodes arecreated that are essential for optimizing However the userdoes not have any control over them The optimizationprocess includes two important stages [23]
(i) Training or learning phase This phase uses all thedifferent input signals to predict the possible out-comes of outputs using cautious learning of previousexperiments These can be accomplished either byconducting a large number of experiments or by
Active and Passive Electronic Components 5
DEFINE SUPPLY RANGE
Generate Quasi MC samples inparameter space
ANN BLOCKPredict SNM for each m samples
SNM gt 002 Evaluate Accurate
SNM
SNMgt0V FAILURE=1
FAILURE=0lsquoBreakrsquo
FAILUREPOINT
OBTAINED
NO
YESDRV islocated
DRV is not located inthe range
YES
NO
YES
NO
USINGANN
WITHOUTUSINGANN
NOYES
All searches done
lsquoBreakrsquo
YES
NO
6>>1 and 6>>2 as (01V)Tol = 0001
6>>m = (6>>1 + 6>>2)2
DRV = 6>>2
(6>>1)
Δ= 6>>2 - 6>>1
Δlt Tol
Vdd1= Vddm Vdd2= Vddm
Figure 4 General block diagram for DRV evaluation using optimization based method
Obtain node voltageusing eq 2 Plot butterfly curve Rotate butterfly
curve using rotationmatrix
Get extreme pointsof plot
SNM = (Minimum of thetwo extreme points)2
Figure 5 General block diagram to evaluate the SNM using optimization method
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
Active and Passive Electronic Components 5
DEFINE SUPPLY RANGE
Generate Quasi MC samples inparameter space
ANN BLOCKPredict SNM for each m samples
SNM gt 002 Evaluate Accurate
SNM
SNMgt0V FAILURE=1
FAILURE=0lsquoBreakrsquo
FAILUREPOINT
OBTAINED
NO
YESDRV islocated
DRV is not located inthe range
YES
NO
YES
NO
USINGANN
WITHOUTUSINGANN
NOYES
All searches done
lsquoBreakrsquo
YES
NO
6>>1 and 6>>2 as (01V)Tol = 0001
6>>m = (6>>1 + 6>>2)2
DRV = 6>>2
(6>>1)
Δ= 6>>2 - 6>>1
Δlt Tol
Vdd1= Vddm Vdd2= Vddm
Figure 4 General block diagram for DRV evaluation using optimization based method
Obtain node voltageusing eq 2 Plot butterfly curve Rotate butterfly
curve using rotationmatrix
Get extreme pointsof plot
SNM = (Minimum of thetwo extreme points)2
Figure 5 General block diagram to evaluate the SNM using optimization method
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
6 Active and Passive Electronic Components
Q (V
)
QB (V)
Q vs QB
QB vs Q
Figure 6 Butterfly curve for Vdd = 05V using optimization method
minus minus minus minus minus
U vs V2 U vs V1
U (V)
V
(V)
(a)
minus
minus
minus
minus
Z (V
)
S1U vs Z
S2
minus minus minus minus minus
U (V)
(b)
Figure 7 (a) Rotated butterfly curve at 119881119889119889 = 05V (b) Plot of Z = V2-V1 with respect to U
ANNBLOCK
SNM
6NJ1
6NJ2
6NJ3
6NJ4
6>>
Figure 8 General block diagram of ANN block
using values of the previously conducted experi-ments These values will be stored and is used for theupcoming analysis phase
(ii) Analysis phase After learning all the calculationprocedure from the previous phase the network is
now ready for successfully providing outputs for anyinputs provided
For a 5000-sample space as mentioned in Section 22 theprocess of SNM evaluation is time-consuming Hence anANN block which has been trained to evaluate the SNM isused This block evaluates the SNM for all the samples andthen separates the samples having low SNM (SNM lt 002V)Only these samples are now sent to the actual analysis blockwhere the accurate value of SNM is evaluated using rotationalgorithm
If the SNM = 0 the sample is declared as the failuresample Input data set consists of119881119905 variations ofM1M2M3and M4 transistors and the 119881119889119889 SNM is the output vector asshown in Figure 8 Fifty data sets are generated using SNMevaluation algorithm and the network is trained using RadialBasis Function (RBF) network which is explained in nextsubsection
241 RBF Network [23] An RBF network uses nonlinearfunctions to map inputs to the outputs into a high dimen-sional feature space A general RBF network consists of three
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
Active and Passive Electronic Components 7
x1
x2
xm-1
xmK
K
K
w1
w2
wN
Input layer Hidden layer Output layer
y =
N
sumi=1
wiK(x xi)
Figure 9 Schematic of RBF [23]
layers as shown in Figure 9 The input layer with inputs x119894(119894 = 1 2 m) where 119898 is a number of input parametersThe hidden layer is generated by one-to-one correspondencebetween the training input data 119909119894 and the kernel functionK(x 119909119894) for 119894 = 1 2 N where 119873 is the number of trainingsamples [23] In the third layer the output is evaluated asthe linear weighted sum of the kernel functions generatedin the hidden layer The following equations are used by thenetwork
(i) To evaluate kernel function119870 (119909119894 119909119895)119870(119909119894 119909119895) = 119890|119909119894minus119909119895|212059010158402 (8)
where 119909119894 119909119895 represent input vectors with 119894 j = 1 2 m Here1205901015840denotes the Gaussian bandwidth
(i) Weight vector 119908 is calculated by
(119870 + 120582119868)119908 = 119910119889
(9)
Here 119870 is the kernel matrix 119868 is the identity matrix of order119873 120582 is called the regularization parameter and 119910119889is the
desired response vector(ii) To evaluate output of the network 119910
119910 = 119873sum119894=1
119908119894119870(119909 119909119894) (10)
119908119894 is the 119894th (119894 = 1 2 N) element of the weight vector119908 and119870(119909 119909119894) is the kernel functionKernel used for the control technique is an Exponential
Radial Basis Function (ERBF) By considering this ANNblock a considerable reduction in the evaluation time isobserved Four different ANN blocks are generated to evalu-ate the DRV for 119879 = 15∘C 25∘C 50∘C and 100∘C respectively
3 Result and Future Work
In this section we present the results of an optimizationbased method which evaluates the DRV of a 6T SRAM cellincorporating the process parameter variation by consideringthe variation of 119881119905 of four transistors
DRV varies within a range and changes with each runof the experiment It depends on the samples generated by
Quasi MC simulation To obtain the actual DRV we conductthe experiment for 25 runs and the highest value obtained isconsidered as the DRV After getting the DRV value from 25experiments the corresponding histogram is plotted for twocases (i) by considering the ANN block and (ii) by ignoringthe ANN block Table 3 indicates the 119881119905 variation range forPMOS and NMOS transistors for 3120590 4120590 and 5120590 variation
Table 4 represents the DRV obtained at 3120590 4120590 and 5120590variation for T = 15∘C 25∘C 50∘C and 100∘C respectivelyusing the parameter specifications shown in Table 1 andthe methodology followed in Section 2 From Table 4 wecan observe that DRV increases with T slightly while itincreases significantly with the variation of 119881119905 To comparethe time taken for DRV evaluation using with and withoutANN block we run the MATLAB code at 25∘C for 3 1205904 120590 and 5 120590 variations and note the corresponding timetaken for the highest value of DRV for 25 runs as shown inTable 5 Figure 10 represents the corresponding bar chartThehistogram to obtain the DRV at T = 15∘C 25∘C 50∘C and100∘C for 3 120590 4 120590 and 5 120590 variation follows the distributionshown in Figure 2(a) and has been presented in Appendix
However the time taken for evaluation depends on theversion ofMATLAB tool the machine on which the programis executing and how fast the failure sample is obtained out ofthe 5000 Quasi MC samples generated From Table 5 we canobserve that ANN block helps in reducing the time taken forDRV evaluation Since the evaluation time varies randomlyfor each run so the comparison of evaluation time cannot begeneralized The method can be extended to evaluate DRVfor a memory chip with complex circuit structure The mod-ification can be made in the algorithm to obtain the moreaccurate DRV results with better simulation time Instead ofobtaining the node voltage values using theoretical equationspractical SPICE-level simulation can be used to evaluate theSNM for a given 119881119889119889 and 119881119905 Optimization algorithms can beimplemented for the node voltages generated by the circuitThe procedure can be extended for other technology nodesby considering other process parameter variations like 119879 andgeometry variations in119882 and 119871 for other cell topologiesAppendix
See Figure 11
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
8 Active and Passive Electronic Components
Table 3 Vt variation range used for PMOS and NMOS
Variation Range for PMOS Range for NMOS3 120590 -04796V to -0344V 039253V to 053947V4 120590 -05022V to -03214V 036804V to 056396V5 120590 -05248V to -02988V 034355V to 058845V
Table 4 DRV values with 3 120590 4 120590 and 5 120590 variation of Vt for T = 15∘C 25∘C 50∘C and 100∘C
Temperature (∘C) DRVWithout ANN (V) DRVWith ANN (V)3 120590 4 120590 5 120590 3 120590 4 120590 5 120590
15 0325 0416 04951 0325 04141 0496125 0331 04189 05 0333 04189 0550 0352 04229 05069 0352 04229 05078100 036 04443 05146 036 04443 05107
Table 5 Time elapsed for DRV evaluation at 25∘C for 3 120590 4 120590 and 5 120590 variationsTemperature (25∘C) DRVWithout ANN (V) DRVWith ANN (V)
3 120590 4 120590 5 120590 3 120590 4 120590 5 120590DRV 0331 04189 05 0333 04189 05Time (s) 459 649 783 10 24 103
032
5
033
1
035
2
036
032
5
033
3
035
2
036
041
6
041
89
042
29
044
43
041
41
041
89
042
29
044
43049
51
05 050
69
051
46
049
61
05 050
78
051
07
15 25 50 100
DRV (V) at 3 Without ANN DRV (V) at 3 With ANNDRV (V) at 4 Without ANN DRV (V) at 4 With ANNDRV (V) at 5 Without ANN DRV (V) at 5 With ANN
DRV
(V)
Temperature (∘C)
Figure 10 Plot of DRV for 3120590 4120590 and 5120590 variation at T = 15∘C 25∘C 50∘C and 100∘C
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
Active and Passive Electronic Components 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Freq
uenc
y
Freq
uenc
yFr
eque
ncy
Freq
uenc
yFr
eque
ncy
Freq
uenc
y
027 028 029 03 031 032 033
027 028 029 03 031 032 033
027 028 029 03 031 032 033 034
DRV (V) DRV (V)
DRV (V)DRV (V)
DRV (V)DRV (V)
034 035 036 028 029 03 031 032 033 034 035 036
5
45
4
35
3
25
2
15
1
05
0
5
45
4
35
3
25
2
15
1
05
0037 0375 038 0385 039 0395 04 0405 041 0415 042 0375 038 0385 039 0395 04 0405 041 0415 042
Figure 11 Continued
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
10 Active and Passive Electronic Components
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Freq
uenc
y
Freq
uenc
y
DRV (V)DRV (V)
Without ANN
With ANN
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0037 038 039 04 041 042 043 039 04 044 045041 042 043
046 0465 047 0475 048 0485 049 0495 05046 0465 047 0475 048 0485 049 0495 05045 0455
045 046 046047 048 049 05 051 047 048 049 05 051 052
Figure 11 DRV for 3 120590 4 120590 and 5 120590 variations at T = 15∘C 25∘C 50∘C and 100∘C with and without ANN block
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
Active and Passive Electronic Components 11
Data Availability
The data used to support the findings of this study areincluded within the article
Conflicts of Interest
The authors declare that they have no conflicts of interest
Acknowledgments
The authors kindly acknowledge Department of E amp CManipal Institute of TechnologyManipal Academy ofHigherEducation Manipal to provide the MATLAB tool facilityfor simulation They also acknowledge the PTM website toprovide the PTMmodel file of 45 nm technology
References
[1] K Roy and S C Prasad Low-Power CMOSVLSI Circuit DesignWiley 2009
[2] D Nayak D P Acharya and KMahapatra ldquoA read disturbancefree differential read SRAM cell for low power and reliablecache in embedded processorrdquo AEU - International Journal ofElectronics and Communications vol 74 pp 192ndash197 2017
[3] S Ahmad N Alam and M Hasan ldquoPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power appli-cationsrdquoAEU - International Journal of Electronics and Commu-nications vol 83 pp 366ndash375 2018
[4] H E Weste Neil and D M Harris CMOS VLSI Design-A Cir-cuits and Systems Perspective Addison-Wesley 4th edition 2010
[5] Ruchi and S Dasgupta ldquoSensitivity analysis of DRV for variousconfigurations of SRAMrdquo in Proceedings of the 2015 19thInternational Symposium on VLSI Design and Test (VDAT) pp1ndash5 Ahmedabad India June 2015
[6] Ruchi and S Dasgupta ldquo6T SRAM cell analysis for DRV andread stabilityrdquo Journal of Semiconductors vol 38 no 2 pp 1ndash72017
[7] H Qin Y Cao D Markovic A Vladimirescu and J RabaeyldquoSRAM leakage suppression by minimizing standby supplyvoltagerdquo in Proceedings of the 5th International Symposium onQuality Electronic Design pp 55ndash60 San Jose Calif USA 2004
[8] N Edri S Fraiman A Teman and A Fish ldquoData retentionvoltage detection for minimizing the standby power of SRAMarraysrdquo in Proceedings of the 2012 IEEE 27th Convention ofElectrical and Electronics Engineers in Israel IEEEI rsquo12 pp 1ndash5Eilat Israel November 2012
[9] A Nourivand A J Al-Khalili and Y Savaria ldquoPostsilicon tun-ing of standby supply voltage in srams to reduce yield lossesdue to parametric data-retention failuresrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 20 no 1 pp29ndash41 2012
[10] L Dolecek M Qazi D Shah and A Chandrakasan ldquoBreakingthe simulation barrier SRAM evaluation through norm mini-mizationrdquo in Proceedings of the 2008 International Conferenceon Computer-Aided Design ICCAD rsquo08 pp 322ndash329 USANovember 2008
[11] R Kanj R Joshi and S Nassif ldquoMixture Importance Samplingand its Application to the Analysis of SRAM Designs in thePresence of Rare Failure Eventsrdquo in Proceedings of the DesignAutomation Conference pp 69ndash72 San Francisco Calif USAJuly 2006
[12] K Katayama S Hagiwara H Tsutsui H Ochi and T SatoldquoSequential importance sampling for low-probability and high-dimensional SRAM yield analysisrdquo in Proceedings of the 2010IEEEACM International Conference on Computer-Aided Design(ICCAD) pp 703ndash708 San Jose Calif USA November 2010
[13] J Wang A Singhee R A Rutenbar and B H Calhoun ldquoTwofast methods for estimating the minimum standby supply volt-age for large SRAMsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 29 no 12 pp1908ndash1920 2010
[14] J Wang and B H Calhoun ldquoCanary replica feedback for near-DRV standby VDD scaling in a 90nm SRAMrdquo in Proceedings ofthe 2007 IEEE Custom Integrated Circuits Conference CICC pp29ndash32 San Jose Calif USA September 2007
[15] JWang andBHCalhoun ldquoTechniques to extend canary-basedstandby VDD scaling for SRAMs to 45 nm and beyondrdquo IEEEJournal of Solid-State Circuits vol 43 no 11 pp 2514ndash25232008
[16] F B Yahya M Mansour A Kayssi and H Hajj ldquoUsing BISTcircuitry to measure DRV of large SRAM arraysrdquo in Proceedingsof the 2010 International Conference on EnergyAware Computing(ICEAC) pp 1ndash4 Cairo Egypt December 2010
[17] J Wang A Hoefler and B H Calhoun ldquoAn enhanced canary-based system with BIST for SRAM standby power reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 19 no 5 pp 909ndash914 2011
[18] GHuang LQian S SaibuaD Zhou andX Zeng ldquoAn efficientoptimization basedmethod to evaluate theDRVof SRAMcellsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol60 no 6 pp 1511ndash1520 2013
[19] B H Calhoun and A Chandrakasan ldquoAnalyzing static noisemargin for sub-threshold SRAM in 65 nm CMOSrdquo in Pro-ceedings of the 31st European Solid-State Circuits Conference(ESSCIRC rsquo05) pp 363ndash366 September 2005
[20] A Makosiej O Thomas A Vladimirescu et al ldquoStability andYield-Oriented Ultra-Low-Power Embedded 6T SRAM CellDesign Optimizationrdquo in Proceedings of the Design AutomationTest in Europe Conference amp Exhibition pp 93ndash98 DresdenGermany March 2012
[21] M Bartholomew-Biggs Nonlinear Optimization with Engineer-ing Applications Springer 2008
[22] E Seevinck F J List and J Lohstroh ldquoStatic-noise marginanalysis of MOS SRAM cellsrdquo IEEE Journal of Solid-StateCircuits vol 22 no 5 pp 748ndash754 1987
[23] S Haykin Neural Networks A Comprehensive FoundationPrentice hall 2nd edition 2004
[24] ldquoPTMmodel for 45nm technologyrdquo httpptmasuedumodel-card200645nm bulkpm assessed February 2016
[25] MQaziM Tikekar and LDolecek ldquoLoop Flattening SphericalSampling Highly efficient model reduction techniques forSRAM yield Analysisrdquo in Proceedings of the Automation ampTest in Europe Conference amp Exhibition pp 801ndash806 DresdenGermany March 2010
[26] K J Kuhn ldquoReducing variation in advanced logic technologiesapproaches to process and design for manufacturability ofnanoscale CMOSrdquo in Proceedings of the IEEE InternationalElectron Devices Meeting (IEDM rsquo07) pp 471ndash474 WashingtonDC USA December 2007
[27] A Wang B Calhon and A P Chandrashekharan Sub-Thre-shold Design for Ultra-low Power Systems Springer 2006
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
12 Active and Passive Electronic Components
[28] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003
[29] J F Ryan JWang and BH Calhoun ldquoAnalyzing andmodelingprocess balance for sub-threshold circuit designrdquo in Proceedingsof the 17th Great Lakes Symposium on VLSI GLSVLSIrsquo07 pp275ndash280 Italy March 2007
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom
International Journal of
AerospaceEngineeringHindawiwwwhindawicom Volume 2018
RoboticsJournal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Active and Passive Electronic Components
VLSI Design
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Shock and Vibration
Hindawiwwwhindawicom Volume 2018
Civil EngineeringAdvances in
Acoustics and VibrationAdvances in
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Electrical and Computer Engineering
Journal of
Advances inOptoElectronics
Hindawiwwwhindawicom
Volume 2018
Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom
The Scientific World Journal
Volume 2018
Control Scienceand Engineering
Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom
Journal ofEngineeringVolume 2018
SensorsJournal of
Hindawiwwwhindawicom Volume 2018
International Journal of
RotatingMachinery
Hindawiwwwhindawicom Volume 2018
Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Chemical EngineeringInternational Journal of Antennas and
Propagation
International Journal of
Hindawiwwwhindawicom Volume 2018
Hindawiwwwhindawicom Volume 2018
Navigation and Observation
International Journal of
Hindawi
wwwhindawicom Volume 2018
Advances in
Multimedia
Submit your manuscripts atwwwhindawicom