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Pirouz Bazargan Sabet December 2003
Effective Implementation of a 32-bit RISC Processor
Pirouz Bazargan Sabet
University of Paris 6 - LIP6 - ASIM
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Pirouz Bazargan Sabet December 2003
Outline
Architecture of a RISC Processor
Implementation
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Pirouz Bazargan Sabet December 2003
Introduction
Architecture ?
All aspects visible from the USER’s (programmer) point of view
External view
Specifications of the processor
What the processor is supposed to do
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Pirouz Bazargan Sabet December 2003
Introduction
Implementation ?
All aspects visible from the DESIGNER’s point of view
Internal view
How much time does it take to perform some operation ?
Which hardware may be used and how it should be organized to make
the specifications feasable
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Pirouz Bazargan Sabet December 2003
Software visible registers
The instruction set
Architecture
Memory Addressing
The exception / reset mechanism
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Pirouz Bazargan Sabet December 2003
Architecture
Architecture of the MIPS processor
Mips ?
A 32-bit processor
One of the two first RISC architectures
Defined in 1981 by the Architecture Research Group at the Stanford University (John Hennessy)
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Pirouz Bazargan Sabet December 2003
Architecture
Simplified Mips-R3000 architecture
No floating point operations
No virtual memory management
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Pirouz Bazargan Sabet December 2003
Software visible registers
The instruction set
Architecture
Memory Addressing
The exception / reset mechanism
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Pirouz Bazargan Sabet December 2003
Architecture
Software visible registers
Registers that can be manipulated (written and read) in the assembly language
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Pirouz Bazargan Sabet December 2003
Software Visible Registers
32 common 32-bit registers
Integer Registers
R0 …. R31
Addressed from their number
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Pirouz Bazargan Sabet December 2003
Software Visible Registers
R0 : The Trash Register
R0 contains always 0A value written into R0 is lost
R31 : The Link Register
When a subroutine is called, the return address is saved into R31
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Pirouz Bazargan Sabet December 2003
Software Visible Registers
Two 32-bit registers : HI and LO
Used by multiply and divide instructions
Multiply32 most significant bits
32 least significant bits
HI
LO
DivideResult
Remainder
HI
LO
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Pirouz Bazargan Sabet December 2003
Software Visible Registers
Four 32-bit special registers : Coprocessor Registers
Needed to implement an operating system
SR Status Register
CAUSE Cause Register (cause of exceptions)
EPC Exception Program Counter (return address in case of exception)
BAR Bad Address Register (illegal memory address)
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Pirouz Bazargan Sabet December 2003
Software visible registers
The instruction set
Architecture
Memory Addressing
The exception / reset mechanism
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Pirouz Bazargan Sabet December 2003
Memory Addressing
32-bit address 4 Gbytes of memory space
Read / Write operations
3 types of data :
Half-word (2 bytes)
Word (4 bytes)
Byte
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Pirouz Bazargan Sabet December 2003
Memory Addressing
The processor can operate under 2 modes
User / Kernel
1
1 : user0 : kernel
The current mode is defined by the Status Register
Status Register
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Pirouz Bazargan Sabet December 2003
Memory Addressing
The memory space is divided into 2 parts
In User mode the processor can only access the addresses ranged from 0000 0000 to 7FFF FFF
0000 0000
7FFF FFFF
8000 0000
FFFF FFFF
USER
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Pirouz Bazargan Sabet December 2003
Memory Addressing
0000 0000
7FFF FFFF
8000 0000
FFFF FFFF
The OS protects the hardware against an error in a User program
USER
O SThe frontier protects the OS
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Pirouz Bazargan Sabet December 2003
Memory Addressing
lsbMsb
memory
register
Data alignment rule
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Pirouz Bazargan Sabet December 2003
Memory Addressing
lsbMsb
memory
register
Bytes’ order : Little Endian0000 0000
FFFF FFFF
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Pirouz Bazargan Sabet December 2003
Memory Addressing
Address alignment rule
The address of an object of N bytes must be multiple of N
Address of a Word multiple of 4
Address of a Half-Word multiple of 2
Address of a Byte multiple of 1
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Pirouz Bazargan Sabet December 2003
Software visible registers
The instruction set
Architecture
Memory Addressing
The exception / reset mechanism
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Pirouz Bazargan Sabet December 2003
Instruction Set
RISC Architecture
Only simple instructions
All instructions have the same size (32 bits)
3-operand instructions (2 read, 1 write)
No operation involving operands in memory - Only load and store operations
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Pirouz Bazargan Sabet December 2003
Instruction Set
3 instruction formats
Register-register instructionsR
Immediate instructionsI
Jump instructionsJ
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Pirouz Bazargan Sabet December 2003
Instruction Set
R format
opcod Operation codefunc Function (opcod extension)rs # of source registerrt # of source registerrd # of destination registersham Shift amount (# of bit the opr. is shifted)
6opcod
5rs
5rt
5rd
5sham
6func
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Pirouz Bazargan Sabet December 2003
Instruction Set
I format
opcod Operation code
rs # of source register
rt / rd # of source or destination register
imd Immediate value
6opcod
5rs
5rt/rd
16imd
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Pirouz Bazargan Sabet December 2003
Instruction Set
J format
opcod Operation code
imd Immediate value
6opcod
26imd
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Pirouz Bazargan Sabet December 2003
Instruction Set
Arithmetic and logic instructions
Control instructions
Memory access instructions
System instructions
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
Add Rd, Rs, Rt Rs+Rt Rd
Overflow exc.addopcod rs rt rd func
R format
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rd imd
I format
Addi Rd, Rs, Imd Rs+Imd Rd
add immediate Overflow exc.Imd is sign extended
Rs
Rd
Imd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
Addu Rd, Rs, Rt Rs+Rt Rd
No overflowadd unsignedR format
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rd imd
I format
Addiu Rd, Rs, Imd Rs+Imd Rd
add immediate unsigned No overflow
Imd is sign extended
Rs
Rd
Imd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Sub Rd, Rs, Rt Rs–Rt Rd
Overflow exc.subtract
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Subu Rd, Rs, Rt Rs–Rt Rd
No overflowSubtract unsigned
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Or Rd, Rs, Rt Rs or Rt Rd
bitwise logic OR
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rd imd
I format
Ori Rd, Rs, Imd Rs or Imd Rd
bitwise logic OR immediate
Imd is zero extended
Rs
Rd
0 0 0 0 Imd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
And Rd, Rs, Rt Rs and Rt Rd
bitwise logic AND
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rd imd
I format
Andi Rd, Rs, Imd Rs and Imd Rd
bitwise logic AND
immediate
Imd is zero extended
Rs
Rd
Imd0 0 0 0
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Xor Rd, Rs, Rt Rs xor Rt Rd
bitwise logic XOR
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rd imd
I format
Xori Rd, Rs, Imd Rs xor Imd Rd
bitwise logic XOR
immediate
Imd is zero extended
Rs
Rd
Imd0 0 0 0
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Nor Rd, Rs, Rt Rs nor Rt Rd
bitwise logic NOR
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod shamrt rd func
R format
Sll Rd, Rt, Sham Rt << Sham Rd
Shift left logic
0
Sham
Rt
Rd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Sllv Rd, Rt, Rs Rt << Rs Rd
Shift left logic variable
0
Rt
Rd
RsOnly the 5 lsb of Rs are meaningful
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod shamrt rd func
R format
Srl Rd, Rt, Sham Rt >> Sham Rd
Shift right logic
0
Sham
Rt
Rd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Srlv Rd, Rt, Rs Rt >> Rs Rd
Shift right logic variable
RsOnly the 5 lsb of Rs are meaningful
0
Rt
Rd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod shamrt rd func
R format
Sra Rd, Rt, Sham Rt >> Sham Rd
Shift right arithmetic
Sham
Rt
Rd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Srav Rd, Rt, Rs Rt >> Rs Rd
Shift right arithmetic variable
RsOnly the 5 lsb of Rs are meaningful
Rt
Rd
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Slt Rd, Rs, Rt Rs < Rt ?
Set if less than
0 Rd
1 RdYes :
No :
Operands are signed
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
Slti Rd, Rs, Imd Rs < Imd ?
Set if less than immediate 0 Rd
1 RdYes :
No :
Operands are signedImd is sign extended
opcod rs rd imd
I format
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rs rt rd func
R format
Sltu Rd, Rs, Rt Rs < Rt ?
Set if less than unsigned 0 Rd
1 RdYes :
No :
Operands are unsigned
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
Sltiu Rd, Rs, Imd Rs < Imd ?
Set if less than immediate, unsigned
0 Rd
1 RdYes :
No :
Operands are unsignedImd is zero extended
opcod rs rd imd
I format
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Pirouz Bazargan Sabet December 2003
Arithmetic and logic
Assembly language Action Format
opcod rd imd
I format
Lui Rd, Imd Imd << 16 Rd
load upper immediate
0 0 0 0 Rd