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F28PL1 Programming Languages
Lecture 2: Assembly Language 1
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CISC & RISC
• CISC: complex instruction set computer• original CPUs very simple• poorly suited to evolving high level languages • extended with new instructions– e.g. function calls, non-linear data structures, array bound
checking, string manipulation
• implemented in microcode– sub-machine code for configuring CPU sub-components– 1 machine code == > 1 microcode
• e.g. Intel X86 architecture
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CISC & RISC
• CISC introduced integrated combinations of features– e.g. multiple address modes, conditional execution– required additional circuitry/power– multiple memory cycles per instruction– over elaborate/engineered
• many feature combinations not often used in practise
• could lead to loss of performance• better to use combinations of simple instructions
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CISC & RISC
• RISC: reduced instruction set computer• return to simpler design• general purpose instructions with small number of
common features– less circuitry/power– execute in single cycle
• code size grew• performance improved• e.g. ARM, MIPS
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ARM
• Advanced RISC Machines• UK company• originally Acorn– made best selling BBC Microcomputer in 1980s
• world leading niche processors– 2009: 90% of all embedded processors– mobile phones, media players, games, peripherals etc– e.g. Nokia, iPod, iPad, Blackberry, Nintendo
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ARM
• 32 bit RISC processor architecture family• many variants • general reference in library:– W. Hohl, ARM Assembly Language, CRC Press, 2009– ARM7TDMI
• ARM does not make chips• licences the IP core (intellectual property) logic
design to chip manufacturers
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Cortex-M3
• ARM CPU in STM32-Discovery board• Thumb2 instruction set– based on ARMV7– subset of full ARM instructions– 16 bit length instructions
• Cortex-M3 manual• http://infocenter.arm.com/help/topic/com.arm.doc.dui05
52a/DUI0552A_cortex_m3_dgug.pdf
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MDK-ARM
• ARM development environment for:– C & assembler– many ARM-based systems
• includes simulator• free restricted download via:• http://www.keil.com/arm/mdkbasic.asp
• MDK-ARM/Cortex-M3 guide• http://www.st.com/internet/com/TECHNICAL_RESOURCES
/TECHNICAL_LITERATURE/USER_MANUAL/CD00283786.pdf
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Cortex-M3 memory map
• linear 4GB address space
• modified Harvard architecture in CPU
Code
SRAM
Peripheral
External RAM
External Device
Vendor SpecificExternal Peripheral BusInternal Peripheral Bus
0x00000000
0x20000000
0x40000000
0x60000000
0xA0000000
0xE00400000xE0000000
0xE0100000
0xFFFFFFFF
0.5GB
1GB
1GB
0.5GB
0.5GB
0.5GB
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Memory
• linear addressing • 2 descending stacks– main stack– process stack – used by OS
• all operations based on registers• must move data between registers & memory
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Registers
• 16 * 32 bit registers• working registers– R0-R7 – low registers– R8-R12 – high registers
• R13 – stack pointer (SP)• R14 - link register (LR)• R15 – program counter (PC)• PSR – program status register– bits for negative (N), zero (Z), carry (C), overflow (V)
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Data formats
• word – 32 bits– long
• half word– 16 bits– int
• byte – 8 bits– char
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Programming approach
• in high level programming:– identify variables & types– compiler maps these to memory & data representation– use of memory v registers invisible
• in low level programming– must make explicit use of memory & registers– must choose data representation
• registers much faster than memory• try to map variables to registers• what if more variables than registers...?
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Example: sum of 1st 10 integers
• we write:#define MAX 11int s;int n;n = 0;while(n<MAX){ s = s+n; n = n+1;}
• C compiler generates:MOVS r2,#0x00
MOVS r1,#0x00B TEST
LOOP ADD r2,r2,r1ADDS r1,r1,#1
TEST CMP r1,#0x0ABLT LOOP
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Example: sum of 1st 10 integers
• we write:#define MAX 11int s;int n;n = 0;while(n<MAX){ s = s+n; n = n+1;}
• C compiler generates:MOVS r2,#0x00
MOVS r1,#0x00B TEST
LOOP ADD r2,r2,r1ADDS r1,r1,#1
TEST CMP r1,#0x0ABLT LOOP
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Example: sum of first 10 integers
• s == r2 - register 2• n == r1 – register 1
MOVS r2,#0x00• move hexadecimal constant 0x00 to register 2 • set condition code flags MOVS r1,#0x00• move hexadecimal constant 0x00 to register 2 • set condition code flags
B TEST• branch to label TEST
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Example: sum of first 10 integers
LOOP ADD r2,r2,r1• label LOOP• put in r2 sum of r2 and r1
ADDS r1,r1,#1• put in r1 sum of r1 and decimal constant #1• set condition code flags
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Example: sum of first 10 integers
TEST CMP r1,#0x0A• label TEST• compare r1 and hexadecimal constant #0x0A == 10• set condition code flags
BLT LOOP• branch to label LOOP if flags indicate “less than”
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Instruction format
mnemonic operands– general format– operands depend on instruction
mnemonic – meaningful short form– reminds us what instruction does
• ARM uses {...} for options• Rd or Rm == register -r0..r15
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Operands
• first operand usually rd• Operand2 == flexible 2nd operand– constant – Rm
• constant == 8 hexadecimal digits• constant == decimal – size of decimal depends on instruction
• #imm16 == 0-65535 == 16 bit
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MOV: move
MOV Rd, Operand2 Rd = Operand2• don’t update condition code flagsMOVS Rd, Operand2• as MOV but update condition code flagsMOV Rd, #imm16 Rd = imm16
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ADD: addition
ADD Rd, Rn, Operand2 Rd = Rn+Operand2ADD Rn, Operand2 Rn = Rn+Operand2ADDC• add with carry • like ADD + carry flagADDS/ADDCS• like ADD/ADDC but set condition code flags
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SUB: subtraction
SUB Rd, Rn, Operand2 Rd = Rn-Operand2SUB Rn, Operand2 Rn = Rn-Operand2SUBC• subtract with carry • like SUB -1 if carry flag not setSUBS/SUBCS• like SUB/SUBC but set condition code flags
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CMP: compare
CMP Rn, Operand2• subtract Operand2 from Rn BUT ...• ... do not modify Rn – otherwise same as SUBS
• update Z, N, C, V flagsCMN RN, Operand2• add Operand2 to Rn BUT ...• ... do not modify Rn• otherwise same as ADDS
• update Z, N, C, V flags
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Flags
• N – 1 if result <0; 0 otherwise• Z – 1 if result =0; 0 otherwise• C – 1 if result led to carry; 0 otherwise– i.e. X+Y > 232
– i.e. X-Y >= 0
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Flags
• V – 1 if result led to overflow; 0 otherwise• (-) == negative• (+) == positive
– i.e. (-)X+(-)Y > 0– i.e. (+)X+(+)Y < 0– i.e. (-)X-(+)Y > 0– i.e. (+X)-(-Y) < 0
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B: branch
B label• branch to label• i.e. reset PC to address for labelBcond label• branch on condition to label
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conditionsuffix flagsEQ == equal Z=1NE == not equal Z=0CS/HS == carry set/ higher or same - unsigned C=1CC/LO == carry clear/lower - unsigned C=0MI == negative N=1PL == positive or 0 N=0VS == overflow V=1VC == no overflow V=0
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conditionsuffix flagsHI == higher - unsigned C=1 & Z=0LS == lower or same - unsigned C=0 or Z=1GE == greater than or equal - signed N=VLT == less than - signed N!=VGT == greater than - signed Z=0 & N=VLE == less than or equal, signed Z=1 & N!=VAL == any value default if not
cond
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Label
• identifier• can precede any line of assembler• represents the address of:– instruction– literal data
• relative to program counter (PC)• turned into PC + offset in machine code
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NOP: no operation
NOP• do nothing• use for padding/layout• no cost
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Layout
• ARM assembly language is layout sensitive• must precede instruction with a tab• for labelled instruction, use tab immediately after
label• can’t use equivalent number of spaces
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Example: multiply by adding
• m == x*yint x;int y;int m;x = 8;y = 10;m = 0;while(y!=0){ m = m+x; y = y-1;}
• x == R1; y == R2; m == R3MOV R1,#0x08MOV R2,#0x0AMOV R3,#0x00
LOOP CMP R2,#0x00BEQ DONEADD R3,R1SUB R2,#0x01B LOOP
DONE NOP
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Register name definition
name RN expression• expression 0..15• name renames the
registere.g.x RN 1y RN 2m RN 3
MOV x,#0x08MOV y,#0x0AMOV m,#0x00
LOOP CMP y,#0x00BEQ DONEADD m,xSUB y,#0x01B LOOP
DONE NOP
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Constant name definition
name EQU expression• name is replace with
value from expressione.g.x RN 1y RN 2m RN 3xinit EQU 8yinit EQU 10
MOV x,#xinitMOV y,#yinitMOV m,#0x00
LOOP CMP y,#0x00BEQ DONEADD m,xSUB y,#0x01B LOOP
DONE NOP