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PROJECT REPORT
ON
SIMULATION OF GENERAL-PURPOSE
MICROPROCESSORS USING VHDL
A Project Report submitted in partial fulfilment of Bachelor of Technology
(B.Tech), 2!"2## Batch
Guide:- Submitted by:-
Mr S!ti"# S#i$de S#!r!d %#!rd&!' ()**))+,./0
R!$'eet Si$1# 2!d!3 ()*,))+,./0
A$i"#! Ar4r! ()+)))+,./0
I"#!$ C#!&5! ()+6))+,./0
%HARATI VIDH2APEETH7S COLLLEGE OF ENGINEERING
A-*8 PASCHIM VIHAR8 ROHTA9 ROAD8 NE DELHI- ))..;6
AFFILIATED TO
GURU GO%IND SINGH INDRAPRASTHA UNIVERSIT28 DELHI
AC9NOLEDGEMENT
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$e, Anisha Arora (#%###%2&!), 'shan hala (#%*##%2&!), Ranjeet +ingh ada-
(#2##%2&!), +harad Bhardaj (###%2&!) th year students of /lectronics 0
ommunications, Bharati 1idyapeeths ollege of /ngineering, 3e 4elhi are highly
than5ful to faculties for guiding us all through the completion of the report. Abo-e all e
ould li5e to ac5noledge our guide 6r.+atish +hinde for imparting his 5noledge and
-aluable e7perience.
Anisha Arora 'shan hala Ranjeet +ingh ada- +harad Bhardaj
(#%###%2&!) (#%*##%2&!) (#2##%2&!) (###%2&!)
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CERTIFICATE
This is to certify that the project report entitled SIMULATION OF GENERAL PURPOSE
MICROPROCESSORS USING VHDL hich is submitted by AnishaArora (#%###%2&!),
'shan hala (#%*##%2&!), Ranjeet +ingh ada- (#2##%2&!), +harad Bhardaj
(###%2&!) th year students of /lectronics 0 ommunications, is an authentic or5
carried by them at Bharati 1idyapeeths ollege of /ngineering (B18/) under my
guidance.
D!te:) De
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A%STRACT
Teaching9learning microprocessors in the laboratory has been traditionally carried out
using general purpose simulators and9or e-aluation boards. 'n"circuit emulators are
not idely used because of their high cost. This paper presents a softare tool
de-eloped for teaching9learning the general microprocessor in the laboratory and9or
the classroom. This softare ill include an assembler, a multimicro simulator, a
logic analy:er, and an assistant. The tool allos to simulate systems consisting of
microprocessor plus a set of e7ternal peripherals. Both the P; core and the
embedded peripherals of each microcontroller are simulated. /-erything in this
softare ill be designed ith the educational perspecti-e in mind. A set of indos
depict the configuration and beha-iour of e-ery embedded peripheral. The tool ould
be suitable for learning nearly e-erything about the microproceesors, ranging from
the P; and instruction set basics to comple7 use of timers, interrupts and the serial
port.
The main features of this softare <
i. -ery realistic simulation of both P; and embedded peripherals=
ii. easy"to"use interface=
iii. graphical indos that sho the state and configuration of the embedded
peripherals=
i-. ability to simulate the concurrent operation of se-eral microcontrollers= and
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-. ability to simulate the interaction of the microcontrollers ith e7ternal
peripherals.
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INDE=
# .'ntroduction to ..........................................................................................................#
#.# basic design methodology.....................................................................................2
#.2 analysis of se>uential circuits..............................................................................
2 'ntroduction to general purpose microprocessors...................................................%
2.# 'nstruction +et.......................................................................................................?
2.2 To operand instructions......................................................................................!
2.* 8ne operand instructions...................................................................................... &
2. 'nstruction using a memory address..................................................................... &
2.% @ump instructions...................................................................................................&
* 4atapath.................................................................................................................#2
*.# input multiple7er.................................................................................................#%
*.2 conditional flags.................................................................................................#%
*.* Accumulator........................................................................................................#%
*. Register file.........................................................................................................#?*.% A;....................................................................................................................#?
*.? +hifter9rotator.....................................................................................................#!
*.! 8utput buffer......................................................................................................#&
*.& ontrol ord......................................................................................................#&
ontrol unit.........................................................................................................#
.# reset...................................................................................................................#
.2 fetch...................................................................................................................2
.* decode...............................................................................................................2
. e7ecute..............................................................................................................2
% P;....................................................................................................................22
?. 6emory..............................................................................................................2*
!. loc5(timing issues) ..........................................................................................2?
&. +imulation result.................................................................................................2!.
. onclusion...........................................................................................................2&
References..........................................................................................................2
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Appendi7.............................................................................................................*
LIST OF FIGURES
Cigure name Page no.
Basic design methodology *
Cinite state model
Architecture of general purpose microprocessor ?
4atapath #
+tate diagram for control unit #
P; 22
RA6 chip 2*
D RA6 chip circuit 2%
+imulation result of 4' A,! 2!
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LIST OF TA%LES
Table name Page no.
'nstruction set ##
A; #?
+hifter9Rotator #!
ontrol ord signals for datapath #&
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) INTRODUCTION TO VHDL
1E4 stands for very high-speed integrated circuit hardare description language. $hich is
one of the programming language used to model a digital system by dataflo,
beha-ioral and structural style of modeling. This language as first introduced in #
for the department of 4efense (4o4) under the 1E+' programe. 'n #&* 'B6, Te7as
instruments and 'ntermetrics started to de-elop this language. 'n #&% 1E4 !.2
-ersion as released in #&! '/// standardi:ed the language.
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)) De"i1$
1E4 is commonly used to rite te7t models that describe a logic circuit. +uch a model is
processed by a synthesis program, only if it is part of the logic design. A simulation program
is used to test the logic design using simulation models to represent the logic circuits that
interface to the design. This collection of simulation models is commonly called a testbench.
1E4 has file input and output capabilities, and can be used as a general"purpose language
for te7t processing, but files are more commonly used by a simulation testbench for stimulus
or -erification data. There are some 1E4 compilers hich build e7ecutable binaries. 'n this
case, it might be possible to use 1E4 to rite a testbench to -erify the functionality of the
design using files on the host computer to define stimuli, to interact ith the user, and to
compare results ith those e7pected. Eoe-er, most designers lea-e this job to the simulator.
't is relati-ely easy for an ine7perienced de-eloper to produce code that simulates
successfully but that cannot be synthesi:ed into a real de-ice, or is too large to be practical.
8ne particular pitfall is the accidental production of transparent latches rather than 4"type
flip"flops as storage elements.
1E4 is not a case sensiti-e language. 8ne can design hardare in a 1E4 '4/ (for CPFA
implementation such as Gilin7 '+/, Altera Huartus, or +ynopsys +ynplify) to produce the
RT schematic of the desired circuit. After that, the generated schematic can be -erified using
simulation softare hich shos the a-eforms of inputs and outputs of the circuit after
generating the appropriate testbench. To generate an appropriate testbench for a particular
circuit or 1E4 code, the inputs ha-e to be defined correctly. Cor e7ample, for cloc5 input, a
loop process or an iterati-e statement is re>uired.
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The 5ey ad-antage of 1E4 hen used for systems design is that it allos the beha-ior of
the re>uired system to be described (modeled) and -erified (simulated) before synthesis tools
translate the design into real hardare (gates and ires).
Another benefit is that 1E4 allos the description of a concurrent system (many parts,
each ith its on sub"beha-ior, or5ing together at the same time). 1E4 is a 4ataflo
language, unli5e procedural computing languages such as BA+', , and assembly code,
hich all run se>uentially, one instruction at a time.
A final point is that hen a 1E4 model is translated into the Igates and iresI that are
mapped onto a programmable logic de-ice such as a P4 or CPFA, then it is the actual
hardare being configured, rather than the 1E4 code being Ie7ecutedI as if on some form
of a processor chip.
FIGURE ): %ASIC DESIGN METHODOLOG2
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1.2 A$!5y"i" 4> Se?ue$ti!5 Ciruential circuits are as follos<
#. 4eri-e the e7citation e>uations from the ne7t"state logic circuit.
2. 4eri-e the ne7t"state e>uations by substituting the e7citation e>uations into the flip"flops
characteristic e>uations.
*. 4eri-e the ne7t"state table from the ne7t"state e>uations.
. 4eri-e the output e>uations (if any) from the output logic circuit.
%. 4eri-e the output table (if any) from the output e>uations.
?. 4ra the state diagram from the ne7t"state table and the output table
FIGURE ,: Fi$ite-"t!te m!
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,I$tr4du
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e7tracts the opcode bits from the instruction and determines hat the current instruction is by
jumping to the state that has been assigned for e7ecuting that instruction. 8nce in
that particular state, the finite"state machine performs step * by simply asserting the
appropriate control signals for controlling the datapath to e7ecute that instruction.
C'F;R/ *uence=
*) arithmetic and logical instructions for performing arithmetic and logics= and
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) input 9 output and miscellaneous instructions.
There are fi-e data mo-ement instructions, eight jump instructions, ten arithmetic and logic
instructions, to input9output instructions, and to miscellaneous instructions.
The number of instructions implemented determines the number of bits re>uired to encode all
the instructions.
All instructions are encoded using one byte e7cept for instructions that ha-e a memory
address as one of its operand, in hich case a second byte for the address is needed. The
encoding scheme uses the first four bits as the opcode. 4epending on the opcode, the last four
bits are interpreted differently as follos.
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8ne"operand instructions alays use the accumulator and the result is stored bac5 in the
accumulator. 'n this case, the last four bits in the encoding are used to further decode the
instruction. An e7ample of this is the '3 (increment accumulator) instruction. The opcode
(###) is used by all the one"operand arithmetic and logical instructions. The last four bits
(#) specify the '3 instruction.
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the first four bits (##) specify the unconditional jump. The ne7t four bits (#) specify
that it is a relati-e jump because it is not :ero. The relati-e position to jump to is K because
the first bit is a , hich is for forard and the last three bits e-aluate to . To jump bac5ard
by four locations, e ould use ## instead. To conditional flags (:ero and positi-e) are
used conditional jumps. These flags are set or reset depending on the -alue of the
accumulator hen the accumulator is ritten to. 'nstructions that modify the accumulator
include 4A, 46, 4', all the arithmetic and logic instructions, and '3. Cor e7ample, if
the result of the A44 instruction is a positi-e number, then the :ero flag ill be reset and the
positi-e flag ill be set. A conditional jump then reads the -alue of these flags to see hether
to jump or not. The @L instruction ill not jump after the pre-ious A44 instruction, here as
the @P instruction ill perform the jump.
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TAB/ #
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6D!t!!t#
The d!t!!t# is responsible for the manipulation of data. 't includes (#) functional units
such as adders, shifters, multipliers, A;s, and comparators, (2) registers and other memory
elements for the temporary storage of data, and (*) buses and multiple7ers for the transfer of
data beteen the different components in the datapath. /7ternal data can be entered into the
datapath through the data input lines. Results from the computation are pro-ided through the
data output lines.
'n order for the datapath to function correctly, appropriate
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the datapath, therefore, must contain an adder. 'f the problem re>uires the storage of three
temporary -ariables, the datapath must ha-e three registers.
Eoe-er, e-en ith these re>uirements, there are still many options as to hat is actually
implemented in the datapath. Cor e7ample, an adder can be implemented as just a single
adder circuit, or as part of the A;. Registers can be separate register units or combined in a
register file. Curthermore, to temporary -ariables can share the same register if they are not
needed at the same time. 4atapath design is also referred to as the re1i"ter-tr!$">er 5e3e5
(RTL) design. 'n the register"transfer le-el design, e loo5 at ho data is transferred from
one register to another or bac5 to the same register. 'f the same data is ritten bac5 to a
register ithout any modifications, then nothing has been accomplished. +o before riting
the data to a register, the data passes through one or more functional units and gets modified.
The time from the reading of the data to the modifying of the data by functional units and
finally to the riting of the data bac5 to a register must all happen ithin one cloc5 cycle
The idth of the datapath is eight bits, i.e. all the connections for data mo-ement are eight
bits ide. 'n the figure, they are the thic5er lines. The remaining thinner control lines are all
one bit ide unless the name for that control line has a number subscript such as
rfaddr_dp2,#,, in hich case there are as many lines as the subscript numbers. Cor e7ample,
the control line label rfaddr_dp2,#, is actually composed of three separate lines.
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C4m4$e$t" 4> d!t!!t#
6) I$ut mu5ti5eBer:
The "to"# input mu7 at the top of the datapath draing selects one of four different inputs to
be ritten into the accumulator. These four inputs, starting from the left, are<
(#) imm_dp for getting the immediate -alue from the 4' instruction and storing it into the
accumulator=
(2) input_dp for getting a user input -alue for the '3 instruction=
(*) the ne7t input selection allos the content of the register file to be ritten to the
accumulator as used by the 4A instruction=
() allos the result of the A; and the shifter to be ritten to the accumulator as used by all
the arithmetic and logical instructions.
6, C4$diti4$!5 F5!1":
The to conditional flags, :ero and positi-e, are set by to comparators that chec5 the -alue
at the output of the mu7 hich is the -alue that is to be ritten into the accumulator for these
to conditions. To chec5 for a -alue being :ero, recall that just a 38R gate ill do. 'n our
case, e need an eight"input 38R gate because of the &"bit ide databus. To chec5 for a
positi-e number, e simply need to loo5 at the most significant sign bit. A 2s complement
positi-e number ill ha-e a :ero sign bit, so a single in-erter connected to the most
significant bit of the databus is all that is needed to generate this positi-e flag signal.
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rst_dp, so that the accumulator is alays cleared on reset. The content of the accumulator is
alays a-ailable at the accumulator output. The -alue from the accumulator is sent to three
different places< (#) it is sent to the output buffer for the 8;T instruction= (2) it is used as the
first (A) operand for the A;= and (*) it is sent to the input of the register file for the +TA
instruction.
6* Re1i"ter Fi5e:
The register file has eight locations, each &"bits ide. Three address lines, rfaddr_dp2,
rfaddr_dp#, rfaddr_dp, are used to address the eight locations for both reading and riting.
There are one read port and one rite port. The read port is alays acti-e hich means that it
alays has the -alue from the currently selected address location. Eoe-er, to rite to the
selected location, the rite control line rfwr_dp must be asserted before a -alue is ritten to
the currently selected address location.
3ote that a separate read and rite address lines is not re>uired because all the instructions
either perform just a read from the register file or a rite to the register file. There is no one
instruction that performs both a read and a rite to the register file. Eence, only one set of
address lines is needed for determining both the read and rite locations.
6+
ALU
The A; has eight operations implemented as defined by the folloing table. The
operations are selected by the three select lines alusel_dp2, alusel_dp#, and alusel_dp.
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TAB/ 2
The select lines are asserted by the corresponding A; instructions as shon under the
Instruction column in the abo-e table. The pass through operation is used by all non"A;
instructions.
6; S#i>ter R4t!t4r:
The +hifter has four operations implemented as defined by the folloing table. The
operations are selected by the to select lines shiftsel_dp#, and shiftsel_dp.
TAB/ *
The select lines are asserted by the corresponding +hifter9Rotator instructions as shon under
the Instruction column in the abo-e table. The pass through operation is used by all non"
+hifter9Rotator instructions.
6/ Outut %u>>er:
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The output buffer is a register ith an enable control signal connected to outen_dp. $hene-er
the enable line is asserted, the output from the accumulator is stored into the buffer. The -alue
stored in the output buffer is used as the output for the computer and is alays a-ailable. The
enable line is asserted either by the 8;T A instruction or by the system reset signal.
6 C4$tr45 4rd:
Crom Cigure 2, e see that the control ord for this custom datapath has fourteen bits, hich
maps to the control signals for the different datapath components. These fourteen control
signals are <
TA%LE *: C4$tr45 &4rd "i1$!5" >4r t#e d!t!!t#
*C4$tr45 U$it
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The finite state machine for the control unit basically cycles through four main states< reset,
fetch, decode, and e7ecute, as shon in Cigure. There is one e7ecute state for each instruction
in the instruction set.
C'F;R/ %
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'n the fetch state, the memory content of the location pointed to by the P is loaded into the
instruction register. The P is then incremented by one to prepare it for fetching the ne7t
instruction. 'f the fetched instruction is a jump instruction, then the P ill be changed
accordingly during the e7ecution phase.
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and by chec5ing on the :ero and positi-e flags. 'f a jump is needed then the target address is
calculated and then assigned to the P.
At the end of the e7ecute state, the C+6 goes bac5 to the fetch state and the cycle repeats for
the ne7t instruction.
+CPU
3o that e ha-e defined both the datapath and the control unit, e are ready to connect the
to together to create our -ery on custom general microprocessor. The necessary signals
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that need to be connected beteen the to units are just the control ord signals, that the
control unit has to generate for controlling the datapath. 'n addition to the control signals,
there are also to conditional flag signals (:ero and positi-e) that the datapath generates as
status signals for the control unit to use. The interface beteen the datapath and the control
unit is shon in figure. The primary inputs to the P; module are cloc5, reset, and data
input. The primary output from the P; module is the data output, addressJJJ.
C'F;R/ ?< P;
; Mem4ry
Another main component in a computer system is memory. This can refer to as either random
access memory (RA6) or read"only memory (R86). $e can ma5e memory the same ay
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e ma5e the register file but ith more storage locations. Eoe-er, there are se-eral reasons
hy e dont ant to. 8ne reason is that e usually ant a lot of memory and e ant it
-ery cheap, so e need to ma5e each memory cell as small as possible. Another reason is
that e ant to use a common data bus for both reading data from, and riting data to the
memory. This implies that the memory circuit should ha-e just one data port and not to or
three li5e the register file. The logic symbol, shoing all the connections for a typical RA6
chip is shon in figure.There is a set of data lines Di, and a set of address lines Ai. The data
lines ser-e for both input and output of the data to the location that is specified by the address
lines. The number of data lines is dependent on ho many bits are used for storing data in
each memory location. The number of address lines is dependent on ho many locations are
in the memory chip. Cor e7ample, a %#2"byte memory chip ill ha-e eight data lines (& bits M
# byte) and nine address lines (2O M %#2).
'n addition to the data and address lines, there are usually to control lines< chip enable (CE ),
and rite enable (W). 'n order for a microprocessor to access memory, either ith the read
operation or the rite operation, the acti-e high CE line must first be asserted. Asserting the
CE line enables the entire memory chip. The acti-e high W line selects hich of the to
memory operations is to be performed. +etting W to a selects the read operation, and
data from the memory is retrie-ed. +etting W to a # selects the rite operation, and data
from the microprocessor is ritten into the memory. 'nstead of ha-ing just the W line for
selecting the to operations read and rite, some memory chips ha-e both a read enable and
a rite enable line. 'n this case, only one line can be asserted at any one time. The memory
location in hich the read and rite operation is to ta5e place, of course, is selected by the
-alue of the address lines. The operation of the memory chip is shon in Cigure.
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C'F;R/ !< A 2On ⋅ m RA6 chip< (a) logic symbol= (b) operation table.
To create a ⋅ static RA6 chip, e need si7teen memory cells forming a ⋅ grid as
shon in Cigure ./ach ro forms a single storage location, and the number of memory cells
in a ro determines the bit idth of each location. +o all the memory cells in a ro are
enabled ith the same address. Again, a decoder is used to decode the address lines A and
A#. 'n this e7ample a 2"to" decoder is used to decode the four address locations. The CE
signal is for enabling the chip, specifically to enable the read and rite functions through the
to A34 gates. The internal WE signal, asserted hen both the CE and W signals are
asserted, is used to assert the Write enables for all the memory cells. The data comes in from
the e7ternal data bus through the input buffer and to the Input line of each memory cell. The
purpose of using an input buffer for each data line is so that the e7ternal signal coming in
only needs to dri-e just one de-ice (the buffer) rather than ha-ing to dri-e se-eral de-ices
(i.e. all the memory cells in the same column). $hich ro of memory cells actually gets
ritten to ill depend on the gi-en address. The read operation re>uires CE to be asserted,
and W to be de"asserted. This ill assert the internal E signal, hich in turn ill enable the
four output tri"state buffers at the bottom of the circuit diagram. Again, the location that is
read from is selected by the address lines.
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C'F;R/ &< A D RA6 E'P 'R;'T
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FIGURE : LDI A8./
CONCLUSION
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The project as an attempt to simulate a basic microprocessor design using 1E4. $e ha-e
used mi7ed style of modelling in the coding of the processor. 'n this e ha-e made our on
instruction set and simulated the instructions. The instructions are successfully simulated.
'n future, e can add more instructions to the instruction set according to our need. The
program can be synthesi:ed and then can be burned into CPFA.
REFERENCES
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) E$4+O"b4r$e8Ad!m ().0 A$ I$tr4du
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entity acc is
port(cl5acc< in stdlogic=
rstacc< in stdlogic=
racc< in stdlogic=
inputacc< in stdlogic-ector (! donto )=outputacc< 8;T stdlogic-ector (! donto ))=
end acc=
architecture acc of acc is
signal d
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constant A34A < stdlogic-ector(* donto )
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aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +#=
"" load program memory ith statements
P6()
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hen 6'+ M "" '98 and miscellaneous instructions
case 'R(# donto ) is
hen '3A M state M +%#=
hen 8;TA M state M +%2=
hen EAT M state M +=
hen others M state M +=end case=
hen others M state M +=
end case=
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=hen +& M "" set :ero and positi-e flags and then goto ne7t instruction
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +#=
:eroflag
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mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M 'R(2 donto )=
rfrctrl M Q#Q=
aluselctrl M II=shiftselctrl M II=
outenctrl M QQ=
state M +#=
hen +#2 M "" 46
mu7selctrl M I#I=
immctrl M (others M QQ)=
accrctrl M Q#Q=
rfaddrctrl M II=
rfrctrl M Q#Q=
aluselctrl M II=
shiftselctrl M II=outenctrl M QQ=
state M +=
hen +#* M "" +T6
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +=
hen +# M "" 4' "" 8S
mu7selctrl M I##I=
immctrl M P6(P)=
P
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end if=
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +#=
hen +22 M "" @L
if (:eroflagMQ#Q) then "" may need T8 ;+/ :eroflag instead
if ('R(* donto ) M II) then
"" absolute
'R
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aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +#=
hen +2 M "" @P
if (positi-eflagMQ#Q) then "" may need T8 ;+/ positi-eflag insteadif ('R(* donto ) M II) then
"" absolute
'R
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immctrl M (others M QQ)=
rfaddrctrl M 'R(2 donto )=
rfrctrl M QQ=
aluselctrl MI#I=
shiftselctrl M II=
outenctrl M QQ=accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +** M "" +;B "" 8S
mu7selctrl MII=
immctrl M (others M QQ)=
rfaddrctrl M 'R(2 donto )=
rfrctrl M QQ=
aluselctrl MI##I=
shiftselctrl M II=
outenctrl M QQ=accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +# M "" 38TA "" 8S
mu7selctrl MII=
immctrl M (others M QQ)=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl MI##I=
shiftselctrl M II=
outenctrl M QQ=
accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +2 M "" '3 "" 8S
mu7selctrl MII=
immctrl M (others M QQ)=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl MI##I=
shiftselctrl M II=outenctrl M QQ=
accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +* M "" 4/ "" 8S
mu7selctrl MII=
immctrl M (others M QQ)=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl MI###I=
shiftselctrl M II=outenctrl M QQ=
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accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen + M "" +EC
mu7selctrl MII=
immctrl M (others M QQ)=rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II= "" pass
shiftselctrl M I#I=
outenctrl M QQ=
accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +% M "" +ECR "" 8S
mu7selctrl MII=
immctrl M (others M QQ)=rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II= "" pass
shiftselctrl M I#I=
outenctrl M QQ=
accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +? M "" R8TR "" JJ
mu7selctrl MII=
immctrl M (others M QQ)=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II= "" pass
shiftselctrl M I##I=
outenctrl M QQ=
accrctrl MQ#Q= "" rite occurs '3 the ne7t cycle
state M +&=
"" state M += "" need one e7tra cycle T8 rite bac5 result
hen +%# M "" '3A
mu7selctrl M I#I=immctrl M (others M QQ)=
accrctrl M Q#Q=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +&=
"" state M +=
hen +%2 M "" 8;TA
mu7selctrl M II=immctrl M (others M QQ)=
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accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M Q#Q=state M +#=
"" state M +=
hen + M "" EAT
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=state M +=
hen others M
mu7selctrl M II=
immctrl M (others M QQ)=
accrctrl M QQ=
rfaddrctrl M II=
rfrctrl M QQ=
aluselctrl M II=
shiftselctrl M II=
outenctrl M QQ=
state M +=
end case=
end if=
end process=
end fsm=
entity dp is
port (cl5dp< in stdlogic=
rstdp< in stdlogic=
mu7seldp< in stdlogic-ector(# donto )=
immdp< in stdlogic-ector(! donto )=
inputdp< in stdlogic-ector(! donto )=accrdp< in stdlogic=
rfaddrdp< in stdlogic-ector(2 donto )=
rfrdp< in stdlogic=
aluseldp< in stdlogic-ector(2 donto )=
shiftseldp< in stdlogic-ector(# donto )=
outendp< in stdlogic=
:erodp< out stdlogic=
positi-edp< out stdlogic=
outputdp< out stdlogic-ector(! donto ))=
end dp=
architecture struct of dp iscomponent mu7 is
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port (selmu7< in stdlogic-ector(# donto )=
in*mu7,in2mu7,in#mu7,inmu7< in stdlogic-ector(! donto )=
outmu7< out stdlogic-ector(! donto ))=
end component=
component acc is port (cl5acc< in stdlogic=
rstacc< in stdlogic=
racc< in stdlogic=
inputacc< in stdlogic-ector (! donto )=
outputacc< out stdlogic-ector (! donto ))=
end component=
component regfile is
port (cl5rf< in stdlogic=
rrf< in stdlogic=
addrrf< in stdlogic-ector(2 donto )=inputrf< in stdlogic-ector(! donto )=
outputrf< out stdlogic-ector(! donto ))=
end component=
component alu is
port (selalu< in stdlogic-ector(2 donto )=
inAalu< in stdlogic-ector(! donto )=
inBalu< in stdlogic-ector(! donto )=
8;Talu< out stdlogic-ector (! donto ))=
end component=
component shifter is
port (selshift< in stdlogic-ector(# donto )=
inputshift< in stdlogic-ector(! donto )=
outputshift< out stdlogic-ector(! donto ))=
end component=
component tristatebuffer is
port (/< in stdlogic=
4< in stdlogic-ector(! donto )=
< out stdlogic-ector(! donto ))=end component=
signal aluout,accout,rfout,mu7out,shiftout< stdlogic-ector(! donto )=
signal outen< stdlogic=
begin
;< mu7 port map(mu7seldp,immdp,inputdp,rfout,shiftout,mu7out)=
;#< acc port map(cl5dp,rstdp,accrdp,mu7out,accout)=
;2< regfile port map(cl5dp,rfrdp,rfaddrdp,accout,rfout)=
;*< alu port map(aluseldp,accout,rfout,aluout)=
;< shifter port map(shiftseldp,aluout,shiftout)=
outen M outendp or rstdp=;%< tristatebuffer port map(outen,accout,outputdp)= ""outputdp M accout=
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:erodp M Q#Q hen (mu7out M II) else QQ=
positi-edp M not mu7out(!)= ""positi-edp M Q#Q $E/3 (mu7out(!) M QQ) /+/ QQ=
end struct=
entity mu7 is
port (selmu7< in stdlogic-ector(# donto )=in*mu7,in2mu7,in#mu7,inmu7< in stdlogic-ector(! donto )=
outmu7< out stdlogic-ector(! donto ))=
end mu7=
architecture mu7 of mu7 is
begin
process(selmu7)
begin
case selmu7 is
hen II M outmu7Minmu7=
hen I#I M outmu7Min#mu7=
hen I#I M outmu7Min2mu7=hen others M outmu7Min*mu7=
end case=
end process=
end mu7=
entity regfile is
port(cl5reg< in stdlogic=
rreg< in stdlogic=
addrreg< in stdlogic-ector(2 donto )=
inputreg< in stdlogic-ector(! donto )=
outputreg< out stdlogic-ector(! donto ))=
end regfile=
architecture regfile of regfile is
type mem is array ( to !) of stdlogic-ector(! donto )=
signal d
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d()Minputreg=
outputregMinputreg=
elsif(addrregMI##I) then
d(%)Minputreg=
outputregMinputreg=
elsif(addrregMI##I) thend(?)Minputreg=
outputregMinputreg=
elsif(addrregMI###I) then
d(!)Minputreg=
outputregMinputreg=
end if=
else
if(addrregMII) then
outputregMd()=
elsif(addrregMI#I) then
outputregMd(#)=elsif(addrregMI#I) then
outputregMd(2)=
elsif(addrregMI##I) then
outputregMd(*)=
elsif(addrregMI#I) then
outputregMd()=
elsif(addrregMI##I) then
outputregMd(%)=
elsif(addrregMI##I) then
outputregMd(?)=
elsif(addrregMI###I) then
outputregMd(!)=
end if=
end if=
end if=
end process=
end regfile=
entity shifter is
port (selshift< in stdlogic-ector(# donto )=
inputshift< in stdlogic-ector(! donto )=outputshift< out stdlogic-ector(! donto ))=
end shifter=
architecture shifter of shifter is
begin
process(selshift,inputshift)
begin
if (selshiftMII) then
outputshiftMinputshift=
elsif (selshiftMI#I) then
outputshiftMshl(inputshift,I#I)=
elsif (selshiftMI#I) thenoutputshiftMshr(inputshift,I#I)=
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elsif (selshiftMI##I) then
outputshiftM tostdlogic-ector(Tobit-ector(inputshift) ror #)=
end if=
end process=
end shifter=
entity tristatebuffer is
port (e< in stdlogic=
d< in stdlogic-ector(! donto )=
y< out stdlogic-ector(! donto ))=
end tristatebuffer=
architecture tri of tristatebuffer is
begin
process(e,d)
begin
if (eMQ#Q) then
yMd=else
yM(othersMQLQ)=
end if=
end process=
end tri=
entity cpu is
port (cl5cpu< stdlogic=
rstcpu< in stdlogic=
inputcpu< in stdlogic-ector(! donto )=
outputcpu< out stdlogic-ector(! donto ))=
end cpu=
architecture structure of cpu is
component ctrl
port (cl5ctrl< in stdlogic=
rstctrl< in stdlogic=
mu7selctrl< out stdlogic-ector(# donto )=
immctrl< out stdlogic-ector(! donto )=
accrctrl< out stdlogic=
rfaddrctrl< out stdlogic-ector(2 donto )=
rfrctrl< out stdlogic=aluselctrl< out stdlogic-ector(2 donto )=
shiftselctrl< out stdlogic-ector(# donto )=
outenctrl< out stdlogic=
:eroctrl< in stdlogic=
positi-ectrl< in stdlogic)=
end component=
component dp
port(cl5dp< in stdlogic=
rstdp< in stdlogic=
mu7seldp< in stdlogic-ector(# donto )=immdp< in stdlogic-ector(! donto )=
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inputdp< in stdlogic-ector(! donto )=
accrdp< in stdlogic=
rfaddrdp< in stdlogic-ector(2 donto )=
rfrdp< in stdlogic=
aluseldp< in stdlogic-ector(2 donto )=
shiftseldp< in stdlogic-ector(# donto )=outendp< in stdlogic=
:erodp< out stdlogic=
positi-edp< out stdlogic=
outputdp< out stdlogic-ector(! donto ))=
end component=
signal immediate< stdlogic-ector(! donto )= ""+'F3A 4immediate<
stdlogic-ector(! 48$3T8 )=
signal accr,rfr,outen,:ero,positi-e< stdlogic=
signal mu7sel,shiftsel< stdlogic-ector(# donto )=
signal rfaddr,alusel< stdlogic-ector(2 donto )= begin
;< ctrl port
map(cl5cpu,rstcpu,mu7sel,immediate,accr,rfaddr,rfr,alusel
,shiftsel,outen,:ero,positi-e)=
;#< dp port
map(cl5cpu,rstcpu,mu7sel,immediate,inputcpu,accr,rfaddr,rfr
,alusel,shiftsel,outen,:ero,positi-e,outputcpu)=
end structure=