. KOLEJ UNIVERSITI TEKl\fOLOGI TUN HUSSEIN ONN
BORANG PENGESAHAN STATUS TESIS·
JUDUL: ANALYSIS OF FPGA DESIGl'\ METHODS USIl'\G Al'\ 8 BIT ALl!
SESI PENGAJIAN: 2005/2006
Saya ROSNAH BINTI MOHD ZIN
(HURUF BESAR)
mengaku membenarkan tesis (Sarjana Muda/Sarjana !Doktor Falsafah)* ini disimpan di Perpustakaan dengan syarat-syarat kegunaan seperti berik:ut:
1. Tesis adalah hakmilik Kolej Universiti Teknologi Tun Hussein Onn. 2. Perpustakaan dibenarkan membuat salinan untuk tujuan pengajian sahaja. 3. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi
pengaj ian tinggi. 4. **Sila tandakan (.y )
['--__ ] SULIT
[ ] TERHAD '-----
(Mengandungi maklumat yang berdarjah keselamatan at au kepentingan Malaysia seperti yang tcrmaktub di dalam AKTA RAHSIA RASMI 1972)
(Mengandungi maklumat TElU1AD yang tclah ditcntukan oleh organisasilbadan di mana penyelidikan dijalankan)
['--_-'--_] TIDAK TERHAD
Disahkan oleh:
•
(TANDATANGAN PENULlS) AN 'AN PENYELIA)
Alamat Tetap:
POS 510. KG PT LUBOK. 83600 SEMERAH,
PROF.MADY A A WT AR SIl\'GH NAMA PENYELIA
BA TU PAHA T • .lOHOR.
Tarikh: 29 NOVEMBER 2005 Tarikh: 29 NOVEMBER 2005
CATATAN: * Potong yang tidak berkenaan. ** Jika tesis ini SULIT atau TERHAD, sib lampirkan surat daripada pihak berk'llasalorganisasi berkenaan dengan menyatakan sekali tempoh lcsis ini perlu dikelaskan sebagai atau TERHAD. • Tesis dimaksudkan sebagai tesis bagi Ijazah doktor Falsafah dan Sarjana seeara
Penyelidikan, atau disertasi bagi pengajian seeara kerja k'llrSUS dan penyelidikan, atau Laporan Projek Sarjana ~vluda (PS:-'!).
"I hereby declare that I have read this report and in my opinion this report in terms of
content and quality requirements fulfill the purpose for award of the degree of
Master of Electrical Engineering"
Signature • •
Name of Supervisor :
Date • •
Q\ PROF. MADY A A WT AR SINGH
ANALYSIS OF FPGA DESIGN METHODS USING
AN 8 BIT ALU
ROSNAH BINTI MOHD ZIN
"This project report is presented in partial fulfilment of the requirement for the Award of
the Degree of Master of Electrical Engineering"
Faculty of Electrical and Electronic Engineering
Kolej Universiti Teknologi Tun Hussein Onn
OCTOBER, 2005
"I hereby declare that this project rep0l1 is a product of my own research
except certain extracts and summarics
whereby each has been clearly declared its source"
Signature
Author
Date
• •
: ROSNAI-I BINTI MOHD ZIN
: 29 NOVEMBER 2005
.. I I
ACKNOWLEDGEMENT
I would like to take this opportunity to ach:nowledge Assoc. Prof. Awtar Singh
all Kamail Singh and Prof. Dr. J. Baesig as my supervisor and Mr. Hinz-Hemmers my
lab supervisor for helping me in carrying out this project.
To all of those that I could not mention by name, accept my apologies and rest
assured I appreciate everything you all have done for me.
• 1 \.
V
ABSTRACT
Field Programmable Logic Arrays (FPGAs) have been growing at a rapid rate in
the past few years. F P G A is a type of logic chip that can be programmed which supports
thousand of gates and provide flexibility and low cost which is suitable for
implementing a prototype system. The existence of C A D software to support F P G A s has
grown in sophistication and it makes most user designs are now complete system and go
to production as an F P G A . This thesis will discuss on F P G A design style using an 8-bit
A L U as design hardware. Generally, the methods that used to implement the 8-bit A L U
are using schematic based entry and V H D L based entry. Implementation of 8-bit A L U
using V H D L includes a behavioral and structural description. The top level of design is
using a schematic based entry. Finally this thesis will discuss the methods that are used
in designing the 8-bit A L U in term of the flexibility, area consumption and timing
analysis. The analysis will give the user more understanding in designing digital system
using F P G A design style and give them a choice which depends on the design
requirements.
VI
ABSTRAK
FPGA telah berkembang dengan pesatnya sejak beberapa tahun kebelakangan ini.
FPGA merupakan cip logik yang boleh deprogram, menampung ribuan get dan
menyediakan kebolehpelbagaian dan mempunyai kos yang rendah dimana
membolehkan ia sesuai untuk mengimplementasi sistem prototaip. Kewujudan perisian
C A D yang menyokong perkembangan FPGA telah berkembang secara sofistikated dan
membolehkan kebanyakan rekabentuk pengguna menjadi sistem lengkap dan
menjadikan FPGA sebagai produk keluaran. Tesis ini membincangkan rekabentuk S bit
A L U menggunakan gaya FPGA. Secara umumnya, kaedah yang digunakan untuk
mengimplementasi 8 bit A L U adalah menggunakan rajah skematik dan V H D L .
Penggunaan V H D L terdiri dari behavioral dan structural description. Paras atas (top
level) rekabentuk menggunakan rajah skematik. Akhir sekali tesis ini membincangkan
kaedah yang digunakan didalam merekabentuk 8 bit A L U darisegi kebolehpelbagaian,
penggunaan ruang dan analisis pemasaan . Analisa ini akan membolehkan pengguna
lebih memahami bagaimana merekabentuk sistem digital menggunakan kaedah FPGA
dan dapat memberikan pilihan kaedah yang akan diguna pakai berdasarkan keperluan
rekebentuk.
vii
TABLE OF CONTENTS
Page TITTLE PAGE i
DECLARATION jj
DEDICATION iH
ACKNOWLEDGEMENT i v
ABSTRACT v
ABSTRAK v i
TABLE OF CONTENTS v i i
LIST OF FIGURES x i
LIST OF TABLES x i i i
LIST OF ABBREVATIONS x i v
LIST OF SYMBOLS x v i
LIST OF APPENDICES x v;j
CHAPTER I
INTRODUCTION
1
2
2
3
1.1 Overview
1.2 Project A i m
1.3 Objective
1.4 Scope o f Project
viii
CHAPTER II
LITERATURE REVIEW
2.1 Field Programmable Gate Array 4
2.1.1 General Structure of F P G A 5
2.2 F P G A Design and Programming 7
2.2.1 Programming Technologies g
2.3 A L T E R A FLEX1 OK 9
2.4 C A D Tools for F P G A 1 0
2.4.1 M A X + P L U S II ( A L T E R A Design Software 11
and Development Tools)
2.5 Advantage of F P G A Design 13
2.6 Basic of V H D L 1 5
2.6.1 The Advantage of V H D L 16
CHAPTER III
METHODOLOGY
3.1 F P G A Design Methodology 17
3.1.1 Modular Approach 17
3.1.2 Create a Schematic Macro 19
3.1.3 Create a V H D L Macro 21
3.2 Structural Description of V H D L 22
3.3 Complete V H D L Code 24
3.4 Project Design Tools 25
3.4.1 Design Entry and High Level Modeling 25
3.4.1.1 Schematic Entry 26
3.4.1.2 Hardware Description languages 26
3.4.2 Design Verification and simulation 27
3.5 System Prototyping: A L T E R A UP2 Board 27
CHAPTER IV
DESIGNING THE 8-BIT ALU
4.1
4.2
4.3
Arithmetic Logic Unit 29
Designing Using Schematic Entry 32
4.2.1 Designing the Logic Unit 32
4.2.2 Designing the Arithmetic Unit 33
4.2.2.1 Designing the A-Logic Unit 34
4.2.2.2 Designing the B-Logic Unit 35
4.2.3 Designing the Full Adder 36
4.2.4 Compiling the Arithmetic Unit 37
4.2.5 Compiling the 1 -bit A L U 39
4.2.6 Compiling the 8-bit A L U 40
Designing the 8-bit A L U Using Structural 42
Description of V H D L
4.4 Designing the 8-bit A L U Using Complete V H D L Code 44
CHAPTER V
RESULTS AND DISCUSSION
5.1 Circuit Implementation 47
5.2 Running the 8-bit A L U 49
5.3 Timing Analysis 51
5.4 Area Consumption 5?
5.5 Flexibility 54
CHAPTER VI
CONCLUSIONS
6.1 Conclusion
6.2 Suggestion for Future Work
55
56
xi
LIST OF FIGURES
FIGURE NO. TITLE P A C
1.1 The basic F P G A design methodology consists of three steps: 2
entry, implementation, and verification.
2.1 General Structure of F P G A 6
2.2 A typical logic block g
2.3 The internal layout of the F L E X 1 OK (courtesy of Altera) 9
2.4 C A D tool design f low for F P G A s 1 q
2.5 The General Design Cycle Supported by the Altera 13
MAX+plus II Software.
3.1 Design and Implementation sequence of a (a) schematic 18
and (b) H D L flow
3.2 Schematic diagram for 2:1 M U X 19
3.3 Create Default Symbol button 19
3.4 To open the symbol editor 20
3.5 A 2:1 M U X macro 20
3.6 V H D L Editor Window for the 2:1 M U X 21
3.7 Top level V H D L code using structural description 23
3.8 A V H D L code using sequential C A S E statement 24
3.9 Overall UP Prototyping Environment 28
4.1 1 bit slice of A L U 31
4.2 Schematic diagram of the Logic Unit 32
4.3 The output waveform for logic unit
4.4 Arithmetic Unit
4.5 Schematic diagram for the A-Logic
4.6 The output waveform of A-Logic unit
4.7 Schematic diagram for B-Logic Unit
4.8 Output waveform for B-Logic Macro
4.9 The Schematic diagram of full adder
4.10 The output waveform for full adder
4.11 Block diagram for arithmetic unit
4.12 Output waveform for the Arithmetic Unit
4.13 Schematic diagram for 2:1 M U X
4.14 Output simulation o f 2 : l M U X
4.15 Schematic diagram of 1 -bit A L U
4.16 Output waveform for arithmetic operation 40
4.17 Output waveform for logic operation 40
4.18 Schematic diagram for 8-bit A L U 41
4.19 The output simulation for 8-bit A L U 42
4.20 The Parent level of structural V H D L code 43
4.21 Functional Simulation for M = 0 (logical operation) 45
4.22 Functional Simulation for M = 1 (arithmetic operation) 46
5.1 The Schematic diagram for the whole system of 48 8- bit A L U
5.2 The results of 8-bit A L U in the logical function 49
5.3 The result of the 8-bit A L U in the arithmetic operation 50
xiii
LIST OF TABLES
TABLE NO. TITLE P A G E
4.1 Function of A L U 30
5.1 The timing results for S-bit A L U 51
5.2 Device Summary for 8-bit A L U 52
(schematic implementation)
5.3 Device Summary for 8-bit A L U 53
( structural description of V H D L )
5.4 De\ 'ice Summary for 8-bit A L U 53
(behavioral description of V H D L )
xiv
LIST OF ABBREVIATION
Altera Hardware Description Language
Arithmetic Logic Unit
Computer Aided Design
Complex Programmable Logic Device
Central Processing Unit
Digital Signal Processing
Embedded Array Block
Electrically Erasable Programmable Read Only Memory
Erasable Programmable Read Only Memory
First In First Out
Field Programmable Gate Array
Hardware Description Language
Input/Output
Input Output Element
Intellectual Property
logic Element
Light Emitting Diode
Look Up Table
Multiplexer
Personal Computer
Printed Circuit Board
ProgrammableLogic Array
Programmable Logic Device
Random Access Memory
ROM
SRAM
UPI
VHDL
VHSIC
Read Only Memory
Static Random Access Memory
University Programmer I
VHSIC Hardware Description Language
Very High Speed Integrated Chip
xv
xvii
LIST OF APPENDIX
APPENDIX TITTLE PAGE
A VHDL CODES 59
B TRUTH TABLES 6 4
C UP EDUCATION BOARD DESCRIPTION 66
CHAPTER I
INTRODUCTION
1.1 Overview
Field Programmable Gate Arrays (FPGAs) is one type oflogic chip that can be
programmed and its internal functional operation is defined by the user. An FPGA
supports a more flexible block structure and through more flexible interconnects as the
routing resources. The number of gates and features has increased dramatically to
compete with capabilities that have traditionally only been offered through ASIC devices.
The applications of FPGA have led to higher density devices, intellectual property (IP)
integration, and high-speed VO interconnects technology. All of these elements have
allowed FPGAs to playa central role in digital systems implementations.
Current FPGA architectures are heterogeneous, containing thousands oflogic
elements and hundreds of embedded multipliers and memory units.( K. J. Alex, H.
Raymond, S. K. Ivan, F. Joshua, D.K, J. Foster, S. B., and A. Muaydh, 2004). Internally,
FPGA typically contain multiple copies of a basic programmable logic element (LE) or
cell. Logic elements are arranged in a column or matrix on the chip. To perform more
complex operations, logic elements can automatically connected to other logic elements
on the chip using a programmable interconnection network. The basic methodology for
FPGA design consists of three inter- related steps: entry, implementation, and verification
(W.S. Cater, 1994) as shown on Figure 1.1.
I Design Entry
SchGmatic Entry Text-basGd Entry
FPGA
Functional Simuhrtion
I 'I llmlng Simulation (Back-annotation)
.1 Design 1 1 Implementation I
Partition, Place & Route
Partition, Map & Interconnect
Design
1 Verification
Simulation In.orcult Verification
EPLD
Figure 1.1: The basic FPGA design methodology consists of three steps:
entry, implementation, and verification.
1.2 Project Aim
The project aim was to analyze the methods that are being used to design FPGA
based hardware which provide a flexibility for the implementation.
1.3 Objective
The objectives of the project are:
2
(a) To design an 8-bit ALU using the ALTERA MAX+PLUS II Software and
implement the hardware onto the UP2 board.
(b) Use a schematic and VHSIC Hardware Description Language (VHDL) for
design entry.
(c) To analyze the methods that are used to design the 8-bit ALU in terms of
the flexibility, area consumed and timing analysis.
3
1.4 Scope Of The Project
The scope of the project covers the study of the architecture, the FPGA design
methodology and the targeted chip, FLEX10K70. The FLEX10K70 chip was used, since
it is the by far the larger chip and is packaged with many more in/out pins available. The
Altera's Max+PLUS II Version 10.1 software is used to draw the schematic diagram and
write VHDL code for the design of 8-bit ALU. The design is then downloaded to the chip
and the outputs are displayed on the 7 segment display. The inputs are controlled by the
switches. The methods that are used to design the 8-bit ALU are analyzed in terms of the
flexibility, area consumed and timing analysis.