Download - FPGA Camp - Intellitech Presentation
Build It or Buy It Build It or Buy It --Engineers may be missing what Engineers may be missing what g y gg y g
their company actually wantstheir company actually wantsPrepared for FPGA CampPrepared for FPGA Camp
By CJ ClarkCEO, Intellitech Corp., p
Ramachandra GambheerManaging Director
Intellitech India Private Ltd.
BangaloreBangaloreMay 21, 2010
Intellitech Corp.Intellitech Corp.
2Copyright © Intellitech Corporation 2010 All rights reserved.
Old methods won’t win customersOld methods won’t win customers
High-Level Tools show in-system logic levels (“H” and “L” for driving, “0” and
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“1” for receiving)
Manage delivery Manage delivery –– don’t riskdon’t risk
DDR1/2/3 8 Pair @ 3.125Gb/SDDR Interface @ 200-535Mhz
OptionalAt-speed
MEMBIST IP
8 Pair @ 6.5Gb/SAt-speed Bit Error Rate
BER design downloaded at time-of-test
BERT-IP TX BERT-IP TXBERT-IP RX
MEMBIST-IP
BERT-IP TX BERT-IP RXBERT-IP RX
S Clk S ClkSys FPGAFPGAFPGA SysClk SysClk
JTAG/1149.1
SysClk
Quick how fast can you deliver a full at speed
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Quick, how fast can you deliver a full at-speedSERDES Test with at-speed DDR and guarantee success?
PrePre--engineered Software makes the differenceengineered Software makes the differencePrePre--engineered Software makes the differenceengineered Software makes the difference
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DesignDesign
V l PCB T tV l PCB T t
Proto DebugProto Debug
ESS/HASSESS/HASS
Vol. PCB TestVol. PCB Test
FunctionalFunctional
Field TestField Test
RepairRepair
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SystemBIST – Pre-built FPGA EcosystemsSystemBIST – Pre-built FPGA Ecosystems
CPU orFPGA
MezzanineJTAG
FPGAw/CPU
XilinxAltera
T O
CPLD
SPI
RE
SET
WD
I
WD
O
XilinxAltera8 bitASH
GPIO/I2C
FLA
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DC/DC DC/DCGPIO/I2CJTAG (in)
Structural test & Standards based Software simplifies tasksStructural test & Standards based Software simplifies tasks
Engineers not familiar with the entire system can create complex strategies for FPGA Engineers not familiar with the entire system can create complex strategies for FPGA configuration, security, anticonfiguration, security, anti--cloning, watchdogs, resets and Builtcloning, watchdogs, resets and Built--inin--Test outside the Test outside the critical path of Mission mode software developmentcritical path of Mission mode software development
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critical path of Mission mode software developmentcritical path of Mission mode software development
Tool downloads PCB specific Tests to ICTool downloads PCB specific Tests to IC
AARCHIIVE
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Move out of embedded software timelinesMove out of embedded software timelines
•Reduces in-house software costs•Mission Software lightly coupled to • reusable FPGA/BIT method through SPI
IN
S g•Less time/cost/skill with Automation Tools•Re-usable Security/Update/Config/BIT method
-HOU
SPEC
• 3rd party outsource-able• Requires only GUI expertise
USE
IAL
+
SYS
IST
GUITEM
GUISpecialist
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All Software Approach
Software + SystemBIST Approach
Pin Level Diagnostics in the field or repair depotPin Level Diagnostics in the field or repair depot
FLASHFLASH InternetInternetPHYPHY
IntellitechWebsitew/ SystemBISTArchive
IntellitechWebsitew/ SystemBISTArchive
Failure map
CPUCPUSPI JTAGDiagnostic
Results
Return to UUT, Email, other
11Copyright © Intellitech Corporation 2010 All rights reserved.
FPGA Configuration
CEO of Intellitech Corporation since 1988 University of New Hampshire College of Engineering and Ph sical Science (CEPS)Engineering and Physical Science (CEPS) Advisory Board (2000 to present)UNH Department of Electrical Engineering IA Board (2000 to present)Chair IEEE 1149.1 JTAG working group from 1996 to present and 2010 editorand 2010 editorActive in IEEE 1149.4, 1149.6, 1532, 1500, 1149.7, P1581 and P1687. He is co inventor on four US patents and over 30 othersHe is co-inventor on four US patents and over 30 othersHe has presented at the USPTO examiner education series, IEEE Lecture series, ITC, BTW, VTS, HOST and DATE.His first job in test was in 1978 with Plantronics/Wilcom.
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Thank You