CBA Program Review – October 2006
From
Paintable Computingto
Scale-free Architectures
Bill Butera
Digital Enterprise Group
Intel Corporation
CBA Program Review – October 20062
Paint Research, DARPA, DTO first HW
Concept
Simulation
‘COTS’ HW
SWProof-of-concept
CBA Program Review – October 20063
Reliability – new challenges at extreme of device shrinkage
Soft Error FIT/Chip (Logic & Mem)
0
50
100
150R
ela
tiv
e
~8% degradation/bit/generation
Time dependent device degradation
0
1
1 2 3 4 5 6 7 8 9 10
Time
Ion
Re
lati
ve
Burn-in may phase out…?
1
10
100
1000
10000
180 90 45 22
Jo
x (
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)
Hi-K?
Extreme device variations
0
50
100
100 120 140 160 180 200
Vt(mV)
Re
lati
ve
Wider
Source: Shekhar Borkar- Intel CTG
CBA Program Review – October 20064
Scale-free ArchitecturesSW techniques for reliable computation on meshes of unreliable HW nodes
High value “statistical workloads” running reliably on meshes of unreliable cores (nodes)
HW meshes whose performance scale smoothly with size -- over multiple orders of magnitude(1K nodes upward)
“Write once”, scale-agnostic application code
Excessive defect tolerance, smooth response to soft error.
Shortened HW design cycle, minimum form factor, faster yield ramps.
Server (50K)
Desktop (20K)
Cell phone (1K)
UMPC (2K)
Farm (300K nodes)
All platforms with the same short design cycle
CBA Program Review – October 20065
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