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Future Works in LLVM Register Allocation
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Talk Overview
1. Introduction
2. Upcoming Changes
3. PBQP
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
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PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Lower PHI-instructions to copies
Register Allocation in LLVM
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PHI Lowering
BB1: %x1 = .
BB3:%x3 = phi [%x1, BB1], [%x2, BB2]
BB2: %x2 = .
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PHI Lowering
BB1: %x1 = .
BB3:%x3 = %xP
BB2: %x2 = .
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PHI Lowering
BB1: %x1 = . %xP = %x1
BB3:%x3 = %xP
BB2: %x2 = . %xP = %x2
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PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Lower PHI-instructions to copies
Register Allocation in LLVM
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PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Register Allocation in LLVM
Lower Three-Address Instructions
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Two-Address Instructions
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Two-Address Instructions
x3 = x2 + x1
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Two-Address Instructions
x3 = x2 + x1
x3 = x2x3 += x1
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PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Register Allocation in LLVM
Lower three-address instructions
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Construct live intervals
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Live Intervals
BB:%x1 = ...
.
.
.%x2 = %x1
.
.
. ... = %x2
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Live Intervals
BB:%x1 = ...
.
.
.%x2 = %x1
.
.
. ... = %x2
%x1
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Live Intervals
BB:%x1 = ...
.
.
.%x2 = %x1
.
.
. ... = %x2
%x1 %x2
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Construct Live Intervals
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Aggressively eliminate copies
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BB:%x1 = ...
.
.
.%x2 = %x1
.
.
. ... = %x2
Coalescing
%x1 %x2
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BB:%x1 = ...
.
.
.
.
.
. ... = %x1
Coalescing
%x1
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Aggressively eliminate copies
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Compute register assignment
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
Apply register assignment
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Register Allocation in LLVM
PHI Elimination Two-Address
Coalescing Allocator
Liveness
Rewriter
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Improvements
• New and better optimizations
• New allocators
• Cleaner infrastructure
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1. Optimizations
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Rematerialization
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. // stuff
... =
. // more stuff
... =
<expr>
vr1
vr1
vr1
Rematerialization
=
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. // stuff
... =
. // more stuff
... =
<expr>
vr1
vr1
vr1
Rematerialization
=
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. // stuff
... =
. // more stuff
... =
<expr>
vr1
vr1
vr1
[M]
[M]
[M]
Rematerialization
=
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. // stuff
... =
. // more stuff
... =
<expr>
vr1
vr1
vr1
Rematerialization
=
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. // stuff
... =
. // more stuff
... =
<expr>
<expr>
Rematerialization
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Splitting
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Splitting
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Splitting
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Splitting
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Splitting
Spill
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Spills introducedin to other loops
Splitting
Spill
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Splitting
Register
Spill
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2. New Allocators
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New Allocators
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New Allocators
• “Linear Scan” is not, in fact, linear
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New Allocators
• “Linear Scan” is not, in fact, linear
• We want something faster
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New Allocators
• “Linear Scan” is not, in fact, linear
• We want something faster
• Priority coloring?
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New Allocators
• “Linear Scan” is not, in fact, linear
• We want something faster
• Priority coloring?
• Linear Scan?
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New Allocators
• “Linear Scan” is not, in fact, linear
• We want something faster
• Priority coloring?
• Linear Scan?
• Need to tidy the infrastructure
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3. Cleaner Infrastructure
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Currently...
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Currently...
Liveness Analysis
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Currently...
Liveness Analysis Allocator
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Currently...
Liveness Analysis Allocator
VirtualRegister Map
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Currently...
Liveness Analysis Allocator
VirtualRegister Map
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Currently...
Liveness Analysis Allocator
VirtualRegister Map
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Currently...
Liveness Analysis Allocator
VirtualRegister Map
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Currently...
Liveness Analysis Allocator Rewriter
VirtualRegister Map
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Rewrite In Place
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Rewrite In Place
Liveness Analysis
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Rewrite In Place
Liveness Analysis
Live Intervals
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Rewrite In Place
Liveness Analysis Allocator
Live Intervals
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Rewrite In Place
Liveness Analysis Allocator
Live Intervals
Modify code in-place
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Rewrite In Place
Liveness Analysis Allocator
Live Intervals
Modify code in-place
Live intervalskept up-to-date
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Rewrite In Place
Liveness Analysis Allocator
Live IntervalsLive intervals remain valid post-alloc
Modify code in-place
Live intervalskept up-to-date
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Improvements
• New and better optimizations
• New allocators
• Cleaner infrastructure
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Upcoming Changes
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Upcoming Changes
• Live index renumbering
• Improved splitting
• Better def/kill tracking for values
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Live Indexes
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BB: . . %x2 = %x1 add %x3, %x2 . .
Live Indexes
33
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BB: . . %x2 = %x1 add %x3, %x2 . .
Live Indexes
123456
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%x3 = ...
BB: . . %x2 = %x1
add %x3, %x2 . .
Live Indexes
123
456
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%x3 = ...
BB: . . %x2 = %x1
add %x3, %x2 . .
Live Indexes
123
456
?
33
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BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .
Live Indexes
P1P2P3
P4P5P6
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BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .
Live Indexes
P1P2P3
P4P5P6
P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P634
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BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .
Live Indexes
P1P2P3
P4P5P6
P7
P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P634
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BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .
Live Indexes
P1P2P3
P4P5P6
P7
P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P6P7 ≺34
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Live Indexes
• unsigned ➙ LiveIndex
• Index Renumbering
✓⌚
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Improved Splitting
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Improved Splitting
• Break multi-value intervals into component values.
36
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Improved Splitting
• Break multi-value intervals into component values.
• Each value gets a 2nd chance at allocation.
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Improved Splitting
• Break multi-value intervals into component values.
• Each value gets a 2nd chance at allocation.
• ... but not a 3rd.
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Improved Splitting
• Break multi-value intervals into component values.
• Each value gets a 2nd chance at allocation.
• ... but not a 3rd.
• 13% reduction in static memory references on test case (a pathological SSE kernel).
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Better Def/Kill Tracking
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Better Def/Kill Tracking
• Defined by a PHI - Track the def block.
For Values
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Better Def/Kill Tracking
• Defined by a PHI - Track the def block.
• Killed by a PHI - Track the appropriate predecessor.
For Values
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Future Work
• Better value def/kill tracking
• LiveIndex renumbering
• Improved splitting
• Rewrite-in-place
• New allocators
✓
⌚⌚⌚⌚
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PBQP
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PBQP
• Discrete optimization problems
• NP-complete
• Subclass solvable in linear time
Partitioned Boolean Quadratic Problems
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Irregular Architectures
• Multiple register classes.
• Register aliasing.
• Register pairing.
• ...
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PBQP Example
42
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PBQP Example
ZX
Y
42
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PBQP Example
901
436
702
ZX
Y
42
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PBQP Example
901
436
702
ZX
Y
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
Y
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
Y
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
Y
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
Y
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
Y
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17
Total: 32
Solution [3,2,1]:
42
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PBQP Example
901
436
702
3 8 18 5 35 2 7
5 2 26 7 31 4 8
1 9 34 5 39 7 6
ZX
YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17
Total: 32
Solution [3,2,1]:
Solution [1,2,3]: 19
42
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PBQP Example
900
400
700
0 0 00 ∞ 00 0 ∞
0 0 00 ∞ 00 0 ∞
0 0 00 ∞ 00 0 ∞
ZX
Y
Nodes represent virtual registers.
Options reflect storage locations.
Option costs:
Typically zero cost for registers,spill cost estimate for stack slot.
Edge costs:
Depends on the constraint.
For Register Allocation:
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Example 1
X Y
Interference on a Regular Architecture
44
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Example 1
400
X Y
Interference on a Regular Architecture
Sp
r0
r1
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Example 1
400
700
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
44
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Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
44
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Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
44
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Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (Sp, Sp) = 1144
![Page 112: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/112.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, Sp) = 745
![Page 113: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/113.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (Sp, r0) = 446
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Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r1) = 047
![Page 115: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/115.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r1) = 0 ✓47
![Page 116: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/116.jpg)
0 0 00 ∞ 00 0 ∞
Example 1
400
700
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r1) = 0 ✓48
![Page 117: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/117.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r1) = 0 ✓49
![Page 118: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/118.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r0) = ∞50
![Page 119: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/119.jpg)
Example 1
400
700
0 0 00 ∞ 00 0 ∞
X Y
Interference on a Regular Architecture
Sp
r0
r1
Sp
r0
r1
Cost (r0, r0) = ✗∞50
![Page 120: Future Works in LLVM Register AllocationFuture Work •Better value def/kill tracking ... Register Pairing (R i, R i+1) Sp s0 s1 Sp s0 s1 s2 s3 s2 0 0 0 0 0 0 ∞ 0 ∞ ∞](https://reader034.vdocuments.net/reader034/viewer/2022050414/5f8b1a9640128052657e0e6a/html5/thumbnails/120.jpg)
Example 1
0 0 00 ∞ 00 0 ∞
Interference on a Regular Architecture
50
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Example 2
0 0 0 0 00 ∞ ∞ 0 00 0 0 ∞ 0
Interference on an Irregular Architecture
Sp
AX
BX
Sp AL AH BL CL
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Example 3
0 0 00 -c 00 0 -c
Coalescing
Sp
AX
BX
Sp AX BX
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Example 4
Register Pairing (Ri, Ri+1)
Sp
s0
s1
Sp s0 s1 s2 s3
s2
0 0 0 0 00 ∞ 0 ∞ ∞0 ∞ ∞ 0 ∞0 ∞ ∞ ∞ 0
53
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The PBQP Allocator
solution = solve pbqpsolution -> allocation
regalloc -> pbqp
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The PBQP Allocator
solution = solve pbqpsolution -> allocation
regalloc -> pbqp
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The PBQP Allocator
solution = solve pbqpsolution -> allocation
regalloc -> pbqp
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The PBQP Allocator
llvm/lib/CodeGen/RegAllocPBQP.cpp
solution = solve pbqpsolution -> allocation
regalloc -> pbqp
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How does it work?
Solver uses a graph reduction algorithm.
Reduce problem to the empty graph with reduction rules, then reconstruct it.
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PBQP
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PBQP
PROS CONS
• Ideal for Irregularity
• Very Simple
• Reasonable quality
• Slooooooow
56
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PBQP
PROS CONS
• Ideal for Irregularity
• Very Simple
• Reasonable quality
• Slooooooow
56
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PBQP
PROS CONS
• Ideal for Irregularity
• Very Simple
• Reasonable quality
• Slooooooow
• Perfect opportunity
for a coffee
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• Improved Optimizations.
• New Allocators.
• Cleaner Architecture.
• PBQP.
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the end.
58