© CoWare, Inc. 1997-2002
Generating TLM Bus Models from FormalGenerating TLM Bus Models from FormalProtocol SpecificationProtocol Specification
Tom Tom MichielsMichielsCoWareCoWare
© CoWare, Inc. 1997-2002
AgendaAgenda
•• Cycle accurate TLMCycle accurate TLM•• RequirementsRequirements•• Difficulties in creating TLM bus modelsDifficulties in creating TLM bus models•• Generating from formal specificationGenerating from formal specification•• Example & ResultsExample & Results
© CoWare, Inc. 1997-2002
Transaction Level Modeling: What Is It?Transaction Level Modeling: What Is It?A Higher Level Of Abstraction For CommunicationA Higher Level Of Abstraction For Communication
•• RTL:RTL:−− Each device on the bus has aEach device on the bus has a
pin-accurate interfacepin-accurate interface−− Each device interface mustEach device interface must
implement the bus protocolimplement the bus protocol
BUS
MEM RISC
Periph Req
GrntSel
DataAddr
Clk
BUS
MEM RISC
Periph
TLM API TLM API
TLM APITransaction HREQ
HADDR
HGRANT
HWDATA
HRESP
HREADY
ReqTrfGrant
Trf
AddrTrf
WriteDataTrf
EotTrf
•• TLM:TLM:−− Allow easy modeling, easyAllow easy modeling, easy
assemblyassembly−− Each device communicates viaEach device communicates via
transaction level APItransaction level API−− Less code, fewer pins, fewerLess code, fewer pins, fewer
events => much fasterevents => much faster
© CoWare, Inc. 1997-2002
TLM Requirements: Use Model POVTLM Requirements: Use Model POV
•• System Architectural ExplorationSystem Architectural Exploration−− Allow cycle accuracy modelingAllow cycle accuracy modeling
•• Analysis and Verification (System-Level)Analysis and Verification (System-Level)−− Verify that the assembled system does what is expectedVerify that the assembled system does what is expected−− Verify architectural decisionsVerify architectural decisions−− Allow cycle accurate mixed abstraction simulationsAllow cycle accurate mixed abstraction simulations−− Fast simulationFast simulation
•• Design and Easy ModelingDesign and Easy Modeling−− API should allow implementation flowAPI should allow implementation flow−− Do not encode timing in both peripherals and busDo not encode timing in both peripherals and bus−− Minimize modeling artifacts exposure (like transaction memoryMinimize modeling artifacts exposure (like transaction memory
management)management)
© CoWare, Inc. 1997-2002
TLM Requirements: Model POVTLM Requirements: Model POV
•• Fast simulation (100kc/s)Fast simulation (100kc/s)•• API that allows modeling without encodingAPI that allows modeling without encoding
−− pollingpolling−− event sensitivityevent sensitivity
•• Bus model should not depend on peripherals for correctBus model should not depend on peripherals for correcttiming.timing.
•• Bus model should allow accurate mixed abstractionBus model should allow accurate mixed abstractionsimulation RTL & TLM.simulation RTL & TLM.
© CoWare, Inc. 1997-2002
What Makes it Hard: Mixed Abstraction Level SimulationWhat Makes it Hard: Mixed Abstraction Level Simulation
Req
GrntSel
DataAddr
Clk
MEM RISC
BUS
Periph
TLM APITransaction
Problems with RTL to TLM converterProblems with RTL to TLM converter
Periph
TLM
API
Converter?
A
B
•• Wait for last delta cycle?Wait for last delta cycle?•• TLM even/function call earlyTLM even/function call early
enough to start driving signals?enough to start driving signals?
Functions &eventssignals
BUS
© CoWare, Inc. 1997-2002
What Makes it Hard: BusWhat Makes it Hard: Bus InterconnectivityInterconnectivity
BUS
MEM1 RISC
Periph1
TLM API TLM API
TLM API
Peripheral BUS
Periph3
TLM API
Periph2
TLM API
BRIDGE
SI SIOS OS
DMA
TLM API TLM API
Periph4
TLM API
MEM2
TLM API
Matrix
•• Combinatorial paths through bus topologies can be difficult toCombinatorial paths through bus topologies can be difficult toimplement. E.g. no full clock cycle available to do arbitration.implement. E.g. no full clock cycle available to do arbitration.
© CoWare, Inc. 1997-2002
What Makes it Hard: Bus Knows Protocol TimingWhat Makes it Hard: Bus Knows Protocol Timing
AddrTrf ReqTrf
GrantTrf
WriteDataTrf
ReadDataTrf
Attributes
Transfers
Initiator
Initiator is allowed tosend a Write Datatransfer during this
time slot
Peripherals can interact with the bus through events andthrough polling.
WriteDataTrf
Target
The bus synchronizes the transfers with thetarget according to the timing of the protocol
Bus
© CoWare, Inc. 1997-2002
Bus model
Creating a Bus model at TLM by handCreating a Bus model at TLM by hand
Req
GrntSel
DataAddr
Clk
Bus specification1 Timing diagram
Cycle accurate TLM
High Level TLM
• Long and complex development phase
• Hard to keep a good speed/accuracy trade-off
• All Validation of model in simulation
• Accuracy allows study of critical part of asystem (bottleneck)
SystemC and C++Expertise needed
Bus model
A TLM user always has to build and maintain a complex modelinginfrastructure in order create several bus models, TLM API, TLM IPs.
• Short and simple development phase
• High speed but low accuracy
• Co-simulation with RTL requires longdevelopment of complex adatper.Sometimes the adapter cannot even becreated.
© CoWare, Inc. 1997-2002
Creating a Bus Model at TLM from Protocol SpecificationCreating a Bus Model at TLM from Protocol Specification
Req
GrntSel
DataAddr
Clk
Bus specification1 Timing diagram
Bus model
Tool takes care off:Tool takes care off:•• Fast simulationFast simulation•• RTL RTL cosim cosim interfacinginterfacing•• Computational kernel of busComputational kernel of bus
User takes care of :User takes care of :•• TimingTiming•• Protocol.Protocol.
© CoWare, Inc. 1997-2002
Example Bus Protocol SpecificationExample Bus Protocol SpecificationAPB timing (1)APB timing (1)include "genprot.bci";
node APB protocol = GPTransaction, bus = { variable setupRead, type = bool, compute = (addrTrf.sent & addrTrf.type == readAtAddress);
variable setupWrite, type = bool, compute = (addrTrf.sent & addrTrf.type == writeAtAddress);
variable setup, type = bool, compute = setupRead | setupWrite; variable enableRead, type = bool, compute = delay (setupRead); variable enableWrite, type = bool, compute = delay (setupWrite); variable enable, type = bool, compute = enableRead | enableWrite;
© CoWare, Inc. 1997-2002
Example Bus Protocol SpecificationExample Bus Protocol SpecificationAPB timing (2)APB timing (2)
input interNodeSetupRead, type = bool; input interNodeSetupWrite, type = bool;
variable canSendInterNodeSetupRead, type = bool, compute = !enable && !interNodeSetupWrite && !addrTrf->sent; variable canSendInterNodeSetupWrite, type = bool, compute = !enable && !interNodeSetupRead && !addrTrf->sent;
use addrTrf, configurators = {
sendTra = grantedTra,receiveTra = grantedTra,
slaveDrive = setup | enable,masterDrive = setup | enable,canSend = !enable,
CanReceive = delay (setup) };
© CoWare, Inc. 1997-2002
Example Bus Protocol SpecificationExample Bus Protocol SpecificationAPB timing (3)APB timing (3) use writeDataTrf, configurators = {
sendTra = grantedTra,receiveTra = grantedTra,
slaveDrive = setupWrite | enableWrite,masterDrive = setupWrite | enableWrite,canSend = setupWrite,
canReceive = delay (setupWrite) };
use eotTrf, configurators = {
sendTra = grantedTra,receiveTra = grantedTra,
slaveDrive = enable,masterDrive = enable,canSend = enable,
canReceive = delay (enable) };
© CoWare, Inc. 1997-2002
Example Bus Protocol SpecificationExample Bus Protocol SpecificationAPB timing (4)APB timing (4)
use ReadDataTrf, configurators = {
sendTra = grantedTra,receiveTra = grantedTra,
slaveDrive = enableRead,masterDrive = enableRead,canSend = enableRead,
canReceive = delay (enableRead) };
decoder MyDecder, sensitivity = addrTrf.sent, };
© CoWare, Inc. 1997-2002
ResultsResults
•• Modeled cycle accurate TLM bus models for AMBAModeled cycle accurate TLM bus models for AMBA•• Modeled cycle accurate TLM bus models for proprietaryModeled cycle accurate TLM bus models for proprietary NoC NoC
busses for CoWare customersbusses for CoWare customers−− Buffers andBuffers and Fifo’s Fifo’s−− SwitchesSwitches−− Split bussesSplit busses−− Busses programmable through control portsBusses programmable through control ports