Download - GRID November 2013 GRID · November 2013 Visit us at Page 1 GRID.pdf SCV-Nano - 11/9 | SCV-ComSoc - 11/13 | erization and Thermal Mapping November 2013 CHAPTER MEETINGS

November 2013 V is i t us a t www .e-gr id .net

GRID.pdf

November 2013

CHAPTER MEETINGS SCV-PACE - 10/29 | Emerging Technologies for 3GPP LTE and LTE-Advanced - user experience, downlink/uplink, MIMO ... [more]

SCV-GOLD - 11/4 | Volunteer Information Evening - Second Harvest Foodbank, Science Fairs, more ... [more]

SCV-Life - 11/4 | The History of Robots - ancient Egypt, hazardous environments, assembly systems, medical, fiction ... [more]

SCV-CNSV - 11/5 | Lift Labs: Defeating Human Tremors - Parkinson's, stabilizing, cancellation, SBIR startup ... [more]

SCV-Phot - 11/5 | Optical and Electronic Approaches to Restoration of Sight to the Blind - stimulation, opto-genetics, challenges ... [more]

SCV-PACE - 11/5 | 3D Heterogeneous Microsystem Integration for Biomedical Applications - communications, power, modeling ... [more]

SPECTRUM - 11/7 | Wireless Power Transfer and Microwave Energy Harvesting - Webinar: short/mid-range, RF energy ... [more]

SCV-TMC - 11/7 | Building an Organization that Fosters Creativity and Innovation -risk taking, thinking differently, examples ... [more]

SCV-WiE - 11/7 | Mobile UX (User Experience) Prototypes - customer view, framework, tools, prototyping ... [more]

SCV-Rel - 11/7 | Thermoreflectance Technique for Thermal Charact-erization and Thermal Mapping - solutions, nanoscale, demos .. [more]

SCV-Nano - 11/9 | Energy Generation & Storage: Possibilities and Realities - half-day: materials, thin film, nano-batteries ... [more]

OEB-Mag - 11/11 | A New Type of Domain Wall in Ultrathin Films: The Dzyaloshinskii Domain Wall - tilt, spin Hall effect ... [more]

SCV-CS - 11/12 | Drinking from the Firehose: Run-ahead Transfer Prediction in the Mill CPU Architecture - code, latency, stall ... [more]

SCV-CPMT - 11/13 | Design, Manufacturing and Performance of a 3D Random Access Memory Subsystem - TSVs, test, yield ... [more]

SCV-ComSoc - 11/13 | Sensor Networks in Civic Infrastructure Applications - Panel: mesh, smart cities, distributed, services ... [more]

SPECTRUM - 11/14 | EMC Simulation in the Design Flow of Modern Electronics - pitfalls, mistakes, countermeasures, simulation ... [more]

SCV-MTT - 11/14 | Gigahertz Common-mode Filter for 10-Gbit/s Differential Signaling - band gap, noise, compact-size ... [more]

SCV-CAS - 11/18 | Sign-based Zero-Forcing Adaptive Equalizer Control for High-Speed I/O - mixed-signal, filter patterns ... [more]

SCV-Nano - 11/19 | Fall Symposium: Nanoengineered Biomedical Devices - 8 speakers: microfluidics, sensors, probes ... [more]

SCV-EDS - 11/19 | Eastern Europe's Semiconductor Technology - Recollections and Projections - stability, products, directions ... [more]

SCV-Mag - 11/19 | Tuning Magnetic Anisotropy in (001)-Oriented L10 (Fe1-xCux)55Pt45 Films - stability, nanoelements, cond'ns ... [more]

SF-IAS - 11/19 | Remote Ground Fault Protection Issues - wind power, damage, consequences, methods ... [more]

Continued -- next page ====>>

GRID.pdf

Santa Clara University Grad School of Engineering Winter Open University [more]- Early-morning, evening, Saturday classes

Chapter Seminars and Workshops

Design Optimization of Robust and Quiet Electric Machines – 1-day, November 7, Santa Clara [more]

Energy Generation & Storage: Possibilities and Realities – Saturday, November 9, Stanford [more]

Nanoengineered Biomedical Devices - 1-day, Tuesday, November 19, Santa Clara [more]

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CONFERENCE CALENDAR

Oct 29: IEEE Rock Stars of Big Data - Computer History Museum, Mtn View [more]

Oct 29 - 31: ARM TechCon Conference and Expo - Santa Clara Convention Center [more] Nov 11-13: IEEE Conference on Cloud Networking (CloudNet) - Hilton Hotel, S.F. [more] Nov 12-15: Android Developer Conference (AnDevCon) - Hyatt Regency, Burlingame [more]

Nov 19-22: Printed Electronics USA Conference - Santa Clara Convention Center [more]

Dec 11-13: 3-D Architectures for Semiconductor Inte-gration and Packaging - Hyatt, Burlingame [more]

Jan 28-31: DesignCon 2014 - Santa Clara Convention Center [more] Calls for Papers: IEEE Int'l Reliability Physics Symposium (IRPS) - June 1-4, 2014 - Waikoloa, HI [more] - Abstracts due December 1st

http://www.irps.org/

http://www.computer.org/Big-Data

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November 2013 V is i t us a t w w w . e - G R I D . n e t

Your Networking Partner ®

November 2013 • Volume 60 • Number 11

IEEE-SFBAC ©2013

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs.

IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 30,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

Getting to Know the Movers and Shakers

It is said that networking is a key skill for the modern engineer -- getting to know a broad range of people who can potentially be your advocate, your coach, or your introduction to key people. One really great way to put yourself before a broad range of professionals in your field is to volunteer as a Chapter officer for a few years. People will get to know you better, and your name will be more broadly known around the Valley among your peers. They may come to you for help -- and in return, you can count on them, when needed.

Your Chapter is currently looking for "the few, the proud", who can commit to lending a hand during 2014. Respond, when asked to be an officer or helper. In fact, don't wait to be asked -- go to your Chapter's website, look up the Chair, and send an email! You'll be glad you did.

Best regards,

Paul Wesling, Editor

Select a Chapter event to learn about new developments and to network with fellow professionals -- choose a course

or conference to master new skills.

Stay ahead of changing professional demands;

sharpen your competitive edge with up-to-date technical skills and through your networking activities. Technology to your INBOX, twice a month.

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information.

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Santa Clara Valley

Ed Aoki

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Oakland East Bay

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San Francisco

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OFFICERS Chair: Ed Aoki

Secretary: Bill DeHope Treasurer: Shirin Tabatabai

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRIDCHAPTER MEETINGS (continued)

SCV-EMB - 11/20 | Special Design Considerations for Medical Electronics - compliance, electronics, SW ... [more] OEB-Life - 11/20 | Molten Salt and Thorium Nuclear Power (MSR) - heat, power, no fuel emissions, tested ... [more]

OEB-PES+IAS - 11/21 | Ground Fault Current Protection of a 480Y/277V Power System - solar power, green energy, inverters, bus rating, cables ... [more]

SCV-RAS - 11/21 | Time-delayed Teleoperation of Robots in Space for Satellite Repair - compensation, visual and haptic feedback, prediction algorithm ... [more]

SCV-CE - 12/3 | State of the Gaming Industry - Technology & Trends - consoles, mobile, casual, accessories ... [more]

SCV-CNSV - 12/3 | Trends in Mobile Processors - SoC, multicore, architectures, 64-bit ... [more]


Patent Agent Jay Chesavage, PE

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Consulting Skills for Engineers: How to Become a Trusted Advisor

– Date/Time: Thursday, Nov 7, 9 AM – 5 PM – Location: – Tibco, Palo Alto – Fee: $425 for IEEE Members; $525 non-members

“This class will tremendously impact your productivity and career development.”

Delegation and Coaching: The Winning Combination

– Date/Time: Wednesday, Nov 13, 9 AM – 5 PM – Location: – Tibco, Palo Alto – Fee: $425 for IEEE Members; $525 non-members

"The Delegation and Planning; and Documenting Feedback for Performance sections of the course were invaluable." ThermoFisher Scientfic, MarCom Director

Thriving in a Changing Environment – Date/Time: Tuesday, Nov 19, 9 AM – 5 PM – Location: – Tibco, Palo Alto – Fee: $425 for IEEE Members; $525 non-members

Upgrade your skill set – prepare for future challenges

November 19-22, 2013 Santa Clara Convention Center

The tenth annual Printed Electronics USA conference and exhibition covers all the applications, technologies and opportunities.

Printed Electronics USA gives the big picture, with speakers from around the world from a range of industries including consumer goods, healthcare, military, electronics, advertising, publishing and others. Commercialization and the full range of technologies are the emphasis, from interactive packaging to sensing fabrics and ultra low cost wireless identification tags.

OLEDs USA is the premier event covering all aspects of the technology, covering the market opportunities, challenges and technical progress from around the world.

Graphene LIVE! covers all promising applications of graphene, including graphene composites, batteries and supercapacitors, functional inks, logic and memory, touch screens, sensors and bio-electronics and beyond.

3D Printing LIVE! Gain a comprehensive understanding of the state-of-the-art in 3D Printing, across a range of application areas and the latest

technological advances.

SCV Chapters, Technology Management & Components, Packaging and Manufacturing Technology Societies

Transitioning from Individual Contributor to Manager

– Date/Time: Tuesday, Dec 10, 9:00AM-5:00PM – Location: Brocade, San Jose – Fee: $425 for IEEE Members; $525 non-members

"The class exceeded my expectations; it helped me understand my role and how my own skill set affects the way I lead. This course was very worthwhile."

Managing Time & Multiple Priorities – Self-Paced – Fee: $250

For complete course information, schedule, and registration form, see our website:

www.EffectiveTraining.com*

The Application of Printed, Organic & Flexible Electronics

Master Classes on Nov 19 & 22: • Intro to Printed Electronics • Intro to Energy Harvesting • Printing Technologies for Electronics • Displays & Lighting: OLED, LED, E-Paper • Graphene and Carbon Nanotubes • Sensors & Actuators • Energy Storage: Batteries & Supercapacitors • The Internet of Things • 3D Printing • Thin Film Photovoltaics … and more!

Use code “IEEE-30” for 30% discount thru Nov 17th. Exhibits-only option available.

www.PrintedElectronicsUSA.com

Exhibit at the Tradeshow! Over 100 leading companies will be showcasing innovative technologies and commercial applications in the field of printed electronics, OLEDs and 3D Printing at the world’s biggest tradeshow on the topic – an ideal place to meet your potential customers.

For information on exhibiting, please contact Sarah Parish, [email protected]

IEEE Professional Skills Courses

http://www.effectivetraining.com/calendar.php?loc=local

http://www.PrintedElectronicsUSA.com/

mailto:[email protected]?subject=GRID_Inquiry:


Today the focus on 3-D integration and

packaging has shifted from trying to understand the technology opportunity to one of understanding the practical challenges of technology adoption and commercialization, including who is getting there first, how, and at what cost. There remains a natural degree of uncertainty as companies work to secure a technology position, obtain new process and design tools, and new customers and new applications.

This conference continues to give a broad yet thorough perspective on the techno-market opportunity and challenge offered by building devices and systems in the vertical dimension. Industry leaders from around the world are invited to speak on topics important to the emerging and on-going 3-D related efforts. The format of the conference and its presentations enables speakers to present the most up-to-date and forthright perspectives as possible. This conference provides a unique forum where one can gain the latest insights to bring clarity in the direction of their own efforts.

AnDevCon Comes Back to Burlingame!

AnDevCon is the technical conference for software developers building or selling Android apps. Whether you're an enterprise developer, work for a commercial software company, or are driving your own start-up, if you are building Android apps, you need to attend AnDevCon. You’ll find hundreds of experienced developers and engineers (like you) choosing from more than 50 classes to bring Android open source development to a high level. Exhibit Hall hours:

Thursday Nov 14 11:00 am – 7:00 pm Friday Nov 15, 11:00 am – 2:30 pm

“This was a great conference! The scope and breadth of

classes gave a great opportunity to learn more about Android development in general AND gave the

opportunity to network with other people at all levels. It's a great learning place with wonderful people!”

Andrew Mauer, Sr. Project Manager, B-Line Express, Inc.

Monday Pre-Conference Half-day Symposium: “Optical Electronics: Increasing Bandwidth

While Reducing Power and Size” ● Opto Systems in Silicon ● System Vendor Perspective ● Scaling Challenges ● Technical Gaps, Roadmaps

Sessions – 30 top industry speakers on: ● Wafer Level System Integration Technology, Progress ● Emerging Pathways in Heterogeneous 3D Integration ● Options for Memory-Logic Integration ● Interposers ● Thermal Challenges, Potential Solutions, Impact ● Thin Wafer Handling and Direct Bonding ● Advances in 2.5D/3D Design and Test ... and more.

Earlybird Rates through October 31st (save $150). Corporate multi-attendee discount.

Full details:

techventure.rti.org

November 12-15, 2013 Hyatt Regency Burlingame

Technical Classes Keynotes, Exhibits, more

Keynote: “The Golden Age of Android,” Jeff Seibert, Twitter

Technical Classes: - Product-Centric Mobile Apps and the Internet of Things - Advanced Patterns for Connected Apps - Agile Android - Android as the New Embedded Linux - Android Custom Views, the Right Way - Android Connected TV Nuts and Bolts - Android OpenGL ES Essentials - Battle-Tested Patterns in Android Concurrency - Android Performance Tips - Bootstrapping Android Development - Becoming More Effective with the Android Emulator - Creating Composite Views in Android - Cross-Platform Dev’t for Android and iOS using C# - Dynamic Audio for Apps and Games - OK, Glass, Let's Explore … plus dozens more.

Earlybird registration thru Oct 25th – save $300 And save $100 by using Code “IEEE”

on 3-day passport, or for free exhibits admission.

For information and to register, visit

www.AnDevCon.com

Hyatt Regency SFO, Burlingame December 11-13, 2013

http://techventure.rti.org/

http://www.AnDevCon.com/


January 28 - 31, 2014

Santa Clara Convention Center

-- 100+ technical papers/panels in 14 Tracks -- 100's of design tools & solutions

DesignCon brings together leading engineers and organizations presenting EDA tools, test and measurement equipment, PCBs and related technologies, semiconductor components and IP, interconnect technologies, and more. Papers discuss cutting-edge case studies, technology innovations, practical techniques, design tips and application overviews.

DesignCon Tracks: 1. Optimize Chip-Level Designs for Signal and Power Integrity 2. Overcome Analog and Mixed-Signal Design and Verification Challenges 3. Wireless and Photonic Design & Integration 4. Optimize System Co-Design: Chip/Package/Board 5. Characterize PCB Materials and Processing Characterization 6. Apply PCB Design Tools and Methodologies 7. Design Parallel and Memory Interfaces 8. Optimize High-Speed Serial Design 9. Detect and Mitigate Jitter, Crosstalk, and Noise 10. Leverage High-Speed Signal Processing for Equalization and Coding 11. Ensure Power Integrity in Power Distribution Networks 12. Achieve Electromagnetic Compatibility and Mitigate Interference 13. Apply Test and Measurement Methodology 14. Ensure Signal Integrity With RF/Microwave/EM Analysis Techniques

Plus: 130+ exhibitors showcasing a wide variety of advanced design tools – Free panel discussions, speed-trainings & product teardowns – DesignTOUR prizes and giveaway – Happy Hours – DesignVision and Best in Test Awards …and more.

Sponsors:

The premier event developed

for engineers by engineers

This is your one-stop shop to upgrade your knowledge and skills with the latest theoretical design techniques and methodologies while seeing first-hand demonstrations of today's most advanced design tools and technologies.

Attending DesignCon will enable you to meet and interact with industry professionals and technical experts in similar roles and organizations around the country. You gain valuable information and insights, an understanding of what our peer organizations are talking about and planning for, and how they are accomplishing certain goals or tackling specific challenges that are similar to our own. The four days at DesignCon is the most cost-effective educational and training choice you can make all year. You will experience a full year of benefits in the form of new and greater knowledge and practical skills and techniques that you can apply directly to your job.

Every year, thousands of engineering professionals make the decision to start the year off right with DesignCon.

Free Expo pass – Admission to Chiphead theater, special events, keynotes and exhibits.

Early Bird Pricing through November 1st! Group Discounts for groups of 5 or more. 20% discount with promo code IEEE20

For full Conference Program and registration information:

www.designcon.com

http://www.designcon.com/


Have you ever wanted to continue your education in engineering while you continued working? Santa Clara University’s School of Engineering offers graduate degree and non-degree programs to both full-time students and working professionals. Simplified registration for the Winter Open University. Graduate-level instruction. Up to 16 units may be transferred to a graduate-degree program.

Early-morning classes: - Probability - Database Systems - Linear Control Systems - Analog ICs - Energy Transmission and Distribution - Active Microwave Devices (and more)

Evening classes: - Linear Algebra - Intro to Nano-Bioengineering - VLSI Design - Computer Architecture - Network Management - Logic Design using HDL - Robotics (and more)

Saturday classes: - Secure Coding in C and C++ - Project Risk Management - Gender and Engineering (and more)

Email LeAnn Marchewka with inquiries: [email protected]

Cloud Networking has emerged as a promising direction for cost-efficient and reliable service delivery across data communication networks. While the "computing" aspects of Cloud technologies have been largely investigated, CloudNet 2013 is devoted to the networking aspects, to fill this gap.

Keynote Speakers: "MultiService Network and Cloud

Orchestration," Dave Ward, Cisco "Network Virtualization: Enabling the

Software-Defined Data Center," Bruce Davie, VMware

Victor Bahl, Microsoft

+ An Invited Industry-Track Session

Offer support and receive mindshare and admissions -- become a Sponsor! See the “Patrons”

tab on the website.

Prepare for that next

project or assignment!

To remain competitive in Silicon Valley's changing environment, engineers need to update their knowledge base. The School of Engineering offers professional Certificates and Open University programs, as well as graduate degrees, for those who are driven to become leaders in their fields.

Winter Registration opens October 26 Classes begin January 6, 2014

Located in the heart of Silicon Valley, with easy parking

Review fall quarter Open University courses:

www.scu.edu/engineering/graduate

Hilton Hotel, San Francisco Financial District

Panel: "Cloud Networking and Intercloud: Challenges and Approaches" Moderator: Steve Diamond, EMC. Panelists: Amol Mohajani, HP; Jennifer Lin, Juniper; Masum Hasan, Cisco

Seven Technical Sessions (more than 30 presentations): SDN, OpenFlow, and Cloud Data Center Optimization Cloud Infrastructure and Service Construction Cloud Storage Systems Security, Privacy and Trust Management Mobile Cloud Network Virtualization, Placement/Migration Transport and Higher Layers for CloudNet

For more information and to register:

www.ieee-cloudnet.org

Santa Clara University School of Engineering Graduate Programs

SCU Winter Open University

http://www.scu.edu/engineering/graduate/

mailto:[email protected]?subject=GRID_Inquiry:

http://www.ieee-cloudnet.org/


San Jose/Mountain View Classes

Headquartered in Mountain View since 1985, we have delivered theory with hands-on practical training to professionals working with analog, RF, wireless, digital, and networking technologies -- to over 45,000 people in these industries. Besser Associates instructors are top luminaries in their field. Their work experience provides insights that help you avoid pitfalls on the job.

Regular Classes and Labs October, 2013 RF Measurements: Principles and Demonstration Oct 28-Nov 1

November, 2013 Hardware DSP: A guide to building DSP Circuits in FPGAs Nov 18-20

LTE & LTE-Advanced: A Comprehensive Overview Nov 18-20

Phase-Locked Loop and Frequency Synthesis Design Nov 21-22

December, 2013 Introduction to Wireless Communication Systems Dec 9-10

Signal Integrity and EMI Fundamentals Dec 11-13

February, 2014 Monolithic Microwave Integrated Circuit (MMIC) Design Feb 5-7

RF and High Speed PCB Design Fundamentals (Los Angeles near LAX) Feb 24-26

April, 2014

RF Design Techniques Mar 31 - Apr 4

DSP - Understanding Digital Signal Processing Apr 1-3 .

Besser Associates’ On-site Courses can be conducted at any US or International location and any course can be

customized to fit the specific needs of your group.

Upcoming Courses for

Engineering Professionals

Web-Classroom Live eLearning

Upcoming Web-Classroom Classes

Introduction to GaN Power Amplifiers Dec 9-11

EMC/Shielding/Grounding Techniques for Chip & PCB Layout Jan 27-31

RF Design: Core Concepts Mar 17-21

Use the code below to download our schedule:

www.besserassociates.com/Schedule.pdf

For these and other classes, or customized/ private courses at your facility, visit the website:

www.besserassociates.com

http://www.besserassociates.com/Schedule.pdf

http://www.besserassociates.com/


Emerging Technologies for 3GPP LTE/LTE-Advanced

Speaker: Prof. Lingjia Liu, Electrical Engineering and

Computer Science Department, University of Kansas

Time: Networking with food and drinks at 6:30 PM; Presentation at 7:00 PM

Cost: $5 Place: Maxim, 160 Rio Robles, San Jose RSVP: from website Web: www.eventbrite.com/event/8846960497

Lingjia Liu, received the Ph.D. degree at Texas A&M University in Electrical and Computer Engineering, the B.S. degree with highest honor at Shanghai Jiao Tong University in Electronic Engineering. He is currently working as an Assistant Professor in the Electrical Engineering and Computer Science Department at the University of Kansas (KU). Prior to joining the EECS at KU, he spent more than three years in Samsung Research America-Dallas (SRA-D) leading Samsung's work on downlink multi-user MIMO, Coordinated multipoint (CoMP) transmission, and Heterogeneous Networks for 3GPP LTE/LTE-Advanced standards. His research is currently funded by National Science Foundation (NSF), Samsung Research America-Dallas, U.S. Air Force Office of Scientific Research, U.S. Air Force Research Laboratory, and University of Kansas Center for Research Inc. His work on LTE/LTE-Advanced was quoted in the September issue of IEEE Spectrum.

Lingjia Liu is a recipient of the Texas Telecommunications Engineering Consortium (TxTEC) Fellowship from the Department of Electrical and Computer Engineering at Texas A&M University in 2003-2004. He received the Global Samsung Best Paper Award in 2008 and 2010 respectively. He is the best paper finalist for the ICC 2012 Wireless Communication Symposium (5/508). In 2013, he is selected as the Air Force Summer Faculty Fellow. He has also been selected by the National Engineers Week Foundation Diversity Council as New Faces of Engineering 2011 and was recognized during the 2011 National Asian American Engineers of The Year Awards Banquet in Seattle.

Lingjia Liu is currently serving as Technical

Program Committee (TPC) co-Chair and a Member of various international conferences and workshops. He has been frequently invited to serve on the NSF proposal review panels. He is also serving as an Editor for IEEE Transactions on Wireless Communications, and as Associate Editor for the EURASIP Journal on Wireless Communications and Networking as well as Wiley's International Journal on Communication Systems. He has 15+ journal publications, 25+ conference papers, 30+ US patent applications, 10+ essential intellectual property rights (IPRs), and numerous technical contributions to major wireless standards including both 3GPP LTE/LTE-Advanced and IEEE 802.16m.

TUESDAY October 29, 2013

SCV PACE (Professional Activities Committee for Engineers) with Education and Information Theory Chapters


Volunteer Information Evening

Speakers: from various organizations (Second Harvest Foodbank, Science Fairs, more)

Time: 6:00 PM - 8:00 PM Cost: none Place: LinkedIn, 2027 Stierlin Ct, Mountain View RSVP: from website Web: ieee-gold-vie.eventbrite.com

Come out and join the IEEE SCV GOLD in our

annual Volunteer Information Evening to learn about a number of volunteering opportunities in the Bay area. Our goal is to arrange a diverse range of speakers for you from a number of organizations in the area. Some roles will allow for you to use your technical skills to improve the world, while others will be less technical in nature. It is our goal to find a number of volunteering roles with varying commitment levels from 1 hour one time to a few hours per month so that you can find a way to give back regardless of your schedule and commitment level. Current confirmed organizations for this evening include Second Harvest Foodbank and the local Science Fairs.

Dinner will be provided by the IEEE SCV GOLD, but donations will be requested with all proceeds going to an IEEE SCV GOLD scholarship for a student studying in one of the fields related to the IEEE.

What is GOLD?

For those of you that don't know, GOLD is the Graduates of the Last Decade affinity group of the IEEE. We primarily focus on helping recent graduates be productive in their jobs and to achieve success through networking (social), technical and professional development events.

MONDAY November 4, 2013

SCV GOLD (Grads of the Last Decade)

http://www.armtechcon.com/?cid=IEEEGrid


The History of Robots

Speaker: Dave Grossman, IEEE Fellow Time: Networking at 6:00 PM; dinner at 6:30 PM Cost: $25 for IEEE members; $27 for non-

members Place: Michaels Restaurant, 2960 N Shoreline

Blvd., Mtn.View RSVP: from website, or by email to

[email protected] Web: www.ieee4life.org/SCV

Dave Grossman is an IEEE Fellow for his work in robotics. After a PhD in Physics from Harvard, he taught at Princeton for a few years. He spent 25 years at IBM in Yorktown Heights NY, in research and management in AI and robotics. A co-inventor of using software to calibrate robots, he pioneered robot assembly of electronic cards, 2-arm robots with collision avoidance, and 3D solid modeling. He also worked on RoboDoc hip surgery and laparoscopic robotics. After IBM, he worked at USC and then co-founded an internet company in Silicon Valley. Subsequently he worked on Stanford projects in the mechanical engineering department and in the medical school. He was also a tour guide at SLAC for a few years. He is currently semi-retired … which means working harder than ever but not getting paid.

Two highly unusual accomplishments: he patented a corrugated cardboard snowplow, and he built in his garage a huge cosmic ray exhibit that will eventually be installed in a science museum.

An irreverent non-technical review of the history of

surprisingly animate machines, from ancient Egypt to current times. Areas include teleoperators for hazardous environments, assembly systems, medical applications, entertainment, and science fiction. The talk has over 100 slides, covering such varied topics as Memnon son of Dawn, Droz’s automata, Vaucanson’s duck, cathedral clocks, Von Kempelen’s chess player, household robots, Asimov’s laws, Disneyland, dinosaurs, and movie droids and cyborgs.


SCV Life Members


Lift Labs: Defeating Human Tremors

Speaker: Anupam Pathak, Lift Labs Time: 7:00 PM Cost: none Place: Agilent Technologies, 5301 Stevens Creek

Blvd., Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org

Anupam Pathak is an inventor and entrepreneur at heart. He founded Lift Labs with the intent to apply his technical background to improve the quality of life for people suffering from Essential Tremor or Parkinson's Disease. Lift Labs is currently launching an active cancellation system that allows people to function despite their illness or disability.

Anupam received his BS and MS from UC Berkeley, and his Ph.D. from the Univ. of Michigan. He studied a diverse range of topics within Mechanical Engineering, including materials, controls systems, thermal science and design.

Outside of work, Anupam loves to teach hands-on science to children. In the past he co-founded a non-profit called Explorabox, whose mission is to provide hands-on science kits to children growing up in economic hardship.

Up to 10 million people in the US suffer from

tremor, typically due to Essential Tremor or Parkinson's Disease. The condition typically worsens with age, and currently there are few options for relief other than drugs or brain surgery.

This talk will discuss the new Lift Labs invention that can actively cancel the user's tremor by stabilizing the object being held. Clinical trial testing has shown tremor cancellation on average of 70%.

Anupam will also talk about the formation of Lift Labs, a great success story as it was formed using funding from the NIH Small Business Innovation Research (SBIR) Grant that was awarded shortly after he received his Ph.D. The awarding of each NIH SBIR Grant is a highly competitive process.

TUESDAY November 5, 2013

SCV Consultants' Network of Silicon Valley


Optical and Electronic Approaches to Restoration

of Sight to the Blind

Speaker: Prof. Daniel Palanker, Stanford University Time: Networking and Pizza at 6:00 PM;

Presentation 7:00 PM Cost: none Place: Intel, Building SC-12, 3600 Juliette Lane,

Santa Clara RSVP: from website Web: ewh.ieee.org/r6/scv/leos

Daniel Palanker is an Associate Professor in the Department of Ophthalmology and in the Hansen Experimental Physics Laboratory at Stanford University. He received his PhD in Applied Physics in 1994 from the Hebrew University of Jerusalem, Israel. Dr. Palanker studies interactions of electric field with biological cells and tissues in a broad range of frequencies: from quasi-static to optical, and develops their diagnostic, therapeutic and prosthetic applications, primarily in ophthalmology. Several of his developments are in clinical practice world-wide: Pulsed Electron Avalanche Knife (PEAK PlasmaBlade™), Patterned Scanning Laser Photocoagulator (PASCAL™), and 3-D Image-guided Laser System for Cataract Surgery (Catalys™). In addition to laser-tissue interactions, retinal phototherapy and associated neural plasticity Dr. Palanker is working on electro-neural interfaces, including the Photovoltaic Retinal Prosthesis for restoring sight to the blind.

Retinal degenerative diseases lead to blindness due to loss of the "image capturing" photoreceptors, while neurons in the "image-processing" inner retinal layers are relatively well preserved. Information can be reintroduced into the visual system using electrical or optical stimulation of the surviving inner retinal neurons. Some electronic retinal prosthetic systems have already been tested in human patients and approved for clinical use, while more advanced technologies are being developed . Alternatively, light sensitivity can be artificially introduced into retinal neurons using opto-genetic or opto-pharmacological methods. Several optogenetic approaches have been successfully tested in animal models of retinal degeneration. I will review the current state of art with each of these approaches, their challenges, technological solutions and perspectives of restoration of sight to the blind.

TUESDAY November 5, 2013SCV Photonics


3D Heterogeneous Microsystem Integration for Biomedical

Applications Speaker: Prof. Amine Miled, Electrical Engineering

and Computer Science Department, Univ of Laval, Quebec

Time: Networking with food and drinks at 6:00 PM; Presentation at 6:30 PM

Cost: $5 Place: Texas Instruments Auditorium, 2900

Semiconductor Dr, Santa Clara RSVP: from website Web: www.eventbrite.com/event/8846960497

Lab-on-Chip (LoC) are in their way to become the

new biomedical standard. This talk covers new developments and extended use of LoC, to integrate new technologies, in addition to new modeling techniques approaches. The objective is to design a LoC with new functions for a fully autonomous device.

In this seminar, a first prototype of an LoC with microelectronics and microfluidic modules, integrated communication system and embedded power supply unit in order to separate micro and nanoparticles with in vitro validations in cerebrospinal fluid are presented. A micro particle separation was achieved through the monitoring of electrical field propagation, frequency, phase and amplitude using different architectures of electrodes. Our objective is to propose new diagnostic tools for a better understanding of neurodegenerative diseases.

We also came up with an innovative approach to give greater flexibility to the modeling of LoCs. This approach consists of modeling the behavior of particles based on the architectural design of the electrodes, the applied signals, and the biological properties of the medium. This modeling technique is based on a hybrid approach including a finite element modeling using ANSYS, and an algorithm implemented on Matlab. Then it was possible to calculate each particle's 3D position in a micro channel based on the results provided by ANSYS, which is not possible based on experimental results.

Also, we built this system entirely with a 3D architecture using heterogeneous technologies including a microfluidic chip, a Bluetooth wireless unit, and an embedded power supply module. The whole microelectronic part of the LoC is designed with CMOS 0.18 um TSMC technology. The microfluidic architecture was fabricated with a new microfabrication process using femto laser and high accuracy dicing saw.


SCV PACE (Professional Activities Committee for Engineers)


Design Optimization of Robust and Quiet Electric Machines

Instructor: Dr. Dan Ionel, IEEE Fellow, Chief Engineer with Regal Beloit Corp, Visiting Professor, University of Wisconsin, Milwaukee

Time: 8:00 AM - 5:00 PM; Reception following Cost: none; includes lunch, breaks, reception Place: Hyatt Regency, Santa Clara RSVP: from website Web: www.e-grid.net/docs/1311-machines.pdf

Dr. Dan M. Ionel, IEEE Fellow, is currently Chief Engineer with Regal Beloit Corp. and Visiting Professor at University of Wisconsin, Milwaukee. For the last couple of years, he also served as instructor for short courses organized by ANSYS. Dr. Ionel has more than 25 years of experience with electrical machines and power electronic drives. After completing post-doctoral research in the SPEED Laboratory, University of Glasgow, UK, he worked in industrial R&D for large corporations in the UK and the US, Invensys Brook Crompton, and A.O. Smith, respectively. More recently, he was the Chief Scientist of the world’s largest wind turbine manufacturer, Vestas. Dr. Ionel’s design experience covers a wide range of electric machines and drives for various applications with power ratings between 0.002hp and 10,000hp. He has published more than 100 technical papers, including two winners of Best Paper Awards from the IEEE, and holds more than 30 patents. Dr. Ionel is the Chair-Elect of the IEEE Power and Energy Society Electric Motor Subcommittee, Chair of the Milwaukee IEEE Power Electronics Chapter, and Editor-in-Chief of the Electric Power Components and Systems Journal.

Dr. Julius Saitz, Application Engineer, Irvine, CA,

received his Ph.D. degree in 2001 from Helsinki University of Technology, Laboratory of Electromechanics. After that he worked as a post-doctoral researcher and lecturer in the same laboratory. In 2004 he joined ANSYS (at that time Ansoft) where he has worked as an application engineer, supporting the lectromechanical suite of tools. Dr. Saitz is a senior member of IEEE and has authored and co-authored several journal and conference papers.

This course provides know-how for applied theory

and advanced simulation techniques for electric machines and power electronics drives, from fractional-horsepower to multi-kilo-HP units. The lectures incorporate case studies from industrial practice and research and development projects . The attendees -- armed with the knowledge gained from this course -- will be able to apply simulation to their technical projects and help their companies streamline and shorten the cycle for delivering high quality products. the course incorporates material taught in recent short courses at University of Wisconsin and University of Michigan.

Fundamentals of electric machines and drives

operation and simulation – rotating fields, mmf, back emf, inductances, equivalent circuits, power flow, power electronics and topologies, control types, state-of-the-art electric machine technologies

• Robust design and optimization – FEA models for large scale optimization studies, DOE and Six-Sigma methods, computational intelligence optimization, differential evolution algorithms, case studies for rare-earth material reduction and for non-rare earth machine alternatives

• Electromagnetically generated forces, vibrations and noise – mechanism of production and transmission, design choices and recommendations, abnormality and faults, condition monitoring

• Advanced modeling techniques – multi-physics models for coupled electromagnetic, mechanical and thermal problems, automation of post-processing tasks, machine parameters extraction, torque-speed curves, efficiency maps, coupled circuits for power electronics machine drives.

Dr. Pavani Gottipati, Application Engineer, Irvine,

CA, received her Ph.D. degree in 2011 from the Department of Electrical and Computer Engineering at Louisiana State University. During her graduate studies, she worked as a Research and Teaching Assistant at LSU and interned at Otis Elevator Company in Connecticut. She joined ANSYS in 2011 as a member of the Low Frequency Electromagnetics team. She is an active member of IEEE and SWE and has several publications.

THURSDAY November 7, 2013

Sponsored by ANSYS, Inc.


Wireless Power Transfer and Microwave Energy Harvesting

Speaker: Dr. Marc Rutschlin, CST; and Dr. Hubregt J.

Visser, Holst Centre, IMEC Time: 8:00 AM (PST) Cost: none Place: on the internet RSVP: from website Web: spectrum.ieee.org/webinars

Dr. Marc Rütschlin grew up and studied in Stellenbosch, South Africa. After completing his PhD in Electronic Engineering, with a focus on dielectric material characterization, he did post-doctoral studies at NIST in Boulder, Colorado, and at the University of Karlsruhe in Germany, with a focus on electromagnetic wave propagation in buildings and small antenna design respectively. Marc joined CST in January 2007, and currently works from CST’s UK office in Nottingham as the global market development manager for microwave and RF applications.

Hubregt J. Visser obtained his Ph.D. from the

Eindhoven University of Technology and Katholieke Universiteit Leuven. He has participated in several projects concerning near-field antenna measurements, monolithic microwave integrated circuits design, and phased-array antenna design. In 2009 he joined the Holst Centre as an employee of IMEC and works on wireless energy transfer. He is also an associate professor at Eindhoven University of Technology and author of the books: ‘Array and Phased Array Antenna Basics’ (Wiley, 2005), ‘Approximate Antenna Analysis for CAD’ (Wiley, 2009) and `Antenna Theory and Applications' (Wiley, 2012).

Although wireless energy transfer is an old idea

(Tesla patented one design in 1901), technological advances and the rise of portable devices have made it relevant again for different applications, such as wireless charging and energy harvesting.

This webinar will consist of two parts. The first part is a review of low frequency power transfer in two categories: short range-inductive charging and powering of electronic devices and electric vehicles, and mid-range power transfer through coupled resonant circuits. We will give several examples and highlight the role of simulation in the design of transfer systems. The tools in CST STUDIO SUITE® used for the design and optimization of these devices will be demonstrated, including the use of hybrid circuit-EM co-simulation to optimize matching circuits to improve link robustness.

The second part of the webinar is concerned with wireless energy transfer over longer distances, where the far-field transfer of RF energy may be used. We make a distinction between harvesting RF energy from signals present in the ambient and transferring RF energy by intentionally transmitting RF signals. After a discussion of the power densities, we will continue with (intentional) RF energy transfer for powering sensors to be used in Smart Buildings. The blocks of a far field RF energy transfer system will be discussed: Transmit antenna (and maximum allowed transmit power), propagation channel and rectifying antenna or rectenna. The components of the rectenna: rectifier, dc-dc boost converter and antenna, will then be discussed. Several examples will be shown.

As our webinar service provider is unable to support access via mobile devices, please ensure you use a desktop or laptop computer to register and attend the event.


SPECTRUM Magazine


Building an Organization that Fosters Creativity and Innovation

Speaker: Kimberley Wiefling, President, Wiefling

Consulting Time: Networking at 6:00 PM; Forum at 6:30 PM;

Dinner at 7:00 PM; Presentation at 7:30 PM Cost: $11 for IEEE members, $14 for

non-members Place: Ramada Silicon Valley, 1217 Wildwood Ave,

Sunnyvale RSVP: from website Web: www.ieee-scv-tmc.org

Kimberly Wiefling, president of Wiefling Consulting, enables teams to achieve what seems impossible, but is merely difficult. She regularly facilitates workshops on creativity, innovation, leadership, team effectiveness, and execution excellence globally.

Kimberly has worked with people from over 50 different countries, in companies ranging from startups to the Global 1000. A physicist by education, she began her career with 10 years at HP in product development program management and engineering leadership. She then spent 3 years growing Silicon Valley startups, including a Xerox PARC spinoff where she was the VP of Program Management and Organizational Effectiveness.

In the past 7 years she’s worked mainly with the globalizing Japanese companies. In 2007 she wrote what became a very popular project management book, “Scrappy Project Management - The 12 Predictable and Avoidable Pitfalls Every Project Faces”, also published in Japanese by Nikkei Business Press. Kimberly is a force of nature - a menace to mediocrity on a mission that matters. She’s determined to transform Planet Earth for the better, one inspired and engaged team at a time.

Many companies that were successful 100 years

ago no longer exist. Trapped by their own success, they gradually learn to reduce risk, avoid mistakes and failure at all costs, and consequently squelch or kill innovation and creativity. This makes them vulnerable to global competition from new or more aggressive companies with less to lose. Oddly enough, the most successful companies are the most vulnerable, as their very success can lead to an inability to recognize and adjust to shifts in the environment. This phenomenon has been described in detail in books like Clayton Christensen’s “The Innovator’s Dilemma” and Jim Collin’s “How the Mighty Fall”.

This presentation will explore the biggest barriers to breakthroughs in an organization, and practical ways to promote risk taking, thinking differently, and sparking innovative thinking in their organizations. Real-world examples of successful and unsuccessful innovators from a number of different industries will be examined and analyzed.

Highlights What is Creativity? Relationship of Creativity to Innovation Barriers to Creativity and Innovation Building Environments that Foster Creativity

and Innovation

THURSDAY November 7, 2013 SCV Technology Management


Mobile UX (User Experience) Prototypes

Speaker: Megan O'Rorke of O'Rorke Design, UX

Prototyper, UX Designer, Teacher Time: Networking at 6:00 PM; Presentation at

6:15 PM Cost: none Place: LSI Corp., 1320 Ridder Park Drive, San

Jose RSVP: from website Web: ieee-wie-scv.org

Megan O’Rorke uses her knowledge of how people and technology work to help us connect and live better lives. In 2012 her qualitative and quantitative research programs helped her team achieve record profits on Sony's e-commerce website store.sony.com. She has worked on a social network, mobile iOS apps, corporate and large e-commerce websites.

Megan is a UX consultant for start-ups and large companies and teaches UX at General Assembly.

You can code in HTML5, CSS3, Javascript and

more but how do you know if you're building the right thing? How do you create a product customers will fall in love with? One of the most critical skills in a User Experience Designer's toolkit is prototyping. Megan will share a framework and tools for creating testing and iterating designs. Learn how to do mobile UX prototyping anywhere -- even in a moving vehicle.


SCV Women in Engineering


Thermoreflectance Technique for Thermal Characterization

and Thermal Mapping

Speakers: Dr. Mo Shakouri, Dustin Kendig, Mark Aghili, Microsanj LLC

Time: Sign-in/Networking at 6:30 PM; Presentation at 7:00 PM

Cost: none Place: Agilent Technologies, 5301 Stevens Creek

Blvd, Santa Clara RSVP: not required Web: ewh.ieee.org/r6/scv/rl

Transient thermal analysis is becoming a critical

tool in research, development and quality analysis of state of art devices and circuits. This educational workshop will cover an overview of thermal imaging techniques, the latest on thermoreflectance solutions and capabilities plus a live hands-on demo.

An overview of thermal imaging techniques is given . Miniaturization of electronic and optoelectronic devices and circuits have increased switching speeds exasperating localized heating problems. Steady-state and transient characterization of temperature distribution in devices and interconnects is important for performance and reliability analysis. In this talk, we review various microscale and nanoscale thermal characterization techniques that could be applied to active and passive devices. Various contact and contactless techniques such as infrared microscopy, liquid crystal, micro Raman, Scanning thermal microscopy, and thermoreflectance will be reviewed.

High-speed transient thermoreflectance imaging of power transistor arrays, SCRs, BJTs, HEMPTs, microcoolers, GaN, LEDs and solar cells will be reviewed. These images show temperature non-uniformities, point defects, and open circuits in test samples. Sub-micrometer spatial resolution and 800 picosecond temporal resolution allow the characterization of skin effects and current crowding in high-speed electronic devices.

Finally, a live demonstration of thermoreflectance imaging will be conducted.

THURSDAY November 7, 2013 SCV Reliability


Energy Generation & Storage: Possibilities and Realities

Speakers: Dr. Daniel Hirleman, Dean, UC-Merced;

Dr. Yi Cui, Materials Science and Engineering, Stanford; Dr. Latika Menon, Department of Physics, Northeastern Univ; J. R. Gaines, Technical Director, Kurt J. Lesker Company; Craig Jacobsen, CEO/CFO, Point Source Power, Inc.

Time: 12:30 PM - 5:00 PM Cost: IEEE Members: $25, Non-members: $35,

Unemployed: $15 ($5 more at door) Place: Packard 101, 350 Serra Mall, Stanford RSVP: by Nov. 3rd, from website Web: sites.ieee.org/sfbanano

Join and meet new colleagues from industry and academia to learn from speakers at the frontier of energy storage materials and devices followed by a networking reception.

Speakers / Topics

Dr. Daniel Hirleman, Dean, School of Engineering, University of California, Merced: Opportunities for collaborative university – industry research for sustainable energy

Dr. Yi Cui, Associate Professor, Materials Science and Engineering, Stanford University: Designing & fabricating nanostructured materials for energy storage and generation

Dr. Latika Menon, Associate Professor, Department of Physics, Northeastern University: Development of nanomaterials for energy related applications

J. R. Gaines, Technical Director, Kurt J. Lesker Company: Revolutionary thin film micro-batteries – creating new products and markets

Craig Jacobsen, Co-founder and CEO/CFO, Point Source Power, Inc.: Nanoparticle enabled super electrodes for solid oxide fuel cells

SATURDAY November 9, 2013

SCV Nanotechnology


A New Type of Domain Wall in Ultrathin Films:

The Dzyaloshinskii Domain Wall Speaker: Andre Thiaville, LPS Time: 3:00 PM Cost: none Place: Lawrence Berkeley Natl Lab RSVP: Please respond by email with name,

company, to Peter Fischer, [email protected] by Nov 6.

Web: ewh.ieee.org/r6/oeb/mag

André Thiaville graduated from Ecole polytechnique, then studied Condensed Matter Physics in Orsay where he got his PhD, about Néel lines in the magnetic domain walls in bubble garnets. He then joined CNRS as staff researcher, working at the Laboratoire de Physique des Solides at the Université Paris-Sud in Orsay. The major part of his research concerns the magnetic structures at the meso-scale, that of domains and domain walls. For this, he has applied several observation techniques, mainly magneto-optical microscopy, magnetic force microscopy, and ballistic electron emission microscopy. In parallel, he always tries to compare, as quantitatively as possible, experimental results to the predictions of the accepted theory for the statics and dynamics of these structures, namely micromagnetics. More than ten years ago, he started the theoretical study of magnetic domain walls in nanowires, at a time when experiments on this topic were rare. As spin-transfer torque was introduced in Magnetism, he was one of the first to study its effect on the dynamics of domain walls in such samples, a subject that developed exponentially afterwards. This work was recognized in 2012 by the french Académie des Sciences through the prix Jean Protas. In the last year, he has been actively investigating all the tools of micromagnetics the effect of an interface DM term on the structure and dynamics of domain walls in ultrathin films with perpendicular anisotropy, in the asymmetric stacking configuration. At LPS, he is leader of the IDMAG research group, and scientist in charge for the research axis #2 of the lab, devoted to nanosciences.

We have explored a new type of magnetic domain

wall structure in ultrathin films with perpendicular anisotropy, as a consequence of the existence of a Dzyaloshinskii-Moriya interaction (DMI) due to the adjacent layers. This study was performed by numerical and analytical micromagnetics. The results show that these walls can, depending on the value of the DMI constant, move in stationary conditions at large velocities under large fields. These walls also show interesting properties of current-induced domain wall motion under the spin Hall effect. Even if, in statics, these walls look like Néel walls for large enough DMI (and have been known for some time), this is the first full micromagnetic study of them, that reveals that their dynamics are unique. Thus we propose to call them Dzyaloshinskii domain walls. I shall first describe the study of the dynamics of these walls in a 1D micromagnetic framework, and show that a simple collective coordinates model can be built to account for most of the physics of this case. In a second step, I will describe the additional features revealed by considering the full (2D) dynamics, with strong domain wall tilt effects appearing for large DMI, and the development of an appropriately extended collective coordinates model.

This work opens naturally into the micromagnetic study of skyrmions in ultrathin films with structural inversion asymmetry.


OEB Magnetics


Drinking from the Firehose: Run-ahead Transfer Prediction

in the Mill CPU Architecture

Speaker: Ivan Godard, CTO, Out-of-the-Box Computing

Time: Networking and refreshments at 6:30 PM; Presentation at 7:00 PM

Cost: none Place: Cadence / Bldg 10, 2655 Seely Ave, San

Jose RSVP: from website Web: sites.ieee.org/scv-cs

Ivan Godard has designed, implemented or led the teams for 11 compilers for a variety of languages and targets, an operating system, an object-oriented database, and four instruction set architectures. He participated in the revision of Algol68 and is mentioned in its Report, was on the Green team that won the Ada language competition, designed the Mary family of system implementation languages, and was founding editor of the Machine Oriented Languages Bulletin. He is a Member Emeritus of IFIPS Working Group 2.4 (Implementation languages) and was a member of the committee that produced the IEEE and ISO floating-point standard 754-2011.

Ivan is currently CTO at Out-of-the-Box Computing, a startup now emerging from stealth mode. OOTBC has developed the Mill, a clean-sheet rethink of general-purpose CPU architectures. The Mill is the subject of this talk.

Programs frequently execute only a handful of

operations between transfers of control: branches, calls, and returns. Yet modern wide-issue VLIW and superscalar CPUs can issue similar handfuls of operations every cycle, so the hardware must be able to change to a new point of execution each cycle if performance is not to suffer from stalls. To change the point of execution requires determining the new execution address, fetching instructions at that address from the memory hierarchy, decoding the instructions, and issuing them, steps that can take tens to hundreds of cycles on modern out-of-order machines. Without special provision, a machine could take 20 cycles to transfer in order to do one cycle of actual work.

The special provision in conventional out-of-order processors is the branch predictor, which attempts to predict the taken vs. untaken state of conditional branches based on historical behavior of the same branch in earlier executions. Modern predictors achieve 95% accuracy, and large instruction windows can hide top-level cache latency, which together are sufficient for programs like benchmarks that are regular and small. On real-world problems such CPUs can spend a third or more of cycles stalled for code.

The Mill uses a novel prediction mechanism to avoid these problems; it predicts transfers rather than only branches. It can do so for all code, including cold code that has never been executed, running well ahead of execution so as to mask all cache and most memory latency. It needs no area- and power-hungry instruction window, using instead a very short decode pipeline and direct in-order issue and execution. It can use all present and future prediction algorithms, with the same accuracy as any other processor. On those occasions in which prediction is in error, the mispredict penalty is four cycles, a quarter that of superscalar designs. As a result, code stall is a rarity on a Mill, even on large programs with irregular control flow.

The talk describes the prediction mechanism of the Mill and compares it with the conventional approach.

TUESDAY November 12, 2013SCV Computer


Design, Manufacturing and Performance of a 3D Random Access Memory Subsystem

Speaker: David Chapman, VP Technical Sales and

Marketing, Tezzaron Semiconductor, Inc. Time: Optional dinner at 6:00 PM; Presentation at

6:45 PM Cost: $20; $10 for full-time students and

unemployed ($5 more at door) Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa

Clara RSVP: from website Web: www.cpmt.org/scv/meetings/cpmt1311.html

After early career stops at HP, Apple and Olivetti focused on technical training, David Chapman became a full time memory geek by joining Mostek as an applications engineer and product planner in 1984. An 11 year tour at Motorola Memory Division managing Product Planning and Applications Engineering started in 1988, followed by 14 years at GSI Technology, starting in 1998 where he served as VP of Marketing and Applications Engineering. David has specialized in developing performance differentiated memory, mainly SRAM and Low Latency DRAM, and taken numerous leadership roles in memory and interface standardization efforts. David joined Tezzaron on July 1, 2013 as VP of Technical Sales and Marketing with a charter to expand Tezzaron’s reach into commercial markets.

The litany of problems associated with 3D ICs is long and ugly. Early adherents have been taking it on the chin for poor yields, high costs, impossibly difficult process steps, questionable reliability and up to now, relatively little gain for all their pain. 3D has been a technology-in-waiting for a decade. But despite excruciatingly slow progress towards volume manufacturing, a broad conviction that it ought to work and should produce amazing results has persisted.

This talk will cover the architecture and the manufacturing flow used to build a 3D random access 64Gb volatile memory subsystem that produces 4Tb/s of data bandwidth, with 7ns random access latency. This 3D implementation solves the problems with 3D and enables the production of ICs with outstanding yield and that pass thermo-mechanical tests with ease. Specific enabling technologies such as tungsten vias, DBITM wafer bonding and self-test and repair will described. Performance characteristics including power consumption will be presented.

WEDNESDAY November 13, 2013

SCV Components, Packaging and Manufacturing Technology


Panel: Sensor Networks in Civic Infrastructure Applications

Speakers: Pramod Akkarachittor, Firetide Inc.; Dr.

Satwant Kaur, Chief Technologist, Innovation for HLS, Hewlett-Packard

Time: Registration, networking, light dinner at 6:30 PM; Presentation at 7:00 PM

Cost: $5 for food; no cost for presentation-only Place: Texas Instruments Building E, 2900

Semiconductor Dr., Santa Clara RSVP: from website Web: www.comsocscv.org

Pramod Akkarachittor is the Vice President Product Management at Firetide Inc. Pramod has responsibility for leading the product management team in developing the product strategy for the company’s wireless networking and network management products. He brings a blend of product management experience combined with over 10 years of wireless network design and development experience. Prior to Firetide, Pramod held several key technical management positions at Cisco. He has a Bachelor of Science degree in computer science and an MBA in marketing from HAAS, UC Berkeley.

Dr. Satwant Kaur, is currently Chief Technologist -

Innovation for HLS in the office of the CTO at Hewlett-Packard. She is the author of Amazon Bestseller “Transitioning Embedded Systems to Intelligent Environments.” She is a frequent speaker at industry events on M2M and embedded systems.

Session Co-Moderators: Narasimha Chari,

Director of Wireless/Mobile Communications Programs at Comsoc SCV, and MP Divakar, Secretary, Comsoc SCV.

"World's Longest Mesh Protecting Lives in

Thailand", Pramod Akkarachittor, VP of Product Management, Firetide Inc.

Public safety – protecting lives from the wrath of mother nature – was the major driver for development of Thailand’s wireless infrastructure. Rural and rugged terrains with no infrastructure called for a wireless infrastructure that delivers fiber-like performance coupled with fiber-like reliability. The presentation will cover the main drivers for a wireless mesh infrastructure comparing it to the alternatives. We will go over the operational and deployment challenges faced by the team, as well as the RF design and the reasoning behind it. In conclusion we will present the factors for a successful mesh deployment.

"Emerging Technologies for Smart Meshed

Cities", Dr. Satwant Kaur, Chief Technologist - Innovation, HLS, Hewlett-Packard

Rather than using centralized operating centers and systems, smart cities employ the wireless mesh network model that distributes city management to the granularity of the local level. The discussions will cover what makes a meshed city smart and the intelligent services thereof made possible by distributed local management of networked devices.

She will discuss distributed, fixed and mobile mesh networks, vehicular area networks (VAN) and other emerging technologies that are used to build smart cities. More importantly, she will show us how smart cities functions do fail, but the distributed nature of Smart City gives it the ability to identify and self learn from failures in an expedient manner. The discussions will also cover some applications, tools and services that make the notion of Smart City very appealing.


SCV Communications


EMC Simulation in the Design Flow of Modern Electronics

Speaker: Andreas Barchanski, EMC Market

Development Manager, CST Time: 8:00 AM (PST) Cost: none Place: on the internet RSVP: from website Web: spectrum.ieee.org/webinars

Andreas Barchanski is the EMC Market Development Manager at CST. He holds an M.Sc. degree in physics and a Ph.D. in numerical electromagnetics from the Technical University Darmstadt. He joined CST as an application engineer in 2007. Besides EMC, his main interest lies in the simulation of various electronic systems ranging from high speed digital to power electronics.

In the design process of modern electronics, every

product development starts with a schematic and ends with the physical implementation of the device, typically done in copper. Along the way of converting the schematic into a real layout however, the designer can fall into numerous possible pitfalls in terms of the EMC performance.

In this webinar we will show several examples of EMC countermeasures in modern electronics and good practices for implementing them, as well as highlighting some common mistakes. We will also demonstrate how simulation can predict the EMC performance of typical components like PCBs, enclosures and cables, and compare the simulation results to measurements performed on physical implementations of the structures.

As our webinar service provider does not support access via mobile devices, please ensure you use a desktop or laptop computer to register and attend the event.


SPECTRUM Magazine


Gigahertz Common-mode Filter for 10-Gbit/s Differential Signaling

Speaker: Miroslav Pajovic, RF/Microwave and EMI

Consulting Engineer Time: Presentation at 6:00 PM Cost: none Place: Agilent, 5301 Stevens Creek Blvd, Santa

Clara RSVP: not required Web: meetings.vtools.ieee.org/

meeting_view/list_meeting/20829

Miroslav Pajovic is currently an RF/Microwave and EMI consulting engineer. Previously he was an EMC designer and researcher in Cisco Systems, Inc., San Jose, and Nortel Networks Corporation, Santa Clara. As well, he was a Principal Staff RF Engineer in RF Centers in Washington, DC and Yugoslavia. He holds Diploma Degree in Electrical and RF Engineering (equivalent to M.Sc. degree) from Belgrade University, Serbia. He is an author of IEEE Transactions on EMC papers published 2007, 2008, and 2010; and USA patents filed 2011 and 2012.

In addition to the desired differential signals, the

undesired and EMI harmful common-mode noise may propagate along differential signal lines. Conventional common-mode filters such as ferrite chokes - which work well in lower frequencies below 1 GHz – have limited effectiveness in the gigahertz frequency range. To suppress critical common-mode in this frequency range without degrading the quality of the differential signals, a gigahertz common-mode filter structure is proposed. This design is directed to a compact-size electromagnetic band gap (EBG) structure suitable for placement in a multilayer PCB, individual IC chip package, or in an optical transceiver module. The filter provides common-mode suppression for 10-Gbit/s differential signal lines for the frequencies 10.3125 GHz and 20.625 GHz, where common-mode noise is highly problematic.

THURSDAY November 14, 2013 SCV Microwave Theory and Techniques


Sign-based Zero-Forcing Adaptive Equalizer Control

for High-Speed I/O

Speaker: Dr. Yasuo Hidaka, Fujitsu Laboratories of America

Time: Networking/Light Dinner at 6:30 PM; Presentation at 7:00 PM

Cost: $2 donation accepted for food Place: QualComm, Building B, 3165 Kifer Road,

Santa Clara RSVP: from website Web: sites.ieee.org/scv-cas

Dr. Yasuo Hidaka is a senior researcher in Platform Technology Innovation Group at Fujitsu Laboratories of America, Sunnyvale. At FLA, he is working on research and development of high-speed interconnect technologies for Fujitsu Servers, primarily focusing on signal integrity problems of electrical interconnect from both sides of transmission channel and I/O circuit. He has acquired a broad range of in-depth experience and knowledge in his career in computer science, electrical engineering, and mechanical engineering, including but not limited to mixed-signal analog circuit, digital/analog signal processing, logic design and verification, high-speed analog circuit, adaptive control theory, etc. He received his Ph.D. in Information Engineering from University of Tokyo in 1995 where his research focused on parallel computer architecture. He received M. Eng. in Information Engineering and B. Eng. in Precision Machinery both from University of Tokyo in 1991 and 1989, respectively. He co-authored 2 books, authored or co-authored 14 journal papers, and 15 peer-reviewed conference papers including 5 papers in ISSCC. He holds 31 granted U.S. patents.

Equalizers are often used for wireline transceivers

to cancel Inter-Symbol Interference (ISI) caused by frequency-dependent channel loss. Adaptation of equalizer parameters is desired, because channel characteristics are generally unknown. Least Mean Square (LMS) and Sign-Sign-LMS (SS-LMS) are adaptation algorithms widely used in digital signal processing, because it is easy to achieve minimum mean square error (MMSE) using these algorithms. However, LMS and SS-LMS are generally not applicable to mixed-signal circuits such as continuous-time linear equalizer (CTLE) or transmitter pre-emphasis in High-Speed I/O, because key reference information required for LMS and SS-LMS are not necessarily available for those mixed-signal circuits. On the other hand, Sign-based Zero-Forcing (S-ZF) is an adaptation algorithm that is always applicable to mixed-signal circuits including CTLE and transmitter pre-emphasis, because it does not require any additional reference information in analog circuits other than error information. Unlike conventional ZF, LMS, or SS-LMS, S-ZF does not assume random data sequence for measurement of correlation between error and reference information. Instead, S-ZF uses filter patterns to accurately de-convolve error information to residual ISI information. S-ZF works robustly for non-scrambled data such as 8B10B coding which may include a monotone sequence such as continuous 1010. Adaptation performance of S-ZF can be similar to LMS and SS-LMS, if used with proper parameters, because S-ZF can also achieve the MMSE condition for the worst channel. For decision feedback equalizer (DFE), S-ZF converges to the same state as SS-LMS, because they are based on the same formula. We have applied the S-ZF scheme for adaptation of equalizers such as CTLE, speculative or non-speculative DFE, and transmitter pre-emphasis in several generations of high-speed I/O from 1.25Gb/s up to 32Gb/s. Recently, we have also extended the S-ZF scheme to be applicable to low-frequency equalizer for which measurement of long-term residual ISI such as for 50 unit intervals (UIs) is required.

MONDAY November 18, 2013SCV Circuits and Systems


Fall Symposium: Nanoengineered Biomedical Devices

Speakers: Prof. Demir Akin, Stanford ; Prof. David

Deamer, UC Santa Cruz; Prof. Erkin Seker, UC Davis; Dr. Adam Seger, MagArray, Inc.; Dr. Mehdi Javanmard, Stanford; Dr. Dominik Ziegler, LBNL; Dr. Tom Peyser, Dexcom

Time: 9:00 AM - 4:00 PM Cost: IEEE Members: $30, Non-members:$40,

Students/unemployed: $20 ($10 more, at door)

Place: TI Auditorium E-1, 2900 Semiconductor Drive, Santa Clara

RSVP: from website Web: sites.ieee.org/sfbanano

Join colleagues from industry and academia to

learn from speakers at the frontier of nanotechnology enabled medical devices, diagnostics, and medical research.

SPEAKER / TOPICS:

Prof. Demir Akin, Deputy Dir, Ctr for Cancer Nanotechnology Excellence. Stanford School of Medicine. Cancer & Nanotechnology: Opportunities and Challenge

Prof. David Deamer, Biomolecular Engineering UC Santa Cruz: Nanopore Analysis of Nucleic Acids: From an Idea to a Working Instrument

Prof. Erkin Seker, Department of Electrical and Computer Engineering, UC Davis: Gold foams for biomedical devices

Dr. Adam Seger, Electrical Engineer, MagArray, Inc. Post-doctoral Researcher UC Santa Cruz: Magnetic nano-sensors for sensitive protein detection

Dr. Mehdi Javanmard, Senior Research Engineer, Stanford Genome Technology Center: Ultrasensitive Electrofluidic Technologies for Point-of-Care Diagnostics

Dr. Dominik Ziegler, Researcher, Molecular Foundry, Lawrence Berkeley National Laboratory: Scuba Dive to the Nanoscale: New Probes for Low-Noise Mass and Force Sensing in Liquids

Dr. Tom Peyser, Vice President, Science and Technology, Dexcom: Glucose monitoring

Prof Tao Ye, School of Natural Sciences, UC Merced: Developing sophisticated nanoscience tools to position and measure single molecules with nanometer resolution

TUESDAY November 19, 2013SCV Nanotechnology


Eastern Europe's Semiconductor Technology - Recollections and Projections

Speaker: Dr. Constantin Bulucea, IEEE Fellow, TI

(retired) Time: Networking and pizza at 6:00 PM,

Presentation at 6:15 PM Cost: none Place: Texas Instruments Building E Conference

Center, 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/eds

Constantin Bulucea was born in Romania, where he received the titles of inginer and doctor-inginer from the Polytechnic Institute of Bucharest in 1962 and 1974, respectively. His professional career spans 50 years, equally split across the Romanian and US semiconductor histories. In Romania, he was the scientific director and director of the R&D Institute for Electronic Components (ICCE) between 1974 and 1986, with assignments of national importance, such as the introduction of silicon transistor technology and the development of the process technology for the Microelectronica MOS/VLSI plant. From that period, his personal legacy includes the creation of the Annual Conference for Semiconductors (CAS), now an international IEEE event.

In the US, he remained on the technical side of the semiconductors business, so enjoying the last years of Silicon Valley’s “Happy Scaling”. In particular, at National Semiconductor, he was the architect of the company’s 0.25, 0.18, and 0.13 um CMOS processes for analog and mixed-signal applications. Before that, he brought to completion Siliconix's device/process architecture for the next generation of trench power DMOS transistors, which became an industry standard in the following years. He has published over 50 technical articles in international journals and holds 60 US patents.

Dr. Bulucea is an IEEE Fellow and an Honorary Member of the Romanian Academy. In 2011, he became a Distinguished Member of the Technical Staff of Texas Instruments (TI), as the result of National Semiconductor’s acquisition. He retired from TI last year, on his 72nd birthday.

Emerging from isolation in forced economic

independence, the semiconductor industries in the Eastern block is seen as having recently gone through three decades of government-backed growth followed by economic collapse (1981-1990), rough transition to the market economy (1991-2000), and stabilization to a new equilibrium within the globalization trend (2001 to 2010). Concurrently, the Western block had its growths, enthusiasms, delusions and corrections. The dynamics of these evolutions will be illustrated with landmark achievements associated with advancing on corresponding “Moore’s Law” curves.

At the world level, relatively longer times are observed from invention to application, as the complexity of the new processes and systems increases. It has taken 13 years for the CMOS IC

invention to be used in primitive microprocessors (20 for more practical ones), versus only 5 for the bipolar IC invention to find its place in space guidance computers. This observation is important when projecting the application of nanotechnologies to VLSI electronics.

The remainder of the discussion will analyze what is expected to happen in the East in the following years. Learning from the observed unpredictability of the semiconductor industry, the speaker will make cautious predictions, still insisting on the very-high-technology commodity characteristic of digital VLSI electronics. Correspondingly, VLSI products will be profitably manufactured in foundries having price tags in the range of $10B. However, the design, modeling/simulation, and testing of such products will remain realistic everywhere. Among other areas of realistic opportunities, the speaker will suggest analog and mixed-signal ICs, power switches and photovoltaics, TCAD, and nanotechnology, each commented separately. For the latter, reduction to practice appears to be the most critical expectation. The globalization-related unemployment will be commented briefly based on statistical distribution of “skills” in the population.


SCV Electron Devices


Tuning Magnetic Anisotropy in (001)-Oriented L10 (Fe1-xCux)55Pt45 Films

Speaker: Dustin A. Gilbert, Physics Department,

University of California, Davis Time: Networking and pizza at 6:45 PM,

Presentation at 7:30 PM Cost: none Place: Western Digital, 1710 Automation Parkway,

San Jose RSVP: not required Web: ewh.ieee.org/r6/scv/mag

Dustin A. Gilbert received his BS in Physics from the University of California, Santa Cruz in 2008, MS in Physics at the University of California, Davis in 2009, and is currently completing his Ph.D. at the same institute working with Prof. Kai Liu. He has previously conducted research at Seagate, Naval Postgraduate School in Monterey, and CUBIC Defense Applications in San Diego. He has published 10 refereed journal papers and received a variety of recognitions, including the 2012 IEEE Magnetics Society Summer School Participant, NSF Graduate Student Fellowship Program 'honorable mention' in 2010, and the US Department of Homeland Security CHSC fellowship in 2008. His research interests include magnetic materials, magnetic interactions, and hysteretic reversal behavior.

The development of high anisotropy magnetic

materials that are compatible with industrial processing is critical in advancing magnetic recording, permanent magnet, and spintronic technologies. Specifically, high anisotropy materials are necessary to ensure long-term thermal stability in magnetic nanoelements, such as ultra-high density recording media and magnetic memory. A material of particular interest is L10 ordered FePt because of its large magneto-crystalline anisotropy, saturation magnetization, and chemical stability. A key limiting factor has been the high annealing temperature necessary to transform the as-deposited disordered face centered cubic (FCC) A1 phase into the ordered tetragonal L10 phase.

We have achieved (001) oriented L10 (Fe1-x Cux)55Pt45 thin films, with magnetic anisotropy up to 3.6×107 erg/cm3, using atomic-scale multilayer sputtering and post annealing at 400 °C for 10 seconds, which is a much lower temperature annealing for a much shorter time compared to earlier studies. By fixing the Pt concentration, structure and magnetic properties are systematically tuned by the Cu addition. Increasing Cu content results in an increase in the tetragonal distortion of the L10 phase, significantly changing the film microstructure and lowering of the saturation magnetization and anisotropy. The relatively convenient synthesis conditions, along with the tunable magnetic properties, make such materials highly desirable for future magnetic recording technologies.

This work has been supported by the NSF (DMR-1008791). Work at NTHU has been supported in part by Hsinchu Science Park of Republic of China under Grant No. 101A16.


SCV Magnetics


Remote Ground Fault Protection Issues

Speaker: Sergio Panetta, Vice President of Engineering, I-Gard Corporation

Time: Networking and relaxation at 5:30 PM, Presentation at 6:00 PM, Dinner at 7:00 PM

Cost: $25 ($10 for IEEE Student members) Place: Sinbad's Restaurant, Pier 2 The

Embarcadero, San Francisco RSVP: Please email Byron Lee,

[email protected] for reservations and to qualify for the drawing

Web: www.e-grid.net/docs/1311-sf-ias.pdf

Sergio Panetta is the Vice President of Engineering at I-Gard Corporation, a position he has held for over 16 years. With over 26 years of electrical engineering experience, both in switchgear design, commissioning and troubleshooting, Sergio continues to actively increase awareness on Electrical Safety on a global front. A senior member of the Association of Professional Engineers of Ontario, he was recently awarded Consulting Engineering status with the APEO professional body.

In addition to working on a number of industry working groups dealing with electrical safety and best practices including UL, IEC, CSA and IEEE, Sergio is the author and owner of several US Patents related to power resistors. He received his Masters of Electrical Engineering from McMaster University.

Power continuity is essential in wind power projects where a trip-out due to ground fault can have serious economic or operational consequences. An arcing phase-to-ground fault can totally destroy the equipment. Consequential downtime adds to the economic loss. Four typical grounding methods for generators and power systems are examined for these factors and the article concludes that resistance grounding provides the best protection against arcing ground-fault damage in wind power projects with distribution systems and improves reliability and availability of the power systems.

TUESDAY November 19, 2013SF Industry Applications


Special Design Considerations for Medical Electronics

Speaker: Jerry Twomey, Consultant Time: Optional dinner at Stanford Hospital

Cafeteria, 6:15 PM; Presentation at 7:30 PM

Cost: none Place: Room M-114, Stanford University Medical

School, Stanford RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs/

Jerry Twomey has designed multiple medical, consumer, and commercial products . Medical devices include blood glucose monitors, wireless-wearable EEG systems, cranial hypothermia systems, and others. His experience in semiconductors, mixed signal systems, signal processing, and analog front end devices is now being used on medical devices Jerry holds an MSEE from Worcester Polytechnic Institute, is a Senior Member of the IEEE, and is a contributing editor for Electronic Design Magazine.

Medical electronics devices sit within a complicated regulatory maze that is entirely different from other devices. Many engineers doing their first medical device hit a wall when trying to clear the compliance hurdle. Due to safety driven regulatory issues medical devices require special efforts in mechanics, electronics, and software. This presentation will go over many of the issues that need to be designed in from the start of a new product.

To be discussed:

IEC-60601-1 and IEC-61010 Target Devices

Patient Isolation Requirements

Risk Matrix Compliance

EMC Stress Testing and System Functionality

Programmable Devices and Software Regulatory Issues

In addition to regulatory requirements, circuits and systems techniques used to meet those requirements will be discussed.


SCV Engineering in Medicine and Biology


Molten Salt and Thorium Nuclear Power (MSR)

Speaker: Dr. Alexander Cannara, Cannara

Consulting Time: 6:00 PM Cost: $15, includes buffet dinner Place: Willow Tree Restaurant, 6513 Regional St,

Dublin RSVP: By Noon November 19, on website Web: www.ieee4life.org

Dr. Alexander Cannara is an electrical engineer, software and networking consultant and educator. He spent 25 years in computer networking, 12 of those managing, developing and delivering technical training. Alex has 15 years of consulting, 7 of those helping hundreds of organizations with network problems and design issues. He has taught courses in engineering, statistics, programming and networking at: Stanford, USF, International Technological University and Golden Gate and Silicon Valley Universities. Alex has worked with local and national groups on energy and climate issues and on safe nuclear power. He’s worked at: Ballantine Laboratories, RMC Research, Zilog, Gibbons and Associates, Mitsubishi Semiconductor, AMD, 3Com, Network General, Vitesse, PacketMotion and Xambala. Dr. Cannara holds a Ph.D. from Stanford University in Mathematical Methods in Educational Research and MS degrees in both Plasma Physics and Statistics.

Suppose someone told you there is a way of

generating heat and electrical power on an industrial scale without the fuel emissions, nuclear materials, and waste we now produce, and do it for the whole world for thousands of years, using a cheap, plentiful source. What would you say?

Suppose these power sources: Cannot explode because they are unpressurized

and produce no flammable materials Shut down naturally, without power or people, if

something goes wrong Are independent of water cooling, so can be built

anywhere, using little land Get their energy from cheap material abundant on

Earth, Moon, and Mars Can be made to consume nuclear wastes Produce valuable industrial/medical/scientific

isotopes now becoming scarce Have already been tested and shown to work Can be built and operated more cheaply than

coal, oil, or gas power The generic name for this is Molten-Salt Reactor

(MSR), and the specific variant is Liquid Fluoride Thorium Reactor (LFTR) -- all American inventions, for now. The Chinese and many others are busy finishing what we designed and operated in the 1960s at the Oak Ridge National Laboratory.


OEB Life Members Group


Ground Fault Current Protection of a 480Y/277V Power System -

Compliance with NEC Design Requirements

Speaker: Dev Paul, AECOM, Inc. Time: Networking at 5:30 PM, Presentation at

6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM

Cost: $25 for IEEE members, $30 for non-members, $15 for student and retired members

Place: Zio Fraedos, 611 Gregory Lane, Pleasant Hill

RSVP: by November 18 to Michael Nakamura, [email protected], 925-330-6595

Web: www.e-grid.net/docs/1311-oeb-pes.pdf

Dev Paul received a master’s degree in electrical engineering and joined Kaiser Engineers which merged with other design engineering companies and ultimately became part of AECOM. Currently in the Transportation division in AECOM’s Oakland office, he is the senior project director responsible for electrical work related to the cold-ironing projects, airport projects and AC/DC rail transit projects. Mr. Paul is the author of 26 technical papers published in the American Public Transportation Association (APTA) and IEEE conferences. In 2002, he received the Ralph H. Lee award from IEEE for his paper on DC Power Systems Grounding. He is the Vice-Chair of IEC/ISO/IEEE P80005-1 standard and Chairperson of Draft IEEE Standard P1627, “Standard for Grounding Practices for DC Electrification OCS including Application of Lightning Surge Arresters”. Dev is a member of several IEEE committees involved in the development of new standards.

Dev Paul will discuss his IEEE/PCIC 2013

Conference paper that he presented as the main author. This paper is based upon an actual design of port facility buildings that required installation of solar power to meet the port’s green energy initiative. For the building parking lots, solar panels were installed on each carport roof for generation of photovoltaic (PV) power. Each building’s main switchboard required a 480Y/277V, 3-phase, 4-wire power supply based upon the characteristics of the building loads and parking lot lighting system. The presentation will cover the following key project considerations:

Low-level arcing ground fault protection of building transformer secondary feeders to main switchboards and discussion of ground fault protection of equipment, NEC 230.95.

Connection of PV utility-interactive DC-AC inverters to buildings’ service switchboards and discussion of the switchboard bus rating, NEC 705.12.D. (2) and NEC 705.12.D. (7).

Although the design solution of a low-level ground-fault current protection on transformer secondary feeders is contained in NEC 240.92(C) (1) (2) Informational Note No.1, quite often in the design the implementation of a differential relay, device 87T, indicated in NEC, is overlooked by the design engineers and AHJ that approve the design. Discussion of technical issues of such protection and dealing with the utility company if power transformer is supplied by utility company will be discussed.

Transformer secondary feeder cables’ short-circuit current withstand capability that depends upon short-circuit fault clearing time by the transformer primary protection device will also be discussed. Although NEC Table 240.92 (B) describes the method of checking such requirements, but quite often design engineer may have difficulty, especially when transformer and secondary cables are by the utility company.

Fire Incident – Lack of transformer secondary ground fault current protection will also be presented.

This presentation will be very helpful for the design engineer involved in complying with NEC requirements and also meeting most recent electrical arc-hazard and coordinated ground fault protection.


OEB Power & Energy, with Industry Applications


Time-delayed Teleoperation of Robots in Space for

Satellite Repair

Speaker: Ryder C. Winck, Ph.D., Postdoc Research Fellow, Collaborative Haptics and Robotics in Medicine Lab, Department of Mechanical Engineering, Stanford University

Time: Presentation at 7:00 PM Cost: none Place: Carnegie Mellon University Silicon Valley,

Room 118, Building 23, N. Akron Road, Moffett Field

RSVP: not required Web: ewh.ieee.org/r6/scv/ras

Ryder C. Winck received the B.S. degree in Mechanical Engineering and B.A. degree in Visual Arts from Rice University in 2007, and the M.S. and Ph.D. degrees in Mechanical Engineering from the Georgia Institute of Technology in 2009 and 2012, respectively. He is currently a postdoctoral research fellow in the Collaborative Haptics and Robotics in Medicine Lab in the Department of Mechanical Engineering at Stanford University. His research interests are in control systems, robotics and haptic interfaces.

Telerobotics has the potential to facilitate the

repair of satellites in geosynchronous orbit by allowing human operators to interact naturally with remote objects. Time delays on the order of seconds make it difficult to provide immersive feedback to the operator, motivating the use of predictive visual and haptic displays of the robot and environment. I will present recent work in developing a teleoperation framework that compensates for delays and provides the operator with useful visual and haptic feedback. This framework invokes a two-part environment model that predicts motion of objects in the environment, both in free space and during contact with the robot. Model-mediated teleoperation is used to provide stable haptic feedback based on this two-part model. Two experiments demonstrating the benefits of the approach will be presented. The first, catching a moving object under time delay, makes use of the free space environment prediction. For this experiment, robot employs a directional dry-adhesive gripper for robust grasping of the object. The second experiment, pushing an object, tests the environment and robot predictions during contact and in transitions between free space and contact. Results demonstrate the ability of the prediction algorithm to provide reliable feedback and improve operator performance before, during, and after robot-environment interactions

THURSDAY November 21, 2013 SCV Robotics and Automation


State of the Gaming Industry - Technology & Trends

Speaker: Dean Takasahashi, lead writer, GamesBeat Time: Networking at 6:30 PM; Presentation at

7:00 PM Cost: $5 for members, $10 for non-members Place: National Instruments, 4600 Patrick Henry

Dr, Santa Clara RSVP: from website Web: ewh.ieee.org/r6/scv/ce

Dean Takasahashi is lead writer for GamesBeat at VentureBeat. He covers video games, security, chips and a variety of other subjects. Dean previously worked at the San Jose Mercury News, the Wall Street Journal, the Red Herring, the Los Angeles Times, the Orange County Register and the Dallas Times Herald. He is the author of two books, Opening the Xbox and The Xbox 360 Uncloaked.

With the recent $1B three day sales results for GTA5, new consoles for the holiday season and the opening of China to consoles, the gaming marketplace is extremely active. In addition to these high profile activities, new connected consoles, mobile and casual gaming and a variety of accessories is once again bringing the Gaming world to the front of the Consumer Electronics experience. Dean will provide an overview of what trends -- US and global -- we can expect in the gaming world as well as his insights on "what is hot" in the industry (hardware and software), in time for the holiday season.

TUESDAY December 3, 2013SCV Consumer Electronics


Trends in Mobile Processors Speaker: Mike Demler, Senior Analyst, The Linley

Group Time: 7:00 PM Cost: none Place: Agilent Technologies, 5301 Stevens Creek

Blvd., Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org

Mike Demler is a Senior Analyst at The Linley Group and a Senior Editor at Microprocessor Report. His diverse career spans nearly the breadth of the semiconductor industry in both technical and business roles, from early-stage R&D to IC design, manufacturing, and software tools.

Mike has extensive engineering experience and is a named inventor on eight US patents. He is the author of High-Speed Analog-to-Digital Conversion, an engineering textbook that has remained in print since 1991. He later served as a strategic-marketing director at Cadence and a product-marketing manager for Synopsys.

Starting this year, smartphone shipments will

represent more than half of the handset market. Mobile processors are the highly integrated Systems-on-a-Chip that have powered this revolution in portable computing devices. In a classic example of disruptive innovation, the rapid pace of change and cutthroat pricing have caused some semiconductor vendors to exit the market while a new generation of companies have risen to the forefront.

A multicore war is underway, with some chip companies pushing the limits from dual to quad to “Octa” configurations, with up to eight CPUs on a chip. New architectures are emerging, including ARM’s big.LITTLE CPU cores in true heterogeneous multiprocessing configurations. In addition, Apple's A7 announcement has kicked off the 64-bit debate, and Intel is continuing to pursue a foothold in this market with a new generation of x86 mobile processors.

In this presentation, Mike Demler will review the latest trends in mobile processors, and attempt to sort out some of the confusion in this highly competitive market.

TUESDAY December 3, 2013

SCV Consultants' Network of Silicon Valley

Download - GRID November 2013 GRID · November 2013 Visit us at Page 1 GRID.pdf SCV-Nano - 11/9 | SCV-ComSoc - 11/13 | erization and Thermal Mapping November 2013 CHAPTER MEETINGS

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