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Robert Bosch GmbH
Automotive Electronics (AE)
GTM-IP Generic Timer Module
GTM-IP Specification
Revision: 3.1.5.1 (Released on 24.03.2016)
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Automotive Electronics
GTM-IP Specification Revision 3.1.5.1
Robert Bosch GmbH ii 24.03.2016
Confidential
Confidential
Revision Number Notice
The specification revision number of this document consists of four decimal integers separated by a dot.
The first decimal integer represents the major release number, the second represents the minor release number and the third represents the delivery number of specification.
A GTM-IP release always refers to the first three decimal integer of the specification revision number and is extended by a design step identifier. This GTM-IP release number can be read out of register GTM_REV.
The fourth decimal integer of specification revision number is related to updated versions of the specification which are independent of a GTM-IP release.
During silicon validation and qualification process it may turn out that the current specification revision related to the silicon is incomplete, inconsistent or ambiguous. It may also be the case that the silicon behaviour diverges for a specific functional feature from specification but the behaviour of silicon is also acceptable for intended GTM applications. In these cases Bosch AE will update the specification and indicate this update by an increase of the fourth decimal integer of specification revision number.
An increased fourth decimal integer means that either the new specification is more precise or that a functional feature was limited or removed. It never means that there was added a new feature.
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Automotive Electronics
GTM-IP Specification Revision 3.1.5.1
Robert Bosch GmbH iii 24.03.2016
Confidential
Table of Contents
1 Introduction .................................................................................................. 1
1.1 Overview ........................................................................................................ 1
1.2 Document Structure ....................................................................................... 2
1.2.1 Sub-module groups ..................................................................................... 2
2 GTM Architecture ......................................................................................... 3
2.1 Overview ........................................................................................................ 3
2.1.1 GTM Architecture Block Diagram ................................................................ 3
2.1.2 ARU Data Word Description ........................................................................ 5
2.1.3 GTM-IP signal multiplex .............................................................................. 7
2.1.4 TIM auxiliary input multiplexing ................................................................... 7
2.1.5 TIM external capture forwarding to TOM and ATOM................................... 8
2.1.6 TIM to MCS signal forwarding ..................................................................... 9
2.2 GTM-IP Interfaces .........................................................................................10
2.2.1 GTM-IP Generic Bus Interface (AEI) ..........................................................11
2.2.2 GTM-IP Multi-master and multitasking support ..........................................12
2.3 ARU Routing Concept ...................................................................................12
2.3.1 Principle of data routing using ARU ............................................................13
2.3.2 ARU source and destination address count per instance ...........................14
2.3.3 ARU Round Trip Time ................................................................................15
2.3.4 ARU Blocking Mechanism ..........................................................................15
2.4 GTM-IP Clock and Time Base Management (CTBM) ...................................16
2.4.1 GTM-IP Clock and time base management architecture ............................16
2.4.2 Cyclic Event Compare ................................................................................17
2.5 GTM-IP Interrupt Concept .............................................................................18
2.5.1 Level interrupt mode ...................................................................................21
2.5.2 Pulse interrupt mode ..................................................................................23
2.5.3 Pulse-notify interrupt mode ........................................................................24
2.5.4 Single-pulse interrupt mode .......................................................................25
2.5.5 GTM-IP Interrupt concentration method .....................................................27
2.6 GTM-IP Software Debugger Support ............................................................27
2.6.1 Register behavior in case of Software Debugger accesses .......................27
2.7 GTM-IP Programming conventions ...............................................................28
2.8 GTM-IP TOP-Level Configuration Register Overview ...................................28
2.8.1 GTM-IP TOP-Level Configuration Register Overview Table ......................29
2.9 GTM TOP-Level Configuration Registers Description ...................................29
2.9.1 Register GTM_REV ....................................................................................29
2.9.2 Register GTM_RST ....................................................................................30
2.9.3 Register GTM_CTRL ..................................................................................31
2.9.4 Register GTM_AEI_ADDR_XPT ................................................................32
2.9.5 Register GTM_AEI_STA_XPT ...................................................................32
2.9.6 Register GTM_IRQ_NOTIFY .....................................................................33
2.9.7 Register GTM_IRQ_EN ..............................................................................35
2.9.8 Register GTM_IRQ_FORCINT ...................................................................37
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Automotive Electronics
GTM-IP Specification Revision 3.1.5.1
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2.9.9 Register GTM_IRQ_MODE ........................................................................38
2.9.10 Register GTM_BRIDGE_MODE.................................................................39
2.9.11 Register GTM_BRIDGE_PTR1 ..................................................................41
2.9.12 Register GTM_BRIDGE_PTR2 ..................................................................42
2.9.13 Register GTM_MCS_AEM_DIS .................................................................43
2.9.14 Register GTM_EIRQ_EN ...........................................................................44
2.9.15 Register GTM_CLS_CLK_CFG..................................................................45
2.9.16 Register GTM_CFG ...................................................................................49
3 Advanced Routing Unit (ARU) ...................................................................50
3.1 Overview .......................................................................................................50
3.2 Special Data Sources ...................................................................................50
3.3 ARU Access via AEI .....................................................................................51
3.3.1 Default ARU Access ...................................................................................51
3.3.2 Debug Access ............................................................................................52
3.4 ARU dynamic routing ....................................................................................53
3.4.1 Dynamic routing - CPU controlled ..............................................................53
3.4.2 Dynamic routing - ARU controlled ..............................................................56
3.5 ARU Interrupt Signals ...................................................................................56
3.5.1 ARU Interrupt Signals Table .......................................................................57
3.6 ARU Configuration Register Overview ..........................................................57
3.6.1 ARU Configuration Register Overview Table .............................................57
3.7 ARU Configuration Register Description .......................................................58
3.7.1 Register ARU_ACCESS .............................................................................58
3.7.2 Register ARU_DATA_H .............................................................................59
3.7.3 Register ARU_DATA_L ..............................................................................60
3.7.4 Register ARU_DBG_ACCESS0 .................................................................61
3.7.5 Register ARU_DBG_DATA0_H .................................................................61
3.7.6 Register ARU_DBG_DATA0_L ..................................................................62
3.7.7 Register ARU_DBG_ACCESS1 .................................................................62
3.7.8 Register ARU_DBG_DATA1_H .................................................................63
3.7.9 Register ARU_DBG_DATA1_L ..................................................................64
3.7.10 Register ARU_IRQ_NOTIFY ......................................................................64
3.7.11 Register ARU_IRQ_EN ..............................................................................65
3.7.12 Register ARU_IRQ_FORCINT ...................................................................66
3.7.13 Register ARU_IRQ_MODE ........................................................................66
3.7.14 Register ARU_CADDR_END .....................................................................67
3.7.15 Register ARU_CADDR ...............................................................................68
3.7.16 Register ARU_CTRL ..................................................................................68
3.7.17 Register ARU_[z]_DYN_CTRL (z:0...1) ......................................................69
3.7.18 Register ARU_[z]_DYN_RDADDR (z:0...1) ................................................70
3.7.19 Register ARU_[z]_DYN_ROUTE_LOW (z:0...1) ........................................71
3.7.20 Register ARU_[z]_DYN_ROUTE_HIGH (z:0...1)........................................71
3.7.21 Register ARU_[z]_DYN_ROUTE_SR_LOW (z:0...1) .................................72
3.7.22 Register ARU_[z]_DYN_ROUTE_SR_HIGH (z:0...1) .................................72
4 Broadcast Module (BRC) ............................................................................74
4.1 Overview .......................................................................................................74
4.2 BRC Configuration ........................................................................................74
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GTM-IP Specification Revision 3.1.5.1
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4.3 BRC Interrupt Signals ...................................................................................76
4.4 BRC Configuration Register Overview ..........................................................76
4.4.1 BRC Configuration Register Overview Table .............................................76
4.5 BRC Configuration Register Description .......................................................77
4.5.1 Register BRC_SRC_[z]_ADDR (z:0...11) ...................................................77
4.5.2 Register BRC_SRC_[z]_DEST (z:0...11) ...................................................77
4.5.3 Register BRC_IRQ_NOTIFY ......................................................................79
4.5.4 Register BRC_IRQ_EN ..............................................................................80
4.5.5 Register BRC_IRQ_FORCINT ...................................................................81
4.5.6 Register BRC_IRQ_MODE ........................................................................82
4.5.7 Register BRC_EIRQ_EN ............................................................................82
4.5.8 Register BRC_RST ....................................................................................83
5 First In First Out Module (FIFO) .................................................................84
5.1 Overview .......................................................................................................84
5.2 Operation Modes ..........................................................................................85
5.2.1 FIFO Operation Mode ................................................................................85
5.2.2 Ring Buffer Operation Mode .......................................................................85
5.2.3 DMA Hysteresis Mode ................................................................................86
5.3 FIFO Interrupt Signals ...................................................................................86
5.4 FIFO Configuration Register Overview .........................................................86
5.5 FIFO Configuration Registers Description ....................................................87
5.5.1 Register FIFO[i]_CH[z]_CTRL (z:0...7) .......................................................87
5.5.2 Register FIFO[i]_CH[z]_END_ADDR (z:0...7) ............................................88
5.5.3 Register FIFO[i]_CH[z]_START_ADDR (z:0...7) ........................................89
5.5.4 Register FIFO[i]_CH[z]_UPPER_WM (z:0...7) ...........................................89
5.5.5 Register FIFO[i]_CH[z]_LOWER_WM (z:0...7)...........................................90
5.5.6 Register FIFO[i]_CH[z]_STATUS (z:0...7) ..................................................91
5.5.7 Register FIFO[i]_CH[z]_FILL_LEVEL (z:0...7) ............................................91
5.5.8 Register FIFO[i]_CH[z]_WR_PTR (z:0...7) .................................................92
5.5.9 Register FIFO[i]_CH[z]_RD_PTR (z:0...7) ..................................................93
5.5.10 Register FIFO[i]_CH[z]_IRQ_NOTIFY (z:0...7)...........................................93
5.5.11 Register FIFO[i]_CH[z]_IRQ_EN (z:0...7) ...................................................94
5.5.12 Register FIFO[i]_CH[z]_IRQ_FORCINT (z:0...7) ........................................94
5.5.13 Register FIFO[i]_CH[z]_IRQ_MODE (z:0...7) .............................................95
5.5.14 Register FIFO[i]_CH[z]_EIRQ_EN (z:0...7) ................................................96
6 AEI to FIFO Data Interface (AFD) ...............................................................97
6.1 Overview .......................................................................................................97
6.2 AFD Register overview .................................................................................97
6.3 AFD Register description ..............................................................................97
6.3.1 Register AFD[i]_CH[z]_BUF_ACC (z:0...7) ................................................97
7 FIFO to ARU Unit (F2A) ..............................................................................99
7.1 Overview .......................................................................................................99
7.2 Transfer modes .............................................................................................99
7.2.1 Data transfer of both ARU words between ARU and FIFO ......................100
7.3 Internal buffer mode ....................................................................................100
7.3.1 Reconfiguration of F2A stream 4 to FIFO channel 0 ................................101
7.4 F2A Configuration Register Overview .........................................................101
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7.5 F2A Configuration Register description ......................................................102
7.5.1 Register F2A[i]_ENABLE .........................................................................102
7.5.2 Register F2A[i]_CH[z]_ARU_RD_FIFO (z: 0...7) ......................................103
7.5.3 Register F2A[i]_CH[z]_STR_CFG (z: 0...7) ..............................................103
7.5.4 Register F2A[i]_CTRL ..............................................................................104
8 Clock Management Unit (CMU) ................................................................106
8.1 Overview .....................................................................................................106
8.1.1 CMU Block Diagram .................................................................................106
8.2 Global Clock Divider ...................................................................................107
8.3 Configurable Clock Generation sub-unit (CFGU) ........................................108
8.3.1 Wave Form of Generated Clock Signal CMU_CLK[x] ..............................110
8.4 Fixed Clock Generation (FXU) ....................................................................110
8.5 External Generation Unit (EGU)..................................................................110
8.6 CMU Configuration Register Overview .......................................................111
8.6.1 CMU Configuration Register Overview Table ...........................................111
8.7 CMU Configuration Register Description ....................................................112
8.7.1 Register CMU_CLK_EN ...........................................................................112
8.7.2 Register CMU_GCLK_NUM .....................................................................113
8.7.3 Register CMU_GCLK_DEN .....................................................................114
8.7.4 Register CMU_CLK_[z]_CTRL (z:0...5) ....................................................114
8.7.5 Register CMU_CLK_6_CTRL ..................................................................115
8.7.6 Register CMU_CLK_7_CTRL ..................................................................116
8.7.7 Register CMU_ECLK_[z]_NUM (z:0...2) ..................................................116
8.7.8 Register CMU_ECLK_[z]_DEN (z:0...2) ...................................................117
8.7.9 Register CMU_FXCLK_CTRL ..................................................................118
8.7.10 Register CMU_GLB_CTRL ......................................................................119
8.7.11 Register CMU_CLK_CTRL ......................................................................119
9 Cluster Configuration Module (CCM) ......................................................121
9.1 Overview .....................................................................................................121
9.1.1 Cluster Clock Signal Wiring ......................................................................121
9.2 Address Range Protection ..........................................................................122
9.3 CCM Configuration Register Overview .......................................................123
9.3.1 CCM Configuration Register Overview Table ...........................................123
9.4 CCM Configuration Register description .....................................................124
9.4.1 Register CCM[i]_PROT ............................................................................124
9.4.2 Register CCM[i]_CFG ..............................................................................124
9.4.3 Register CCM[i]_CMU_CLK_CFG ...........................................................126
9.4.4 Register CCM[i]_CMU_FXCLK_CFG .......................................................129
9.4.5 Register CCM[i]_AEIM_STA ....................................................................129
9.4.6 Register CCM[i]_ARP[z]_CTRL (z: 0..NARP-1) .......................................130
9.4.7 Register CCM[i]_ARP[z]_PROT (z:0...NARP-1) .......................................132
9.4.8 Register CCM[i]_HW_CONF ....................................................................134
9.4.9 Register CCM[i]_TIM_AUX_IN_SRC .......................................................136
9.4.10 Register CCM[i]_EXT_CAP_EN ...............................................................139
9.4.11 Register CCM[i]_TOM_OUT ....................................................................139
9.4.12 Register CCM[i]_ATOM_OUT ..................................................................140
10 Time Base Unit (TBU) ...............................................................................142
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GTM-IP Specification Revision 3.1.5.1
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10.1 Overview .....................................................................................................142
10.1.1 TBU Block Diagram ..................................................................................142
10.2 TBU Channels.............................................................................................144
10.2.1 Independent Modes ..................................................................................144
10.2.2 Dependent Mode ......................................................................................145
10.3 TBU Configuration Register Overview ........................................................145
10.3.1 TBU Configuration Register Overview Table ............................................145
10.4 TBU Register description ............................................................................146
10.4.1 Register TBU_CHEN ................................................................................146
10.4.2 Register TBU_CH0_CTRL .......................................................................146
10.4.3 Register TBU_CH0_BASE .......................................................................147
10.4.4 Register TBU_CH1_CTRL .......................................................................148
10.4.5 Register TBU_CH2_CTRL .......................................................................149
10.4.6 Register TBU_CH[y]_BASE (y:1,2) ..........................................................150
10.4.7 Register TBU_CH3_CTRL .......................................................................150
10.4.8 Register TBU_CH3_BASE .......................................................................151
10.4.9 Register TBU_CH3_BASE_MARK ...........................................................152
10.4.10 Register TBU_CH3_BASE_CAPTURE ....................................................152
11 Timer Input Module (TIM) .........................................................................154
11.1 Overview .....................................................................................................154
11.1.1 TIM Block Diagram ...................................................................................154
11.1.2 TIM channel internal connectivity .............................................................155
11.1.3 Input source selection INPUTSRCx .........................................................156
11.1.4 Input observation ......................................................................................158
11.1.5 External capture source selection EXTCAPSRCx ....................................158
11.2 TIM Filter Functionality (FLT) ......................................................................160
11.2.1 Overview ..................................................................................................160
11.2.2 TIM Filter Modes ......................................................................................162
11.2.3 TIM Filter reconfiguration .........................................................................167
11.3 Timeout Detection Unit (TDU) .....................................................................168
11.3.1 Counter/comparator slice .........................................................................168
11.3.2 Used parallel functions .............................................................................169
11.3.3 Which of the available 8 bit resources are cascaded with a chosen SLICING 170
11.3.4 Architecture of the TDU Sub-unit..............................................................172
11.3.5 ACB Bits for valid data provided by a TIM channel ..................................175
11.4 TIM Channel Architecture ...........................................................................175
11.4.1 Overview ..................................................................................................175
11.4.2 TIM Channel Modes .................................................................................177
11.5 MAP Submodule Interface ..........................................................................194
11.5.1 Structure of map data ...............................................................................195
11.6 TIM Interrupt Signals ...................................................................................195
11.6.1 TIM Interrupt Signals Table ......................................................................195
11.7 TIM Configuration Register Overview .........................................................196
11.7.1 TIM Configuration Register Overview Table .............................................196
11.8 TIM Configuration Registers Description ....................................................197
11.8.1 Register TIM[i]_CH[x]_CTRL ....................................................................197
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11.8.2 Register TIM[i]_CH[x]_CTRL (i:0) .............................................................201
11.8.3 Register TIM[i]_CH[x]_FLT_RE ................................................................205
11.8.4 Register TIM[i]_CH[x]_FLT_FE ................................................................206
11.8.5 Register TIM[i]_CH[x]_GPR0 ...................................................................207
11.8.6 Register TIM[i]_CH[x]_GPR1 ...................................................................207
11.8.7 Register TIM[i]_CH[x]_CNT ......................................................................208
11.8.8 Register TIM[i]_CH[x]_CNTS ...................................................................209
11.8.9 Register TIM[i]_CH[x]_IRQ_NOTIFY ........................................................209
11.8.10 Register TIM[i]_CH[x]_IRQ_EN ................................................................210
11.8.11 Register TIM[i]_CH[x]_IRQ_FORCINT .....................................................211
11.8.12 Register TIM[i]_CH[x]_IRQ_MODE ..........................................................212
11.8.13 Register TIM[i]_RST .................................................................................212
11.8.14 Register TIM[i]_IN_SRC ...........................................................................213
11.8.15 Register TIM[i]_CH[x]_EIRQ_EN .............................................................215
11.8.16 Register TIM[i]_CH[x]_TDUV ...................................................................216
11.8.17 Register TIM[i]_CH[x]_TDUC ...................................................................217
11.8.18 Register TIM[i]_CH[x]_ECNT ...................................................................218
11.8.19 Register TIM[i]_CH[x]_ECTRL .................................................................218
11.8.20 Register TIM[i]_INP_VAL .........................................................................223
12 Timer Output Module (TOM) ....................................................................224
12.1 Overview .....................................................................................................224
12.1.1 TOM block diagram ..................................................................................224
12.2 TOM Global Channel Control (TGC0, TGC1) .............................................226
12.2.1 Overview ..................................................................................................226
12.2.2 TGC Sub-unit ...........................................................................................226
12.3 TOM Channel .............................................................................................229
12.3.1 TOM Channel 0..7 architecture ................................................................229
12.3.2 TOM Channel 8..14 architecture ..............................................................230
12.3.3 TOM Channel 15 architecture ..................................................................231
12.3.4 Duty cycle, Period and Clock Frequency Update Mechanisms ................233
12.3.5 Continuous Counting Up Mode ................................................................236
12.3.6 Continuous Counting Up-Down Mode ......................................................237
12.3.7 One-shot Counting Up Mode ....................................................................239
12.3.8 One-shot Counting Up-Down Mode .........................................................241
12.3.9 Pulse Count Modulation Mode .................................................................243
12.3.10 Trigger Generation ...................................................................................245
12.4 TOM BLDC Support ....................................................................................246
12.5 TOM Gated Counter Mode .........................................................................246
12.6 TOM Interrupt signals .................................................................................246
12.7 TOM Configuration Register Overview .......................................................247
12.8 TOM Configuration Register Description ....................................................248
12.8.1 Register TOM[i]_TGC[y]_GLB_CTRL (y:0...1) .........................................248
12.8.2 Register TOM[i]_TGC[y]_ENDIS_CTRL (y:0...1) .....................................249
12.8.3 Register TOM[i]_TGC[y]_ENDIS_STAT (y:0...1) ......................................251
12.8.4 Register TOM[i]_TGC[y]_ACT_TB (y:0...1) ..............................................252
12.8.5 Register TOM[i]_TGC[y]_OUTEN_CTRL (y:0...1) ....................................253
12.8.6 Register TOM[i]_TGC[y]_OUTEN_STAT (y:0...1) ....................................254
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12.8.7 Register TOM[i]_TGC[y]_FUPD_CTRL (y:0...1) .......................................254
12.8.8 Register TOM[i]_TGC[y]_INT_TRIG (y:0...1) ...........................................256
12.8.9 Register TOM[i]_CH[x]_CTRL ..................................................................257
12.8.10 Register TOM[i]_CH[x]_CN0 ....................................................................261
12.8.11 Register TOM[i]_CH[x]_CM0 ....................................................................261
12.8.12 Register TOM[i]_CH[x]_SR0 ....................................................................262
12.8.13 Register TOM[i]_CH[x]_CM1 ....................................................................262
12.8.14 Register TOM[i]_CH[x]_SR1 ....................................................................263
12.8.15 Register TOM[i]_CH[x]_STAT ..................................................................263
12.8.16 Register TOM[i]_CH[x]_IRQ_NOTIFY ......................................................264
12.8.17 Register TOM[i]_CH[x]_IRQ_EN ..............................................................264
12.8.18 Register TOM[i]_CH[x]_IRQ_FORCINT ...................................................265
12.8.19 Register TOM[i]_CH[x]_IRQ_MODE ........................................................266
13 ARU-connected Timer Output Module (ATOM) ......................................267
13.1 Overview .....................................................................................................267
13.1.1 ATOM block diagram ................................................................................267
13.1.2 ATOM Global Control (AGC) ....................................................................269
13.1.3 ATOM Channel Mode Overview ...............................................................272
13.2 ATOM Channel Architecture .......................................................................273
13.2.1 ATOM channel architecture ......................................................................273
13.2.2 ARU Communication Interface .................................................................274
13.3 ATOM Channel Modes ...............................................................................276
13.3.1 ATOM Signal Output Mode Immediate (SOMI) ........................................277
13.3.2 ATOM Signal Output Mode Compare (SOMC) ........................................279
13.3.3 ATOM Signal Output Mode PWM (SOMP) ...............................................302
13.3.4 ATOM Signal Output Mode Serial (SOMS) ..............................................318
13.3.5 ATOM Signal Output Mode Buffered Compare(SOMB) ...........................326
13.4 ATOM Interrupt Signals ..............................................................................335
13.5 ATOM Register Overview ...........................................................................335
13.6 ATOM Register Description ........................................................................336
13.6.1 Register ATOM[i]_AGC_GLB_CTRL ........................................................336
13.6.2 Register ATOM[i]_AGC_ENDIS_CTRL ....................................................338
13.6.3 Register ATOM[i]_AGC_ENDIS_STAT ....................................................339
13.6.4 Register ATOM[i]_AGC_ACT_TB ............................................................340
13.6.5 Register ATOM[i]_AGC_OUTEN_CTRL ..................................................341
13.6.6 Register ATOM[i]_AGC_OUTEN_STAT ..................................................342
13.6.7 Register ATOM[i]_AGC_FUPD_CTRL .....................................................343
13.6.8 Register ATOM[i]_AGC_INT_TRIG ..........................................................344
13.6.9 Register ATOM[i]_CH[x]_CTRL ...............................................................345
13.6.10 Register ATOM[i]_CH[x]_STAT ................................................................351
13.6.11 Register ATOM[i]_CH[x]_RDADDR ..........................................................352
13.6.12 Register ATOM[i]_CH[x]_CN0 ..................................................................353
13.6.13 Register ATOM[i]_CH[x]_CM0 .................................................................353
13.6.14 Register ATOM[i]_CH[x]_SR0 ..................................................................354
13.6.15 Register ATOM[i]_CH[x]_CM1 .................................................................354
13.6.16 Register ATOM[i]_CH[x]_SR1 ..................................................................355
13.6.17 Register ATOM[i]_CH[x]_IRQ_NOTIFY ...................................................356
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13.6.18 Register ATOM[i]_CH[x]_IRQ_EN............................................................356
13.6.19 Register ATOM[i]_CH[x]_IRQ_FORCINT .................................................357
13.6.20 Register ATOM[i]_CH[x]_IRQ_MODE ......................................................357
14 Dead Time Module (DTM) .........................................................................359
14.1 Overview .....................................................................................................359
14.1.1 DTM overview ..........................................................................................359
14.1.2 Connections of TOM and ATOM to DTM inputs DTM_IN[y]/DTM_IN[y]_T 360
14.1.3 Connections of TIM to DTM inputs TIM_CH_IN0/TIM_CH_IN1 for TIM_SEL=0 .............................................................................................................361
14.1.4 Connections of TIM to DTM inputs TIM_CH_IN0/TIM_CH_IN1 for TIM_SEL=1 .............................................................................................................361
14.1.5 Connections between DTM instances ......................................................362
14.2 DTM Channel ..............................................................................................363
14.2.1 DTM channel overview .............................................................................363
14.2.2 Standard dead time generation ................................................................364
14.2.3 Cross channel dead time ..........................................................................366
14.3 Phase Shift Control Unit ..............................................................................367
14.3.1 Phase Shift Unit overview ........................................................................367
14.3.2 Example wave of phase shift on channel 1 ..............................................368
14.4 Multiple output signal combination ..............................................................369
14.4.1 Combination of input signal TIM_CH_IN/AUX_IN with TOM/ATOM signal 369
14.4.2 Combination of multiple TOM/ATOM output signals .................................370
14.4.3 Pulse generation on edge ........................................................................371
14.5 Synchronous update of channel control register 2 ......................................371
14.5.1 Synchronous update mechanism of register DTM[i]_CH_CTRL2 ............372
14.6 DTM output shut off ....................................................................................372
14.7 DTM connections on GTM-IP top level .......................................................373
14.7.1 DTM behavior after reset ..........................................................................373
14.7.2 (A)TOM output signal routing in case of no DTM instance available ........374
14.8 Configuration Register Overview ................................................................374
14.9 Configuration Register Description .............................................................374
14.9.1 Register CDTM[i]_DTM[j]_CTRL (j:0...5) ..................................................375
14.9.2 Register CDTM[i]_DTM[j]_CH_CTRL1 (j:0...5) .........................................376
14.9.3 Register CDTM[i]_DTM[j]_CH_CTRL2 (j:0...5) .........................................379
14.9.4 Register CDTM[i]_DTM[j]_CH_CTRL2_SR (j:0...5) ..................................381
14.9.5 Register CDTM[i]_DTM[j]_CH_CTRL3 (j:0...5) .........................................384
14.9.6 Register CDTM[i]_DTM[j]_PS_CTRL (j:0...5) ...........................................385
14.9.7 Register CDTM[i]_DTM[j]_CH[z]_DTV (j:0...5, z:0...3) .............................387
14.9.8 Register CDTM[i]_DTM[j]_CH_SR (j:0...5) ...............................................387
15 Multi Channel Sequencer (MCS) ..............................................................389
15.1 Overview .....................................................................................................389
15.1.1 Generic Design Parameters .....................................................................389
15.2 Architecture .................................................................................................390
15.2.1 MCS Architecture .....................................................................................390
15.3 Scheduling ..................................................................................................392
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15.3.1 Round Robin Scheduling ..........................................................................393
15.3.2 Accelerated Scheduling ............................................................................394
15.3.3 Single Prioritization Scheduling ................................................................398
15.3.4 Multiple Prioritization Scheduling..............................................................398
15.4 Memory Organization ..................................................................................399
15.5 AEI Bus Master Interface ............................................................................400
15.6 ADC Interface .............................................................................................401
15.6.1 Basic ADC Functions ...............................................................................401
15.7 Instruction Set .............................................................................................402
15.7.1 Instruction Set Summary (part 1)..............................................................404
15.7.2 Instruction Set Summary (part 2)..............................................................405
15.7.3 Instruction Set Summary (part 3)..............................................................406
15.7.4 Instruction Codes (part 1) .........................................................................407
15.7.5 Instruction Codes (part 2) .........................................................................408
15.7.6 MOVL Instruction......................................................................................410
15.7.7 MOV Instruction........................................................................................410
15.7.8 MRD Instruction........................................................................................410
15.7.9 MWR Instruction .......................................................................................411
15.7.10 MWRL Instruction .....................................................................................411
15.7.11 MRDI Instruction.......................................................................................411
15.7.12 MRDIO Instruction ....................................................................................412
15.7.13 MWRI Instruction ......................................................................................413
15.7.14 MWRIO Instruction ...................................................................................413
15.7.15 MWRIL Instruction ....................................................................................414
15.7.16 POP Instruction ........................................................................................414
15.7.17 PUSH Instruction ......................................................................................415
15.7.18 ARD Instruction ........................................................................................415
15.7.19 ARDI Instruction .......................................................................................416
15.7.20 AWR Instruction .......................................................................................417
15.7.21 AWRI Instruction ......................................................................................417
15.7.22 NARD Instruction......................................................................................418
15.7.23 NARDI Instruction .....................................................................................419
15.7.24 BRD Instruction ........................................................................................420
15.7.25 BWR Instruction .......................................................................................420
15.7.26 BRDI Instruction .......................................................................................421
15.7.27 BWRI Instruction ......................................................................................421
15.7.28 ADDL Instruction ......................................................................................422
15.7.29 ADD Instruction ........................................................................................422
15.7.30 ADDC Instruction......................................................................................423
15.7.31 SUBL Instruction ......................................................................................424
15.7.32 SUB Instruction ........................................................................................424
15.7.33 SUBC Instruction ......................................................................................425
15.7.34 NEG Instruction ........................................................................................426
15.7.35 ANDL Instruction ......................................................................................426
15.7.36 AND Instruction ........................................................................................427
15.7.37 ORL Instruction ........................................................................................427
15.7.38 OR Instruction ..........................................................................................427
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15.7.39 XORL Instruction ......................................................................................428
15.7.40 XOR Instruction ........................................................................................428
15.7.41 SHR Instruction ........................................................................................428
15.7.42 SHL Instruction .........................................................................................429
15.7.43 ASRU Instruction ......................................................................................429
15.7.44 ASRS Instruction ......................................................................................430
15.7.45 ASL Instruction .........................................................................................430
15.7.46 MULU Instruction......................................................................................431
15.7.47 MULS Instruction ......................................................................................431
15.7.48 DIVU Instruction .......................................................................................432
15.7.49 DIVS Instruction .......................................................................................433
15.7.50 MINU Instruction.......................................................................................434
15.7.51 MINS Instruction .......................................................................................434
15.7.52 MAXU Instruction .....................................................................................434
15.7.53 MAXS Instruction......................................................................................435
15.7.54 ATUL Instruction.......................................................................................435
15.7.55 ATU Instruction.........................................................................................435
15.7.56 ATSL Instruction .......................................................................................436
15.7.57 ATS Instruction .........................................................................................436
15.7.58 BTL Instruction .........................................................................................437
15.7.59 BT Instruction ...........................................................................................437
15.7.60 SETB Instruction ......................................................................................437
15.7.61 CLRB Instruction ......................................................................................438
15.7.62 XCHB Instruction ......................................................................................438
15.7.63 JMP Instruction.........................................................................................439
15.7.64 JBS Instruction .........................................................................................439
15.7.65 JBC Instruction .........................................................................................439
15.7.66 CALL Instruction .......................................................................................440
15.7.67 RET Instruction.........................................................................................440
15.7.68 JMPI Instruction........................................................................................441
15.7.69 JBSI Instruction ........................................................................................441
15.7.70 JBCI Instruction ........................................................................................442
15.7.71 CALLI Instruction ......................................................................................442
15.7.72 WURM Instruction ....................................................................................443
15.7.73 WURMX Instruction ..................................................................................444
15.7.74 WURCX Instruction ..................................................................................445
15.7.75 WUCE Instruction .....................................................................................445
15.7.76 NOP Instruction ........................................................................................446
15.8 MCS Internal Register Overview .................................................................447
15.8.1 MCS Internal Register Overview ..............................................................447
15.9 MCS Internal Register Description ..............................................................447
15.9.1 Register R[y] (y:0...7) ...............................................................................448
15.9.2 Register RS[y] (y:0...7) .............................................................................448
15.9.3 Register STA ............................................................................................449
15.9.4 Register ACB ...........................................................................................452
15.9.5 Register CTRG .........................................................................................453
15.9.6 Register STRG .........................................................................................458
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15.9.7 Register TBU_TS0 ...................................................................................460
15.9.8 Register TBU_TS1 ...................................................................................460
15.9.9 Register TBU_TS2 ...................................................................................461
15.9.10 Register MHB ...........................................................................................461
15.9.11 Register GMI0 ..........................................................................................461
15.9.12 Register GMI1 ..........................................................................................466
15.9.13 Register DSTA .........................................................................................471
15.9.14 Register DSTAX .......................................................................................473
15.10 MCS Configuration Register Overview .......................................................475
15.10.1 MCS Configuration Register Overview .....................................................475
15.11 MCS Configuration Register Description ....................................................475
15.11.1 Register MCS[i]_CH[x]_CTRL ..................................................................476
15.11.2 Register MCS[i]_CH[x]_PC ......................................................................477
15.11.3 Register MCS[i]_CH[x]_R[y] (y:0...7) ........................................................478
15.11.4 Register MCS[i]_CH[x]_ACB ....................................................................478
15.11.5 Register MCS[i]_CH[x]_MHB ...................................................................479
15.11.6 Register MCS[i]_CH[x]_IRQ_NOTIFY ......................................................479
15.11.7 Register MCS[i]_CH[x]_IRQ_EN ..............................................................480
15.11.8 Register MCS[i]_CH[x]_IRQ_FORCINT ...................................................481
15.11.9 Register MCS[i]_CH[x]_IRQ_MODE ........................................................481
15.11.10 Register MCS[i]_CH[x]_EIRQ_EN............................................................482
15.11.11 Register MCS[i]_CTRL_STAT ..................................................................483
15.11.12 Register MCS[i]_REG_PROT ..................................................................485
15.11.13 Register MCS[i]_CTRG ............................................................................487
15.11.14 Register MCS[i]_STRG ............................................................................491
15.11.15 Register MCS[i]_RESET ..........................................................................493
15.11.16 Register MCS[i]_CAT ...............................................................................495
15.11.17 Register MCS[i]_CWT ..............................................................................496
15.11.18 Register MCS[i]_ERR ...............................................................................497
15.11.19 Memory MCS[i]_MEM ..............................................................................498
16 Memory Configuration (MCFG) ................................................................499
16.1 Overview .....................................................................................................499
16.1.1 Memory Layout Configurations (ERM = 0) ..............................................500
16.1.2 Memory Layout Parameters (ERM = 0) ....................................................501
16.1.3 Memory Layout Configurations (ERM = 1) ..............................................502
16.1.4 Memory Layout Parameters (ERM = 1) ...................................................502
16.2 MCFG Configuration Registers Overview ...................................................503
16.2.1 MCFG Configuration Registers Overview Table ......................................503
16.3 MCFG Configuration Registers ...................................................................503
16.3.1 Register MCFG_CTRL .............................................................................503
17 TIM0 Input Mapping Module (MAP) .........................................................506
17.1 Overview .....................................................................................................506
17.1.1 MAP Submodule architecture ...................................................................506
17.2 TIM Signal Preprocessing (TSPP) ..............................................................507
17.2.1 TIM Signal Preprocessing (TSPP) subunit architecture ...........................507
17.2.2 Bit Stream Combination ...........................................................................508
17.3 MAP Register overview ...............................................................................509
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17.4 MAP Register description ...........................................................................509
17.4.1 Register MAP_CTRL ................................................................................509
18 Digital PLL Module (DPLL) .......................................................................512
18.1 Overview .....................................................................................................512
18.2 Requirements and demarcation ..................................................................512
18.3 Input signal courses ....................................................................................514
18.3.1 Trigger and State Input Signal ..................................................................514
18.4 Block and interface description ...................................................................514
18.4.1 DPLL Block Diagram ................................................................................514
18.4.2 Interface description of DPLL ...................................................................515
18.5 DPLL Architecture .......................................................................................520
18.5.1 Purpose of the module .............................................................................520
18.5.2 Explanation of the prediction methodology ...............................................520
18.5.3 Clock topology ..........................................................................................520
18.5.4 Clock generation ......................................................................................521
18.5.5 Typical frequencies ..................................................................................521
18.5.6 Time stamps and systematic corrections .................................................521
18.5.7 DPLL Architecture overview .....................................................................523
18.5.8 DPLL Architecture description ..................................................................525
18.5.9 Block diagrams of time stamp processing. ...............................................527
18.5.10 Register and RAM address overview .......................................................528
18.5.11 Software reset and DPLL deactivation .....................................................534
18.6 Prediction of the current increment duration ...............................................534
18.6.1 The use of increments in the past ............................................................535
18.6.2 Increment prediction in Normal Mode and for first PMSM forwards .........535
18.6.3 Increment prediction in Emergency Mode and for second PMSM forwards 539
18.6.4 Increment prediction in Normal Mode and for first PMSM backwards ......542
18.6.5 Increment prediction in Emergency Mode and for second PMSM backwards 544
18.7 Calculations for actions ...............................................................................546
18.7.1 Action calculations for TRIGGER forwards ..............................................547
18.7.2 Action calculations for TRIGGER backwards ...........................................549
18.7.3 Action calculations for STATE forwards ...................................................551
18.7.4 Action calculations for STATE backwards ................................................553
18.7.5 Update of RAM in Normal and Emergency Mode.....................................555
18.7.6 Time and position stamps for actions in Normal Mode .............................558
18.7.7 The use of the RAM .................................................................................561
18.7.8 Time and position stamps for actions in Emergency Mode ......................561
18.8 Signal processing ........................................................................................564
18.8.1 Time stamp processing ............................................................................564
18.8.2 Count and compare unit ...........................................................................565
18.8.3 Sub pulse generation for SMC=0 .............................................................565
18.8.4 Sub pulse generation for SMC=1 .............................................................570
18.8.5 Calculation of the Accurate Position Values .............................................573
18.8.6 Scheduling of the Calculation ...................................................................574
18.9 DPLL Interrupt signals ................................................................................596
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18.9.1 DPLL Interrupt signals ..............................................................................596
18.10 MCS to DPLL interface ...............................................................................597
18.10.1 Architecture and organization ...................................................................597
18.10.2 General functionality .................................................................................597
18.10.3 MCS to DPLL Register overview ..............................................................598
18.11 DPLL Register Memory overview ................................................................599
18.11.1 Available DPLL register overview .............................................................599
18.11.2 RAM Region 1a map description ..............................................................602
18.11.3 RAM Region 1b map description ..............................................................602
18.11.4 RAM Region 1c map description ..............................................................605
18.11.5 Register Region EXT description .............................................................605
18.11.6 RAM Region 2 map description ................................................................607
18.12 DPLL Register and Memory description .....................................................608
18.12.1 Register DPLL_CTRL_0 ...........................................................................608
18.12.2 Register DPLL_CTRL_1 ...........................................................................611
18.12.3 Register DPLL_CTRL_2 ...........................................................................617
18.12.4 Register DPLL_CTRL_3 ...........................................................................618
18.12.5 Register DPLL_CTRL_4 ...........................................................................620
18.12.6 Register DPLL_CTRL_5 ...........................................................................621
18.12.7 Register DPLL_ACT_STA ........................................................................623
18.12.8 Register DPLL_OSW ...............................................................................623
18.12.9 Register DPLL_AOSV_2 ..........................................................................625
18.12.10 Register DPLL_APT .................................................................................627
18.12.11 Register DPLL_APS .................................................................................628
18.12.12 Register DPLL_APT_2C ..........................................................................630
18.12.13 Register DPLL_APS_1C3 ........................................................................631
18.12.14 Register DPLL_NUTC ..............................................................................632
18.12.15 Register DPLL_NUSC ..............................................................................634
18.12.16 Register DPLL_NTI_CNT .........................................................................636
18.12.17 Register DPLL_IRQ_NOTIFY ..................................................................637
18.12.18 Register DPLL_IRQ_EN ...........................................................................640
18.12.19 Register DPLL_IRQ_FORCINT ................................................................644
18.12.20 Register DPLL_IRQ_MODE .....................................................................645
18.12.21 Register DPLL_EIRQ_EN ........................................................................646
18.12.22 Register DPLL_INC_CNT1 ......................................................................649
18.12.23 Register DPLL_INC_CNT2 ......................................................................650
18.12.24 Register DPLL_APT_SYNC .....................................................................651
18.12.25 Register DPLL_APS_SYNC .....................................................................653
18.12.26 Register DPLL_TBU_TS0_T ....................................................................654
18.12.27 Register DPLL_TBU_TS0_S ....................................................................655
18.12.28 Register DPLL_ADD_IN_LD1 ..................................................................655
18.12.29 Register DPLL_ADD_IN_LD2 ..................................................................657
18.12.30 Register DPLL_STATUS ..........................................................................658
18.12.31 Register DPLL_ID_PMTR_[z] (z:0...NOAC-1) ..........................................663
18.12.32 Register DPLL_CTRL_0_SHADOW_TRIGGER ......................................664
18.12.33 Register DPLL_CTRL_0_SHADOW_STATE ...........................................664
18.12.34 Register DPLL_CTRL_1_SHADOW_TRIGGER ......................................665
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18.12.35 Register DPLL_CTRL_1_SHADOW_STATE ...........................................666
18.12.36 Register DPLL_RAM_INI .........................................................................667
18.12.37 Memory DPLL_TS_T ................................................................................668
18.12.38 Memory DPLL_TS_T_OLD ......................................................................668
18.12.39 Memory DPLL_FTV_T .............................................................................669
18.12.40 Memory DPLL_TS_S ...............................................................................670
18.12.41 Memory DPLL_TS_S_OLD ......................................................................670
18.12.42 Memory DPLL_FTV_S .............................................................................671
18.12.43 Memory DPLL_THMI ................................................................................671
18.12.44 Memory DPLL_THMA ..............................................................................672
18.12.45 Memory DPLL_THVAL .............................................................................673
18.12.46 Memory DPLL_TOV .................................................................................673
18.12.47 Memory DPLL_TOV_S .............................................................................674
18.12.48 Memory DPLL_ADD_IN_CAL1 ................................................................675
18.12.49 Memory DPLL_ADD_IN_CAL2 ................................................................676
18.12.50 Memory DPLL_MPVAL1 ..........................................................................677
18.12.51 Memory DPLL_MPVAL2 ..........................................................................677
18.12.52 Memory DPLL_NMB_T_TAR ...................................................................678
18.12.53 Memory DPLL_NMB_T_TAR_OLD ..........................................................679
18.12.54 Memory DPLL_NMB_S_TAR ...................................................................680
18.12.55 Memory DPLL_NMB_S_TAR_OLD..........................................................680
18.12.56 Memory DPLL_RCDT_TX ........................................................................681
18.12.57 Memory DPLL_RCDT_SX ........................................................................682
18.12.58 Memory DPLL_RCDT_TX_NOM ..............................................................682
18.12.59 Memory DPLL_RCDT_SX_NOM .............................................................683
18.12.60 Memory DPLL_RDT_T_ACT ....................................................................683
18.12.61 Memory DPLL_RDT_S_ACT ...................................................................684
18.12.62 Memory DPLL_DT_T_ACT ......................................................................685
18.12.63 Memory DPLL_DT_S_ACT ......................................................................685
18.12.64 Memory DPLL_EDT_T .............................................................................686
18.12.65 Memory DPLL_MEDT_T ..........................................................................687
18.12.66 Memory DPLL_EDT_S .............................................................................687
18.12.67 Memory DPLL_MEDT_S ..........................................................................688
18.12.68 Memory DPLL_CDT_TX ..........................................................................688
18.12.69 Memory DPLL_CDT_SX ..........................................................................689
18.12.70 Memory DPLL_CDT_TX_NOM ................................................................689
18.12.71 Memory DPLL_CDT_SX_NOM ................................................................690
18.12.72 Memory DPLL_TLR ..................................................................................691
18.12.73 Memory DPLL_SLR .................................................................................691
18.12.74 Memory DPLL_PDT_[z] (z:0...NOAC-1) ...................................................692
18.12.75 Memory DPLL_MLS1 ...............................................................................692
18.12.76 Memory DPLL_MLS2 ...............................................................................693
18.12.77 Memory DPLL_CNT_NUM_1 ...................................................................694
18.12.78 Memory DPLL_CNT_NUM_2 ...................................................................694
18.12.79 Memory DPLL_PVT .................................................................................695
18.12.80 Memory DPLL_PSTC ...............................................................................696
18.12.81 Memory DPLL_PSSC ...............................................................................697
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18.12.82 Memory DPLL_PSTM ..............................................................................697
18.12.83 Memory DPLL_PSTM_OLD .....................................................................698
18.12.84 Memory DPLL_PSSM ..............................................................................699
18.12.85 Memory DPLL_PSSM_OLD .....................................................................699
18.12.86 Memory DPLL_NMB_T ............................................................................700
18.12.87 Memory DPLL_NMB_S ............................................................................701
18.12.88 Memory DPLL_RDT_S[i] ..........................................................................701
18.12.89 Memory DPLL_TSF_S[i] ..........................................................................702
18.12.90 Memory DPLL_ADT_S[i] ..........................................................................702
18.12.91 Memory DPLL_DT_S[i] ............................................................................703
18.12.92 Register DPLL_TSAC[z] z:(0...NOAC-1) ..................................................704
18.12.93 Register DPLL_PSAC[z] z:(0...NOAC-1) ..................................................705
18.12.94 Register DPLL_ACB_[z] ...........................................................................705
18.12.95 Register DPLL_CTRL_11 .........................................................................708
18.12.96 Register DPLL_THVAL2 ..........................................................................715
18.12.97 Register DPLL_TIDEL ..............................................................................716
18.12.98 Register DPLL_SIDEL ..............................................................................717
18.12.99 Register DPLL_CTN_MIN ........................................................................717
18.12.100 Register DPLL_CTN_MAX .................................................................718
18.12.101 Register DPLL_CSN_MIN ..................................................................719
18.12.102 Register DPLL_CSN_MAX .................................................................719
18.12.103 Register DPLL_STA ...........................................................................720
18.12.104 Register DPLL_INCF1_OFFSET ........................................................724
18.12.105 Register DPLL_INCF2_OFFSET ........................................................724
18.12.106 Register DPLL_DT_T_START ............................................................725
18.12.107 Register DPLL_DT_S_START ............................................................726
18.12.108 Register DPLL_STA_MASK ...............................................................726
18.12.109 Register DPLL_STA_FLAG ................................................................727
18.12.110 Register DPLL_INC_CNT1_MASK .....................................................729
18.12.111 Register DPLL_INC_CNT2_MASK .....................................................729
18.12.112 Register DPLL_NUSC_EXT1 .............................................................730
18.12.113 Register DPLL_NUSC_EXT2 .............................................................731
18.12.114 Register DPLL_APS_EXT ..................................................................733
18.12.115 Register DPLL_APS_1C3_EXT ..........................................................735
18.12.116 Register DPLL_APS_SYNC_EXT ......................................................736
18.12.117 Register DPLL_CTRL_EXT ................................................................737
18.12.118 Memory DPLL_RR1A .........................................................................738
18.12.119 Memory DPLL_RR2 ............................................................................739
18.13 DPLL RAM Region 1a value description .....................................................739
18.13.1 Memory DPLL_PSA[i] ..............................................................................739
18.13.2 Memory DPLL_DLA[i] ...............................................................................740
18.13.3 Memory DPLL_NA[i] .................................................................................741
18.13.4 Memory DPLL_DTA[i] ..............................................................................741
18.14 DPLL RAM Region 2 value description .......................................................742
18.14.1 Memory DPLL_RDT_T[i] ..........................................................................742
18.14.2 Memory DPLL_TSF_T[i] ...........................................................................743
18.14.3 Memory DPLL_ADT_T[i] ..........................................................................744
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18.14.4 Memory DPLL_DT_T[i] .............................................................................745
18.15 MCS to DPLL Register description .............................................................745
18.15.1 Register MCS2DPLL_DEB0 .....................................................................746
18.15.2 Register MCS2DPLL_DEB1 .....................................................................746
18.15.3 Register MCS2DPLL_DEB2 .....................................................................747
18.15.4 Register MCS2DPLL_DEB3 .....................................................................748
18.15.5 Register MCS2DPLL_DEB4 .....................................................................749
18.15.6 Register MCS2DPLL_DEB5 .....................................................................749
18.15.7 Register MCS2DPLL_DEB6 .....................................................................750
18.15.8 Register MCS2DPLL_DEB7 .....................................................................751
18.15.9 Register MCS2DPLL_DEB8 .....................................................................752
18.15.10 Register MCS2DPLL_DEB9 .....................................................................752
18.15.11 Register MCS2DPLL_DEB10 ...................................................................753
18.15.12 Register MCS2DPLL_DEB11 ...................................................................754
18.15.13 Register MCS2DPLL_DEB12 ...................................................................754
18.15.14 Register MCS2DPLL_DEB13 ...................................................................755
18.15.15 Register MCS2DPLL_DEB14 ...................................................................756
18.15.16 Register MCS2DPLL_DEB15 ...................................................................757
19 Sensor Pattern Evaluation (SPE) .............................................................758
19.1 Overview .....................................................................................................758
19.1.1 SPE Submodule integration concept into GTM-IP ...................................758
19.1.2 SPE Sample input pattern for TIM[i]_CH[x,y,z](48) ..................................760
19.2 SPE Submodule description .......................................................................761
19.2.1 SPE to TOM Connections ........................................................................761
19.2.2 SPE Submodule architecture ...................................................................763
19.2.3 SPE forward - backward commanding .....................................................764
19.2.4 SPE[i]_IN_PAT register representation ....................................................765
19.2.5 SPE Revolution detection .........................................................................767
19.3 SPE Interrupt signals ..................................................................................767
19.4 SPE Register overview ...............................................................................767
19.5 SPE Register description ............................................................................768
19.5.1 Register SPE[i]_CTRL_STAT ..................................................................768
19.5.2 Register SPE[i]_PAT ................................................................................770
19.5.3 Register SPE[i]_OUT_PAT[z] (z:0...7) ......................................................772
19.5.4 Register SPE[i]_OUT_CTRL ....................................................................772
19.5.5 Register SPE[i]_REV_CNT ......................................................................773
19.5.6 Register SPE[i]_REV_CMP ......................................................................774
19.5.7 Register SPE[i]_IRQ_NOTIFY .................................................................774
19.5.8 Register SPE[i]_IRQ_EN ..........................................................................775
19.5.9 Register SPE[i]_IRQ_FORCINT ...............................................................776
19.5.10 Register SPE[i]_IRQ_MODE ....................................................................777
19.5.11 Register SPE[i]_EIRQ_EN .......................................................................777
19.5.12 Register SPE[i]_CTRL_STAT2 ................................................................778
19.5.13 Register SPE[i]_CMD ...............................................................................779
20 Interrupt Concentrator Module (ICM) ......................................................780
20.1 Overview .....................................................................................................780
20.2 Bundling ......................................................................................................780
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20.2.1 GTM Infrastructure Interrupt Bundling ......................................................780
20.2.2 DPLL Interrupt Bundling ...........................................................................781
20.2.3 TIM Interrupt Bundling ..............................................................................781
20.2.4 MCS Interrupt Bundling ............................................................................781
20.2.5 TOM and ATOM Interrupt Bundling ..........................................................782
20.2.6 Module Error Interrupt Bundling ...............................................................783
20.2.7 FIFO Channel Error Interrupt Bundling .....................................................783
20.2.8 TIM Channel Error Interrupt Bundling .......................................................784
20.2.9 MCS Channel Error Interrupt Bundling .....................................................784
20.2.10 Error Interrupt Cluster Bundling ................................................................784
20.3 ICM Interrupt Signals ..................................................................................784
20.4 ICM Configuration Register Overview .........................................................786
20.4.1 ICM Configuration Register Overview Table ............................................786
20.5 ICM Configuration Register Description ......................................................787
20.5.1 Register ICM_IRQG_0 .............................................................................788
20.5.2 Register ICM_IRQG_1 .............................................................................789
20.5.3 Register ICM_IRQG_2 .............................................................................791
20.5.4 Register ICM_IRQG_3 .............................................................................792
20.5.5 Register ICM_IRQG_4 .............................................................................793
20.5.6 Register ICM_IRQG_5 .............................................................................795
20.5.7 Register ICM_IRQG_6 ...........................................................