High speed digital systems laboratory
Part A - PresentationPart A - Presentation
Project Name: Serial Communication Analyzer
Presenter Name: Igal Kogan
Alexander Rekhelis
Instructor: Hen Broodney
Semester: Winter-Spring 2001/2
High speed digital systems laboratory
Project GoalsProject Goals
Implementation of testing and debugging device for serial communication protocol RS-232 and DSP protocol McBSP.
Both protocols are encoded and/or decoded by Altera FPGA. Also PCI Interface protocol, that implemented in PCI MegaCore, is managed by Altera FPGA.
The design will base on Altera Flex PCI Development Kit and the external devices will connect through bridges that are specially designed as RS-232 and McBSP protocols buffers.
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AbstractAbstract
The device will manage the data in several ways:
1) As data buffer it will transfer the data from the input device to the output device.
2) As communication analyzer it will read the data from input, send it to PC through PCI Bus for
processing, and according to user commands will send the updated data to output.
Note: Since the communication is bi-directional, input and output devices can be switched constantly.
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Abstract (cont.)Abstract (cont.)
RS-232 RS-232
McBSP McBSP
Serial Communication
Analyzer
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Highlights of RS232 protocolHighlights of RS232 protocol
RS-232 is an electrical interface standard between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) such as modems, PALM, mouse and so.
RS-232 is used for asynchronous data transfer as well as synchronous links.
It appears under different incarnations such as RS-232C, RS-232D, V.24, V.28 or V.10 but essentially all these interfaces are interoperable.
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PC Com Port - EIA-574 RS-232 pin out DB-9 pin used for Asynchronous Data
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One byte of asynchronous data
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Highlights of McBSP protocolHighlights of McBSP protocol
– Full-duplex communication– Double-buffered data registers, which allow a continuous
data stream– Independent framing and clocking for receive and transmit– Direct interface to industry-standard analog interface chips
(AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
– External shift clock or an internal, programmable frequency shift clock for data transfer
– Autobuffering capability through the 5-channel DMA
controller.
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McBSP Interface SignalsMcBSP Interface Signals
Pin I/O/Z† DescriptionCLKR I/O/Z Receive clock
CLKX I/O/Z Transmit clock
CLKS I External clock
DR I Received serial data
DX O/Z Transmitted serial data
FSR I/O/Z Receive frame synchronization
FSX I/O/Z Transmit frame synchronization
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PC
I B
usL
ocal Bus
.Altera ליחידות לוגיות, כפי שמומש ע”י חברת PCI Coreחלוקת ה-
.Control Logic Block לבין PCI Busתפקידו למנשק בין ה-
PCI CorePCI Core
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Software (Hardware)Software (Hardware)
We are currently focused on RS232 protocol implementation.
The communication can be handled at: 1200, 2400, 4800, 9600,
19200, 38400, 57600, 115200 baud rate.
The communication rate, condition (with or without
handshake) analyzing and test options will be determined by
the GUI through the WinDriver.
Control Logic block will provide the proper interactions between PCI Core and RS232 or McBSP communication blocks (by local bus).
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HardwareHardware
All hardware will be implemented on Altera FLEX PCI Development Kit.
One channel for RS-232 communication is already placed on the kit. The implementation of the second RS-232 communication channel that connects to the Altera on the kit and also the implementation of the connections between two McBSP channels on DSP board to the Altera on the kit board are currently in progress.
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Altera PCI Development Board
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Technical Specification
1) Interface voltages:
1.1) RS-232 – ‘0’ -> +3v : +15v
‘1’ -> -3v : -15v
1.2) McBSP – ‘0’ -> 0v
‘1’ -> +3.3v
2) Distances – 0m : 2m
3) Communication rates :
3.1) RS-232 – 1200,2400,4800,9600,19200,38400,57600,115200
3.2) McBSP – 33Mbps (pci bus clock)
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Technical Specification (cont.)
4) RS-232 interface working with handshake or without handshake.
5) Loopback connectivity test.
6) Communication reliability tests:
6.1) Parity checks.
6.2) CRC tests without acknowledge .
6.3) CRC tests with acknowledge.
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RS-232 pin out (addition)RS-232 pin out (addition)
TX
U2
MAX208
642217
73
2316
101213141115
5181921
212420
R1OUTR2OUTR3OUTR4OUT
R1INR2INR3INR4IN
C1+C1-C2+C2-V+V-
T1INT2INT3INT4IN
T1OUTT2OUTT3OUTT4OUT
RTSSignals to Altera
C10.1uF
C40.1uF
C50.1uF
RS232_TX_1
C60.1uF
DTR
C30.1uF
RS232_CTS_2
RX
U1
MAX208
642217
73
2316
101213141115
5181921
212420
R1OUTR2OUTR3OUTR4OUT
R1INR2INR3INR4IN
C1+C1-C2+C2-V+V-
T1INT2INT3INT4IN
T1OUTT2OUTT3OUTT4OUT
9-VCC
RS232_CTS_1
Signals to Altera
RS232_DTR_2
CTS
C70.1uF
RS232_RTS_2
RS232_TX_2
RS232_RX_1
P1CON DB9 MALE
5 9 4 8 3 7 2 6 1
RX
8-GND
RI
RTS
DTR
RS232_CD_2
RS232_CD_1
9-VCC
RS232_RTS_1
Signals to Altera
CTS
8-GND
CD
C80.1uF
C20.1uF
RS232_DTR_1
P2CON DB9 MALE
5 9 4 8 3 7 2 6 1
CD
RS232_RX_2
RI
RS232_RI_1Signals to Altera
RS232_RI_2
TX
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McBSP pin out (addition)McBSP pin out (addition)
J4
CONNECTOR EDGE 80
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
FSR1
DX0
CLKX1
DR0
CLKR1McBSP 1
(to Altera)
FSX0
(to Altera)
FSR0
DX1
J3
CONNECTOR EDGE 80
123456789
1011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
DSP BOARD
McBSP 0
ALTERA side DSP side
CLKR0
CLKX0
DR1
FSX1
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System Block DiagramSystem Block DiagramAltera Flex
PCI Development
Kit
PCI
RS-232 Communication
Device
McBSP Communication
Device
RS-232 Communication
Device
McBSP Communication
Device
WinDriver
GUI
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System modules diagram (FPGA)System modules diagram (FPGA)
RS-232
Protocol
RS-232
Protocol
McBSP
Protocol
McBSP
Protocol
Control
Logic
PCI
MegaCore
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FPGA block diagramFPGA block diagram
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FPGA block diagramFPGA block diagram
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FPGA block diagramFPGA block diagram
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FPGA block diagramFPGA block diagram
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RS-232 simulationRS-232 simulation
• Design with HDL Designer
• Simulation with Modelsim
• Synthesis with Leonardo Spectrum
• P & R with MaxPlusII
Hardware Development ToolsHardware Development ToolsHigh speed digital systems laboratory
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R E L I A B I L I T Y
T E S T S
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Reliability Tests
1) Checking our side – this is check for our hardware
Serial Communication
Analyzer
Local loopback for
all interfaces
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Example – RS-232 loopback connections
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Example – McBSP loopback connections
clkx
clkrdx
drfsx
fsr
Loopback
connection
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Reliability Tests (cont.)
2) Communication device closing loopback – this test checking all hardware.
Serial Communication
Analyzer
Communication
Device
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Reliability Tests (cont.)
3) Analyzer closing loopback – this is good visual test for all our design.
Serial Communication
Analyzer
Communication
Device
Data Sampled Data
?
==
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Reliability Tests (cont.)
4) Parity check.
Serial Communication
Analyzer
Communication
Device
G U IThe GUI display the
percentage of the success
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Reliability Tests (cont.)
5) CRC – Cyclic Redundancy Check (without ack)
Serial Communication
Analyzer
Communication
Device
G U I
The frame consist of the
10 bytes of data and 1 byte
of the CRC result (sum of bits).
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Reliability Tests (cont.)
6) CRC – Cyclic Redundancy Check (with ack)
Serial Communication
Analyzer
Communication
Device
G U I
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Reliability Tests (cont.)
6) CRC – Cyclic Redundancy Check (with ack)
10 bytes 1 byte 1 byte+ +
D A T A C R C A C K
a) CRC – sum of the data bits from communication device
b) ACK – sum of the data bits that analyzer send
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Testing of the protocols (RS-232)
TerminalOur side
GUI
Palm Example
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Project statusProject status
, שילובו בתכנון ומימוש ממשק PCI Coreהכרת ה-חומרה בינו ובין יתר יחידות התכנון .
McBSP ו- RS-232לימוד ממשקי התקשורת .
.VHDL ב-RS232מימוש פרוטוקול
לימוד הנושא תקשורת אמינה והגדרת כל הבדיקות שיבדקו בתקשורת.
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Part B goals
.PCI Core וחיבורו ל- VHDL ב-McBSPמימוש פרוטוקול
, הגדרה ומימוש ממשק למשתמש לצורך הפעלת GUIכתיבת Windows -ל Driver.הכרטיס
הפעלה מלאה של נתח תקשורת טורית, ביצוע בדיקות תקינות תקשורת על ההתקנים שתומכין בפרוטוקולים נבדקים ,כתיבת
חוברת הדרכה למשתמש.
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ScheduleSchedule
Phase1 – Hardware Design
Phase2 – Software Design
Phase3 – Debug
Oct Nov Dec Jan Feb Mar Apr May Jun Jul
Phase 1Phase 2
Phase 3
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Schedule (cont.)Schedule (cont.)
:לוח זמנים
04/2002 – 06/2002בדיקת ביצועי של הפרוטוקולים : 11/04/2002.'הצגת דו"ח סופי חלק א - 22/04/2002 הלבשת כל מערכת תקשורת על -
PCIcore. 10/05/2002 - Debugging. 01/06/2002 כתיבת - GUI בעזרת WinDriver. 01/07/2002בדיקות אחרונות - .07/2002 .בחינות סוף סמסטר : 08/2002 הצגת חלק ב' - הצגת כרטיס עובד על פי :
כל הדרישות
High speed digital systems laboratory
תודה
רבה
Serial Communication Analyzer