http://photonics.intec.ugent.bePhotonics Research Group
InP Technology on CMOS
D. Van Thourhout
MWP 2006, Grenoble
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
The photonics research group at INTEC/IMEC
P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan…
D. Van Thourhout, P. Bienstman, R. Baets
The Silicon Process division at IMEC Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven,
Rudi De Ruyter, Johan Mees
PICMOS partners J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Lagahe, B. Aspar (TRACIT) (planarization) C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)
European Union, Belgian and Flemish government
Acknowledgements
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Towards CMOS-compatible nanophotonics?Outline
Introduction: why, how, who Basic structurs Fiber-chip coupling Wavelength dependent devices Towards active devices: InP on SOI
Micro-disk lasers Fabry-Perot lasers Detectors
Conclusion
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Electronics vs. PhotonicsElectronics
Single material: Silicon(also provides insulator SiO2)
One platform: CMOS
Large market: highly tuned, mature processes
One main building block:the transistor
Common ITRS roadmap(dominated by a few large companies)
Size: 10nm few um
Photonics Many incompatible materials: GaAs,
InP, Polymers, LiNbO3 ,...
Many processing technologies
Limited market: primitive processes
Many building blocks: resonators, lasers, detectors, ...
Many factions pushing their own solutions
Size: few um few cm
Pentium 4
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Silicon nanophotonics… the solution to all our problems
Transparent at telecom wavelengths (1.3um, 1.55um)
High refractive index contrast ultra-compact circuits
“Compatible” with CMOS-processing Highest quality processes High yield, high repeatability
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Current Fabrication Process
Si-substrate
SiO2
SiPhotoresist Photoresist
AR-coating
wafer Photoresist(UV3)
Bare Soft bake AR coating Illumination(248nm deep UV)
bakePost Development Resist Hardening
Silicon etch Resist strip
SiO2 (1-2um)
Waveguide Definition
Width (500nm) x Height (220nm)
Silicon
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
SOI-nanophotonic wires
Group Date h [nm] w [nm]loss
[dB/cm]BOX [um]
top clad Fab.
IMEC Apr. '04 220 500 2.4 1 no DUV
IBM Today 220 445 2.1 2 no EBeam
Cornell Aug. '03 270 470 5.0 3 no EBeam
NTT Feb. '05 300200
300400
7.82.8
3 yes EBeam
Yokohama Dec. '02 320 400 105.0 1 no EBeam
MIT Dec. '01 200 500 32.0 1 yes G-line
LETI / LPM Apr. '05 300 300 15.0 1 yes DUV
200 500 5.0
Columbia Oct. 03 260 600 110.0 1 yes EBeam
NEC Oct. ‘04 300 300 19.0 1 yes EBeam
Table updated till Sep. ’05 – Lower values (<2dB) reported but waveguide structure unclear (e.g. Luxtera, EPIC network)
2dB/cm 120 dB/cm
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Basic structures
(b)
Exc
ess
ben
d l
oss
[d
B/9
0°]
0.08
0.06
0.04
0.02
01 2 3 4 5
0.004dB/90°0.01dB/90°
0.027dB/90°
0.09dB/90°
Low loss bendsLow loss bends <0.3dB excess loss for splitters<0.3dB excess loss for splitters
Radius [um]
97% transmission in crossings97% transmission in crossings
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Fiber-chip coupling
Single-mode fiber
1m
SOI wire
Important:
Low loss coupling
Large bandwidth
Coupling tolerance
Fabrication Limited extra processing Tolerant to fabrication
Low reflection
Polarization ?
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Coupling to fiber – Inverse taperInverse taper
Broad wavelength range
Single mode
Easy to fabricate (if you can do the tips)
Low facet reflections
0.4m
80nm
0.2m
500 m
polished facet
Group h [nm]
w [nm]
L [um] tip width [nm]
Cladding Material
Cladding Size
Loss
IBM 220 445 150.0 75.0 Polymer 2x2 < 1dB
Cornell 270 470 40.0 100.0 SiO2 2x00 < 4dB
NTT 300 300 200.0 60.0 Polymer/Si3N4
3x3 0.8
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Coupling to fiber – Grating coupler
Alternative: Grating couplers
Waferscale testing
Waferscale packaging
High alignment tolerance
deep trench
shallow fibre coupler
Towards optical circuit
Single modefiber core
From Fibre
33% efficiencymeasured
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Increase effieciency ?Standard coupler (33%)
Improvement: add bottom mirror + apodize
air
Si
SiO2 box-layer
Si-substrate
air
Si
SiO2 box-layer
Si-substrate
Mode mismatch
Loss to substrate
90% simulated !
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Increase effieciency ?
FIB cross-section
grating coupler
Top view
BCB
1dB bandwidth > 40nm
No mirror
mirror69%
Improving performance
Add bottom mirror
Apodize
“Other”
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Complex filters 9x16 AWG
16 channels, 200GHz channel spacing
36 arrayed waveguides
0.1mm2 footprint
shallow etchdeep etch
waveguide
500nm800nm
10μm
10μm
5μm
2μm
100μm
-30
-25
-20
-15
-10
-5
0
1520 1525 1530 1535 1540 1545 1550 1555 15601520 1525 1530 1535 1540 1545 1550 1555 1560
wavelength [nm]
-30
-25
-20
-15
-10
-5
0
tran
smis
sion
[dB
]
1 2 3 4 8 16 1
FSR
• 2.2dB insertion loss (on-chip)• 18dB crosstalk suppression
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
SOI wavelength router
reference waveguides
4 x 4 wavelength router
Four input and four output fibers
250 GHz channel spacing
shallow star couplers, 3μm radius bends
3.5dB device insertion loss (waveguides and star coupler), -12 to -14 dB sidelobes
connectorchip
Packaging with standard V-groove arrayUsing UV-curable epoxy Packaging techniques developed for PLC reusable !!
250um
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Wavelength dependent devices
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
SOI-nanowire or Silica-on-Silicon ?
Silica-on-silicon PLC
SOI-nanowire circuits
Loss 0.3dB/m 2dB/cm (x1000 !)
Bend radius >1mm 1um (÷1000 !)
Insertion loss AWG
1.5dB - 4dB 2.5dB
Fiber coupling 0.5dB (high-) 0.5dB-1.5dB
Crosstalk -40dB -20dB
Polarisation Solved Polarisation Diversity
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
What about actives ?SOI-nanophotonics
Extremely powerful platform for passive guided wave photonics
We also need actives
Detectors and modulators See next talks
Sources Option 1: use Silicon
Indirect bandgap material, very inefficient light emitter Still: smart scientists manage to squeeze some light
out of it (see talk Pavesi)
Option 2: use III-V materials Direct bandgap, efficient light emitter
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
IST-PICMOSGOAL: Build Photonic Interconnect Layer on
CMOS by waferscale integration Solve CMOS interconnect bottleneck
Use waferscale technologies, compatible with CMOS
Partners: IMEC, ST, CEA, TRACIT, CNRS-FMNT, NCSR-D, TU/e
CMOS-wafer
Ultra-compact sourcesand detectors coupled to waveguides
Photonic wiring layerbased on high index-contrastSOI or polymer waveguides
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
III-V on Silicon ???Flip-chip bondingFlip-chip bonding
Thin film device
integration
Thin film device
integration
(IO-project)
(Duke Univesity)
III-V epi on SiliconIII-V epi on Silicon
Alignment ?Reliability ?Mass production ?
Integration through
die-to-wafer bonding
Integration through
die-to-wafer bonding
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processStarting point: Processed SOI-waveguide wafer
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processPlanarization
Planarization
SiO2-deposition and CMP
or: BCB spin-on-layer
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processDie-to-wafer bonding
Bonding InP-dies on top of planarized SOI-wafer Low alignment accuracy required
Fast pick-and-place
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processSubstrate removal
Remove InP-substrate down to etch stop layer Remove etch stop Thin membrane remains (200nm ~ 2um)
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processHardmask deposition
Decontamination and hardmask deposition in CMOS-line Succesfull demonstration of handling III-V material in Silicon “Fab”
(LETI) Alignment of waveguides and devices through lithographic methods
Micro-disk sources
DBR sources
Detectors
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processProcessing of InP-optoelectronic devices
Mesa etching and Metallization “Waferscale” processing !!!
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
IST-PICMOSMolecular bonding
InP on SOI-waveguides on CMOS demonstrated (LETI, TRACIT)
Polymer bonding Planarization and bonding in
single step (IMEC)
Ultra-thin bonding layers (sub 200nm demonstrated)
InP-layer
Si-wire
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Microdisk laser
I=800A
I=950A
I=1150A
I=1650A
I=2850A
1450 1500 1550 1600 1650
wavelength [nm]
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
multimode fibre
1E-12
1E-11
1E-10
1E-09
Po
we
r [a
.u.]
Diameter = 7.5um
Pulse width = 360ns
Period = 3600ns
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Lasing characteristics“Threshold current as low as 550A”
(pulsed operation)
1550
1560
1570
1580
1590
1600
1610
1620
5 6 7 8 9 10
Disk Diameter [um]
La
sin
g W
av
ele
ng
th [
nm
] mode1
mode2
Only fundamental (0,0,M)-modes are lasing!
0
200
400
600
800
1000
1200
5 6 7 8 9 10
Disk Diameter [um]
Th
res
ho
ld c
urr
en
t [u
A]
Pulse width = 360ns
Period = 3600ns
T = 15°C
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Temperature dependence
0
100
200
300
400
400 600 800 1000 1200 1400 1600 1800
current [uA]
po
wer
[a.
u.]
“Laser emission up to 70°C”(pulsed operation)
T=10°CT=10°C
T=20°CT=20°CT=30°CT=30°C
T=40°CT=40°C
T=50°CT=50°CT=60°CT=60°C
T=70°CT=70°C
D = 6m
1567
1568
1569
1570
1571
1572
0 10 20 30 40 50
Tamb [°C]
peak
wav
elen
gth
[nm
]
1Kpm86 dTd
14 K012)( InPdTdn
13 K017)( BCBdTdn
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Fabry-Perot laserCoupling light between III-V and SOI by means of an
adiabatic inverted taper
High coupling efficiency (simulated losses below 1dB)
Large optical bandwidth (>300nm experimentally shown)
Large fabrication tolerance
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Coupling of III-V and SOIInverted taper manufacturable using 248nm deep UV lithography
175nm
220nm
590nm
175 m
390nm 1.3m3m
BCB spacer layer
Polyimide waveguide layer
SOI taper tipSOI taper tip
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Fabrication of bonded devicesTop view and cross section of the fabricated structures
Top viewTop view Cross sectionCross section
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
MeasurementsLaser action in bonded devices
• Light collection at the SOI waveguide facet using lensed fiber
• Laser action and coupling to SOI waveguide observed
• Only pulsed operation so far due to high thermal resistance of DVS-BCB bonding layer
• Relatively high threshold current density due to facet quality
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
MeasurementsPhotodetector operation
• Light injection in SOI waveguide
• Large optical bandwidth
• Responsivity of 0.23A/W at 1555nm
• So far no electrical bandwidth measurements performed
L=50umL=50um
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InGaAs Detectors on SOI
Measured response of 4 detectors
To detectors
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
Conclusion
Silicon-on-insulator technology Extremely compact devices Fabrication with commercial CMOS technology Building blocks demonstrated Potential for a “standardised” platform
WDM-devices Basic devices demonstrated (AWG, filters…)
Extension with active functionality Demonstrated electrically contacted micro-disk lasers on
Silicon
Demonstrated Fabry-Perot lasers coupled to SOI-waveguides
Demonstrated efficient detectors
© intec 2006 - Photonics Research Group - http://photonics.intec.ugent.be
The photonics research group at INTEC/IMEC
P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan…
D. Van Thourhout, P. Bienstman, R. Baets
The Silicon Process division at IMEC Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven,
Rudi De Ruyter, Johan Mees
PICMOS partners J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Lagahe, B. Aspar (TRACIT) (planarization) C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)
European Union, Belgian and Flemish government
Acknowledgements