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PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Latent Effects in Digital ICs under Electrical Overstress Pulses

P. K. Skorobogatov, K. A. Epifantsev

Abstract — The results of experiments on electrical overstresses (EOS) influence on digital ICs with the amplitude below the threshold of damage are presented. As a result the latent effects of additive nature were found out.

I. INTRODUCTION

Electronic circuits are strongly influenced by space radiation [1-3]. The charging of spacecraft components by high energy radiation can result in spontaneous pulsed electrostatic discharges (ESD). These pulses can interrupt normal operation of spacecraft electronics [4]. Energetic electrons can sufficiently penetrate the spacecraft structure and stop within cable insulation, circuit boards, and other dielectrics, depositing their charge. Once enough charge has been accumulated within a dielectric, discharge can occur if the resultant electric field strength exceeds the material’s breakdown limit. This phenomenon is known as internal ESD. As shown in [5] internal ESD accounts for 25% of reported spacecraft anomalies and failures due to space environment.

A number of tests with 100 keV – 2 MeV electron beams on wiring, circuitboards and samples of typical geometry find pulses rarely exceed 100 V peak on 50 and last less than 1µs [4]. The varieties of pulse sizes and shapes seem to grow with the complexity of equipment.

The amplitude and energy of one spacecraft ESD pulse may be insufficient to produce the damage of IC resulting in latent effects. But the series of ESD pulses can reduce the IC reliability and tends to parametric degradation and functional malfunction due to additive mechanisms.

The latent effects in digital ICs were investigated under series of electrical overstress (EOS) pulses with amplitude below and up to threshold of damage.

II. TEST EQUIPMENT AND PROCEDURE

The specialized pulse voltage generator (EMI-601) was used to estimate the IC EOS behavior. The EMI-601 generator has output parameters presented in Table 1. Test procedure is described in [6].

TABLE 1. THE EMI-601 PERFORMANCE DATA

Parameter Value Pulse form Double Exponent Pulse amplitude, V 5 < Um < 800 Pulse rise time, ns 20...30 Pulse width at 0.5 level, s: 0.1, 1.0 and 10 Output resistance, 50

The test setup diagram is shown in Fig. 1.

Fig. 1. EOS test setup diagram: Uoutu is output signal from divider; Uouti is output signal from current sensor (resistor or current transformer)

The IC under test is connected through buffer unit

(BU) to a storage oscilloscope and a functional control module (FCM). BU ensures the device to be under test conditions. FCM is used in complex ICs testing, such as microprocessors, RAM, etc. The EOS hardness levels were defined separately for inputs, outputs and supply pins of IC. The EOS pulses were applied between the ground and appropriate pin.

The criteria of failure were as follows: - IC malfunction; - IC parametric failure. The unused IC pins must be connected to the ground

or supply through 5 kΩ – 10 kΩ resistors to prevent the undesirable transitions during tests.

P. K. Skorobogatov is with National Research Nuclear University “MEPhI”, Moscow, Russia, (e-mail: pkskor@ spels.ru).

K.A. Epifantsev, is with National Research Nuclear University “MEPhI”, Moscow, Russia), (e-mail: kaepif@spels.ru).

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III. THE EXPERIMENTAL RESULTS

A series of experiments was conducted over some of ICs. Voltage amplitude pulse was chosen below the damage threshold determined previously for single EOS.

The experiments on 74ALS00 IC analogous showed that the most critical parameter is an input leakage current at high level. Fig. 2 represents the number of the EOS 10 µs pulses, needed for 74ALS00 IC input circuit damage for different pulse amplitudes.

Fig. 2. Number of the EOS 10 µs pulses needed for 74ALS00 IC input circuit damage for different pulse amplitude: 1 - parametric failure; 2 - functional failure.

Experiments were performed at room temperature and +5V power supply. The parametric failure (due to input leakage current increase) was observed in the beginning of EOS series. After additional EOS pulses the functional failure (absence of switching) was indicated.

It was observed that the series of EOS pulses with sub threshold amplitude causes parametric and functional failures. Than less pulse amplitude, that their greater amount is necessary for failure occurrence. All of this confirms an additive nature of EOS impact for chosen IC type [9].

For definition of each pulse contribution to IC input leakage current degradation, the input current dependence from the number of EOS 10 µs width pulses with sub threshold amplitude 24 V was experienced. The results of experiments presented in fig. 3 confirm the additive nature of parametric damage. The exit of input leakage current over the failure criterion does not take place as long as the number of EOS pulses is less than 14.

The relaxation of IC input current was investigated also. The partial input current recovery (about 50%) was defined after EOS pulses with sub threshold voltage amplitude for the times of order of tens of minutes.

The experiments on CMOS RAM HM6504B-2 IC analogous did not find the sufficient additive effects of

parametric damages under input sub threshold EOS pulses. Most likely, the input protection circuit prevents degradation of inside elements up to the threshold of its destruction.

Fig. 3. 74ALS00 high level input leakage current vs number of 24 V 10 µs EOS pulses.

Weak additive effect was found out after the series of

ESD pulses applied to CMOS IC power supply pins. Results of experiments presented in fig. 4, show presence of the relatively narrow gap between parametric and functional failures. Additive effects are relatively pure as compared with 74ALS00 IC.

Significant functional additive effect was found after series of input sub threshold EOS pulses applied to CMOS RAM HM6504B-2 IC. EOS sub threshold input pulses result in functional damage of CMOS RAM (in reading mode) at lower amplitudes than in case of one EOS pulse damage.

Fig. 4 The number of the EOS 10 µs pulses needed for CMOS RAM HM6504B-2 IC damage through power supply pins vs pulse amplitude: 1 - parametric failure; 2 - functional failure.

The number of EOS 10 µs input pulses needed for RAM functional damage is presented in fig. 5.

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Fig. 5. The number of EOS 10 µs input pulses needed for IC RAM functional damage.

Electrothermal behavior of SOS CMOS chip elements

is described in [10].

IV. DISCUSSIONS The experiments confirmed the role and importance of

latent effects in the EOS degradation of IC parameters. The latent defects are very difficult to identify. A

device that is exposed to an EOS event may be partially degraded, yet continue to perform its intended function. However, the operating life of the device may be reduced significantly. Such effects may cause the IC failure in critical applications [11].

Direct EOS to devices may cause failures either through voltage breakdown damage to insulating oxide layers, or energy related damage to p-n junction, metallization burnout and other features. Similar effects also occur when latent damage takes place.

Dielectric breakdown. If the breakdown field strength of such oxide layer is exceeded, dielectric breakdown can occur. Where subsequent current flow does not have sufficient energy to cause a short circuit, the device may continue to operate. It may have a detectable increased leakage current that was observed (fig. 3). This device has a low reliability and may fail later.

Junction burnout. An EOS pulse may pass through a transistor junction. The high current causes local heating that may lead to melting and short-circuit of the junction. If the EOS amplitude is not enough additional p-n junction layers diffusion due to heating may cause its parameters degradation.

Metallization melt. Metallization melt or burnout happens when the current in an interconnection track is high enough to raise the temperature to melting point. Under the melting point it may cause metallization electromigration.

Latch-up. Latch-up is a problem in CMOS ICs caused by the turn-on and latching of parasitic SCR structures. Large currents can flow, leading to thermal heating and possible latent effects.

V. CONCLUSION

Obtained experiment results showed that generally it

is necessary to take into account additive effects in bipolar and CMOS ICs under sub threshold EOS pulses. The presence of sub threshold effects of additive nature requires their account at the development of on-board equipment for space applications.

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