![Page 1: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/1.jpg)
Instruction Sets:Addressing modes and
FormatsGroup #4
Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar
Computer DesignEEL 4709cProf: Herman WatsonSpring 2009
![Page 2: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/2.jpg)
Addressing Modes
Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack
![Page 3: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/3.jpg)
Immediate Addressing Operand is part of instruction Value to be loaded is fixed at compile-time
(not very flexible) e.g. ADD 8
Add 8 to contents of accumulator 8 is operand
Does not have an effective address Fast (Value to be loaded – included in inst) Value stored in memory follows
immediately the operation code in memory
![Page 4: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/4.jpg)
Immediate Addressing Diagram
OperandOpcode
Instruction
![Page 5: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/5.jpg)
Direct Addressing
Address field contains address of operand
Effective address (EA) = address field (A) e.g. ADD C
Add contents of cell C to accumulator Look in memory at address C for operand
Directly retrieves stored value in memory from another memory location.
Fast (Internal RAM) Limited address space
![Page 6: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/6.jpg)
Direct Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
![Page 7: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/7.jpg)
Indirect Addressing
Memory cell pointed to by address field contains the address of (pointer to) the operand
EA = (C) Look in C, find address (C) and look there
for operand Exceptional level of flexibility. Always refers to Internal RAM.
![Page 8: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/8.jpg)
Indirect Addressing
2n where n = word length Multilevel, cascaded, or nested Address space (Large) Slower Multiple memory accesses -> operand
![Page 9: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/9.jpg)
Indirect Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
Pointer to operand
![Page 10: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/10.jpg)
Register Addressing
Operand contained in register (Named -> address filed)
Registers (Limited) Needs -> Very small address field
Instructions (Fast, hence faster instruction fetch)
EA= R
![Page 11: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/11.jpg)
Register Addressing
Address space -> Very limited Memory Address -> None Multiple registers -> Improves
performance N.B. C programming Good compiler writing or assembly
programming -> Required Execution -> Very fast
![Page 12: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/12.jpg)
Register Addressing Diagram
Register Address ROpcode
Instruction
Registers
Operand
![Page 13: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/13.jpg)
Register Indirect Addressing
Address of operand obtained indirectly via an address register.
Indirect addressing uses an address register to point at the location of the operand in memory.
EA = (R) Generates lots of different addresses
when program executed. Address Space -> Large (2n)
![Page 14: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/14.jpg)
Register Indirect Addressing Diagram
Register Address ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
![Page 15: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/15.jpg)
Displacement Addressing
Choosing displacement field size is important -> directly affects instruction length.
EA = A + (R) Address field hold two values
A = base value R = register that holds displacement or vice versa
![Page 16: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/16.jpg)
Displacement Addressing Diagram
Register ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Address A
+
![Page 17: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/17.jpg)
Relative Addressing
An address specified by indicating its distance from another address. (Base Address)
A version of displacement addressing For example: B+15 B being the base address and 15 the
distance (Called the offset)
![Page 18: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/18.jpg)
Base-Register Addressing
R -> Explicit or Implicit R contains pointer to base address A holds displacement e.g. segment registers in 80x86
![Page 19: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/19.jpg)
Indexed Addressing
Variables which use indexed addressing: Variables referenced by pointers Arrays Local Variables, in stack-based languages.
E.g. (IX, IY registers) A = base R = displacement EA = A + R Automatically increments address with
the value stored in an index register.
![Page 20: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/20.jpg)
Combinations
Combinations of the three basic addressing modes -> additional addressing modes.
Resultant or operational instruction cannot be immediate data. (Direct of Indirect memory location)
Postindex EA = (A) + (R)
Preindex EA = (A+(R))
![Page 21: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/21.jpg)
Stack Addressing
Data structure grows downward from high to low memory in SP.
New byte pushed onto the stack -> SP decremented
Byte pulled from the stack -> SP incremented
Operand is (implicitly) on top of stack e.g.
ADD Pop top two items from stackand add
![Page 22: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/22.jpg)
Pentium Addressing Modes
Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled
12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative
![Page 23: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/23.jpg)
Pentium Addressing Mode Calculation
![Page 24: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/24.jpg)
PowerPC Addressing Modes
Load/store architecture Indirect
Instruction includes 16 bit displacement to be added to base register (may be GP register)
Can replace base register content with new address Indirect indexed
Instruction references base register and index register (both may be GP)
EA is sum of contents Branch address
Absolute Relative Indirect
Arithmetic Operands in registers or part of instruction Floating point is register only
![Page 25: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/25.jpg)
PowerPC Memory Operand Addressing Modes
![Page 26: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/26.jpg)
Instruction Formats
Essentially the layout of the Bits in an Instruction set including: OpCodes Operand(s) expressed either implicitly or
explicitly Memory address Register
Usually more than one instruction format is used and usually varies depending on whether its addressing Memory, I/O devices or a Register
![Page 27: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/27.jpg)
Instruction Length
Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed
![Page 28: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/28.jpg)
Longer Instruction Length
Pros: More OpCodes Operands Addressing Modes Greater Address Range Therefore easier
Programming Language Cons:
Waste of Space
Example: A 64 bit instruction is less than twice as useful as a 32 bit instruction.
![Page 29: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/29.jpg)
Allocation of Bits
Number of addressing modes: i.e. certain opcodes always call for indexing, in others, addressing
modes must be explicit and more than one bit might be needed. Number of operands:
Typical instructions in today’s machines call for two operands. Register versus memory:
The more registers that can be used for oprand references , the fewer bits are needed. Most resent day designs have at least 32 registers.
Number of register sets: A method used by Pentium uses two sets of 8 registers and only 3
bits are required to identify the register. The opcode will determine which register is being referenced.
Address range: Rarely used because it imposes a limitation in the amount of
address since its directly related to the size of the address.
![Page 30: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/30.jpg)
PDP-8 Instruction Design
Only 12 bit Instructions 7 Bits to Reference to Memory:
(2)^7 = 128 Different Words
2 Bits used as modifiers ; First referenced to page
containing instruction Second used to indicate
whether direct or indirect addressing is to be used.
3 Bits used for the opcode: Of the 8 different opcode
combinations, 2 are used to reference a page bit or an indirect leaving 6 basic operations.
![Page 31: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/31.jpg)
PDP-8 Instruction Format
![Page 32: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/32.jpg)
PDP-10 Instruction Format
• Orthogonality• Principle that two variables are independent of
each other.• Completeness
• Each arithmetic data type (integer, fixed-point, real) should have a complete and identical set of operations.
• Direct addressing• Used instead of base plus displacement
addressing to lower the burden on the programmer.
![Page 33: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/33.jpg)
PDP-11 Instruction Format
![Page 34: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/34.jpg)
• The PDP-11 was designed to provide a powerful and flexible instruction set
• Only constraint was the use of a 16-bit minicomputer [BELL70]
• It employs 16-bit general purpose registers• Two of these 16 have a significant purposes:
• One is used as a stack pointer for special purpose stack operations
• The other is used as the program counter (containing address of next instruction)
![Page 35: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/35.jpg)
VAX Instruction Examples
![Page 36: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/36.jpg)
VAX
![Page 37: Instruction Sets: Addressing modes and Formats Group #4 Eloy Reyes Rafael Arevalo Julio Hernandez Humood Aljassar Computer Design EEL 4709c Prof:](https://reader036.vdocuments.net/reader036/viewer/2022062423/5697c00d1a28abf838cc9561/html5/thumbnails/37.jpg)
Questions?
Why is it known immediate addressing? Which addressing mode has a limited address space? How does data structure grows in stack addressing? Give two examples of indexed addressing modes. Why do programmers prefer longer instruction ? How many bits does the PDP-8 design use for addressing? How is called the address the Pentium translation mechanism? In register operand mode, what one has to with 64-bit floating
point operation? The PDP-10 was designed to be what kind of system and with
what emphasis? What two criteria were used in designing the VAX instruction
format?