Instructor: Yuzhuang [email protected]
MidtermThe midterm is schedule on June 17th, 17:30-
19:30 pm. It covers the following:VHDL Programming.Number Systems.Sequential Circuit Design. This includes State-
Machine Diagrams, ASM chart, control unit, data path, etc.
The Simple Single-Cycle Computer. Its Datapath, the Control Word, Instruction Formats, Single Cycle Hardwired Control, etc.
Block Diagram for a Single-Cycle Computer
BusA Bus BAddress out
Data outMW
Data in
MUX B1 0
MUX D0 1
DATAPATH
RWDA
AA
Constantin
BA
MB
FSVCNZ
Functionunit
A B
F
MDBus D
IR(2:0)
Data in Address
Datamemory
Data out
DRegister
fileA B
Instructionmemory
Address
Instruction
Zero fill
DA
BA
AA
FS
MD
RW
MW
MB
Instruction decoder
JB
Extend
LP B
C
BranchControl
VCNZ
JBL
P BC
IR(8:6) || IR(2:0)
PC
CONTROL
JumpAddress
Instruction Specifications for the Simple Computer
TABLE 9-8InstructionSpecificationsfor theSimpleComputer
Instruction OpcodeMne-monic Format Description
StatusBits
MoveA 0000000 MOVA RD, RA R[DR]← R[SA ]* N, ZIncrement 0000001 INC RD,RA R[DR]← R[SA ] + 1* N, ZA dd 0000010 A DD RD, RA, RB R[DR]← R[SA ] + R[SB]* N, ZSubtract 0000101 SUB RD, RA, RB R[DR]← R[SA ]− R[SB]* N, ZDecrement 0000110 DEC RD, RA R[DR]← R[SA ]− 1* N, ZA ND 0001000 A ND RD, RA, RB R[DR]← R[SA ]∧R[SB]* N, ZOR 0001001 OR RD, RA, RB R[DR]← R[SA ]∨R[SB]* N, ZExclusive OR 0001010 XOR RD, RA, RB R[DR]← R[SA ]⊕ R[SB]* N, ZNOT 0001011 NOT RD, RA R[DR]← * N, ZMoveB 0001100 MOVB RD, RB R[DR]← R[SB]*Shift Right 0001101 SHR RD, RB R[DR]← sr R[SB]*Shift Left 0001110 SHL RD, RB R[DR]← sl R[SB]*Load Immediate 1001100 LDI RD, OP R[DR]← zf OP*A dd Immediate 1000010 A DI RD, RA, OP R[DR]← R[SA ] + zf OP* N, ZLoad 0010000 LD RD, RA R[DR]← M[SA ]*Store 0100000 ST RA, RB M[SA ]← R[SB]*Branch on Zero 1100000 BRZ RA,AD if (R[SA ] = 0) PC← PC + seAD,
if (R[SA ]≠ 0) PC ← PC + 1N, Z
Branch on Negative
1100001 BRN RA,AD if (R[SA ] < 0) PC← PC + seAD,if (R[SA ]≥ 0) PC ← PC + 1
N, Z
Jump 1110000 JMP RA PC ← R[SA ]
* For all of theseinstructions,PC ← PC +1isalsoexecutedtopreparefor thenextcycle
Control Unit of the Single Cycle Simple Computer
We have described the design of its datapath.
The block diagram for this computer has a hardwired control unit that fetches and executes an instruction in a single clock cycle.
We do not write to the instruction memory, making it appear in this model to be a combinational rather than a sequential component.
The Program Counter (PC)The PC provides the instruction address to the
instruction memory.
The PC is updated in each clock cycle. The behaviour of the PC is determined by the opcode, N, and Z.
PC Operation PL JB BC
Count Up 0 X X
Jump 1 1 X
Branch on Negative (else Count Up) 1 0 1
Branch on Zero (else Count Up) 1 0 0
Instruction DecoderThe instruction decoder is a combinational circuit that
provides all of the control words for the datapath, based on the contents of the fields of the instruction.
TruthTable for Instruction Decoder Logic
Instruction FunctionType
Instruction Bits Control Word Bits
15 14 13 9 MB MD RW MW PL JB BC
Function unit operations usingregisters
0 0 0 X 0 0 1 00 X X
Memory read 0 0 1 X 0 1 1 00 X XMemory write 0 1 0 X 0 X 0 1 0 X XFunction unit operations using
register and constant1 0 0 X 1 0 1 00 X X
Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0Conditional branch on negative (N)1 1 0 1 X X 0 0 1 0 1Unconditional Jump 1 1 1 X X X 0 0 1 1 X
Instruction Decoder contd.The 13th, 14th and 15th bits of the instruction are
set to 1 respectively, to distinguish the memory read, memory write and constant involved instructions from the register only instructions.
For this reason MB=15th bit, MD=13th bit, and the 14th bit is involved in generating MW.
There is some additional logic to prevent RW and MW to be 1 at the same time.
Instruction Decoder contd.The 15th bit of the instructions is used mainly for
jumping and branching instructions. However to distinguish them from the instructions involving constants, the 14th bit is also needed to generate PL.
BC uses the 9th bit. JB uses the 13th bit, however as PL=1 when JB=1, there is no conflict with MD.
For conditional branching, it is required that FS=0000. That’s the reason PL is involved in generating FS.
Instruction Decoder Logic
19–17
DA
16–14
AA
13–11
BA
10
MB
9–6
FS
5
MD
4
RW
3
MW
2
PL
1
JB
0
BC
Instruction
Opcode DR SA SB
Control word
151413121110 9 8–6 5–3 2–0
Sample Instructions
Six Instructionsfor theSingle-Cycle Computer
Operationcode
Symbol icname Format Description Func tion MBMDRWMWPL JB BC
1000010 ADI Immediate Add immediateoperand
1 0 10 0 0 0
0010000 LD Register Load memorycontent intoregister
0 1 10 0 1 0
0100000 ST Register Store registercontent in
memory
0 1 01 0 0 0
0001110 SL Register Shift left 0 0 10 0 1 0
0001011 NOT Register Complementregister
0 0 10 0 0 1
1100000 BRZ Jump/Branch If R[SA]= 0, branchto PC+ se AD
If R[SA] = 0,,
If R[SA] 0,
1 0 00 1 0 0
R DR R SAzf I(2:0)+
R DR M R SA
M R SA R SB
R DR slR SB
R DR R SA
PC PC se AD+PC PC 1+
Shortcomings of the Single-Cycle ComputerThe single cycle computer can not perform more
complex operations. For example, unsigned binary multiplications.
The single cycle computer has two distinct 16-bit memories, one for instructions and one for data.
Every instruction, no matter it is simple or complex (e.g., jmp), is executed in a clock cycle. Therefore It has a lower limit on the clock period.
Worst-Case Delay Path in Single-Cycle Computer PC
Instruction Memory
Register File (Read)
MUX B
FU or Data Memory
Register File (Write)
MUX D
0.2
ns
4.0
0.6
0.2
4.0
0.2
0.6
Store Instructions and Data in a Single MemoryDatapath : a single memory, and an MUX M.
Add 8 temporary registers to the register file.
Control Unit: Instruction Register (IR) to store the
instruction fetched from the memory.Control State. The control unit is now a
sequential circuit.Control Logic : different control words. Branch
logic is moved to here.
Sequencecontrol
Datapathcontrol
CONTROL
4
RW
4
4
4
16
IL
3 3 37
4
NS
PS
IL
DX
AX
BX
MB
FS
MD
RW
MM
MW
4
DATAPATH
MB1 0MUX B
Bus BBusA MM
0 1MUX M
Dataout
MW Addressout
Data in
A B
Functionunit
F
0 1MUX DMD
Bus D
FSVCNZ
Zero fill
PS
Extend
2
Registeraddresslogic
AX BX DX
DRSASB
3
33
4 4 4
Control Logic
4
4
PC
IROpcode DR SA SB
Control State
Data in Address
MemoryM
Data out
DA
AA
D
16 16Register
file
A BBA
Control Word Format for Multi-Cycle ComputerThe addressing of the registers needs 4 bits (DX, AX, BX).
NS PS IL
MB
MD
RW
MM
MWDX AX BX FS
27 2423222120 1716 1312 9 8 7 4 3 2 1 0
DatapathSequencing
NS PS IL
Next State Action CodeAction Code
Gives next stateof Control StateRegister
Hold PC00 No load 0Inc PC 01 Load IR 1Branch 10Jump 11
Sequence ControlNS: next statePS: control PCIL: control IR
Sequential Control Design Now the computer has two stages: instruction fetch (INF stage)
and instruction execution (EX0 stage).
IR
Register File (Read)
MUX B
FU or Data Memory
Register File (Write)
MUX D
0.2
ns
0.6
0.2
4.0
0.2
0.6
PC
MUX M
Memory
IR
0.2
ns
0.2
4.0
0.2
INF EX0
Instruction Specifications Instruction Speci fications for the Simple Computer - Part 1
Instruction Opcode MnemonicFormat DescriptionStatusBits
Move A 0000000MOVA RD,RA R[DR] R[SA] N, ZIncrement 0000001 INC RD,RA R[DR] R[SA]+ 1 N, ZAdd 0000010 ADD RD,RA,RB R[DR] R[SA]+ R[SB] N, ZSubtract 0000101 SUB RD,RA,RB R[DR] R[SA] [SB] N, ZDecrement 0000110 DEC RD,RA R[DR] R[SA] 1 N, ZAND 0001000 AND RD,RA,RB R[DR] R[SA] R[SB] N,ZOR 0001001 OR RD,RA,RB R[DR] R[SA] R[SB] N,Z
Exclusive OR 0001010 XOR RD,RA,RB R[DR] R[SA] R[SB] N, ZNOT 0001011 NOT RD,RA R[DR] N,ZR[SA]
R
Partial State Machine Diagram for Multiple-Cycle Computer
0000001
00000100000101
0000110
00010000001001
0001010
0001011
0000000
EX0
INF
R[DR] R[SA ]
R[DR] R[SA ] + 1R[DR] R[SA ] + R[SB]
+ R[SB] +1R[DR] R[SA ]
R[DR] R[SA ]2 1
R[DR] R[SA ] R[SB]
R[DR] R[SA ]% R[SB]
IR M[PC]
R[DR] R[SA ]
R[DR] R[SA ] R[SB]
Opcode =
PC PC + 1S
Deriving Logic ExpressionsFor PC <- PC +1, we must set PS to 01.
We can write PS(0) = EX0·MOVA + EX0 ∙ INC + EX0 ∙ ADD + … + EX0·BRZ·(not Z).
Each combination of state, opcode, and condition codes where the signal should be 1 introduces a product term to the final expression.
Multiplication in the Multiple-Cycle ComputerFor simple instructions, we need more time
to finish them in the multi-cycle computer.
Multiplication shows the advantage.Assume multiplication in the function unit
needs 10 ns. For the single cycle-cpu, the clock cycle must be increased to 15.8 ns.
The clock cycle would remain 5.8 ns, if we give one more clock cycle for multiplication.
State Diagram for Multiplication
INF IR <- M[PC]
EX0
MultiplyR[SA]*R[SB]
IMUL1
R[DR] <- R[SA]*R[SB],PC <- PC + 1
Register Indirect InstructionsR[DR] <- M[M[R[SA]]].
INF IR <- M[PC]
EX0
Opcode = 0010001 R8 <-
M[R[SA]]
EX1 Opcode = 0010001 R[DR]<-R8,
PC <- PC+1
Partial State Machine Diagram for Right-Shift and Left-Shift Multiple Instructions
From INF
To INF
R8 R[SA ]
Opcode = 0001101R8 sl R8
PC PC 1 1
R[DR] R8,
EX1
EX2
EX0Z · ((Opcode = 0001101) + (Opcode = 0001110))
Z · ((Opcode = 0001101) + (Opcode = 0001110))
Z · ((Opcode = 0001101) + (Opcode = 0001110))
EX3R8 sr R8
Opcode = 0001110
R9 zf OP
Z · ((Opcode = 0001101) + (Opcode = 0001110))
Z · ((Opcode = 0001101) + (Opcode = 0001110))
R9 R9 2 1
EX4
(Opcode = 0001101) + (Opcode = 0001110)
Z · ((Opcode = 0001101) + (Opcode = 0001110))
PC PC 1 1
PC PC 1 1
Micro-programmed ControlA control unit with its binary control values stored as
words in memory is called a micro-programmed control.
Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system.
The micro-program is usually fixed at the system design time and so is stored in ROM.
CAR: Control Address Register.
THANKS!