Download - Intoduction au VHDL
-
8/8/2019 Intoduction au VHDL
1/58
Electronic Design Process
-
8/8/2019 Intoduction au VHDL
2/58
Introduction to VHDLIntroduction to VHDL
NiveauxNiveaux dabstractiondabstraction pour la conceptionpour la conception numriquenumrique
Chaque niveau d'abstraction dfinit un description de la circuit avec moins ou plus de
dtails par rapport au niveaux infrieur ou suprieur
-
8/8/2019 Intoduction au VHDL
3/58
Code comportementaldcrit les fonctionnalitset le comportement de
la circuit
Introduction to VHDLIntroduction to VHDL
Behavioral vs. RTL (Structural)Behavioral vs. RTL (Structural)
Code structural dcrit la
niveau registres et porte
logique de circuit
-
8/8/2019 Intoduction au VHDL
4/58
RTL
SimulationSynthse
Gate
Level
SimulationLay-outPlacement/routage
FPGA ASIC
Flot de
conceptionBehavioral
Testbench
Tech.
Lib.
Simui.
Lib.
-
8/8/2019 Intoduction au VHDL
5/58
Cest quoit VHDL?
VHSIC
Hardware
Description
Language
VHSIC Very High Speed Integrated Circuit
vhdl
Fonctions
concurrents
Description
hirarchique
Fonctions
squentielles
Modlisation
de temps
-
8/8/2019 Intoduction au VHDL
6/58
6
VHDL: concepts de base
Structure gnraleVotre fichier texte de
description: xxx.vhd
Mode transfert des
signaux de votre
entity
-
8/8/2019 Intoduction au VHDL
7/58
VHDL:Les en-ttes de fichier
LibraryIEEE ;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
.
Le mot use : indique quelle package de la librairie nous allons utiliser
Il faut pas utiliser Numeric_std et std_logic_arith en mme temps pour ne pas avoir
conflit
-
8/8/2019 Intoduction au VHDL
8/58
VHDL:Lentit
entity sequencement is
Port (
clock : in std_logic;
reset : in std_logic;
Q : out std_logic_vector (1 down to 0)
);End sequencement ;
sequencement
Clock
reset
Q(1:0)
-
8/8/2019 Intoduction au VHDL
9/58
VHDL: Dclaration de l'architecture
Rfrence
une entit
Nom de
larchitecture
-
8/8/2019 Intoduction au VHDL
10/58
The 2-to-1 Multiplexer
Introduction to VHDLIntroduction to VHDL
d0
d1
f
s
ENTITY mux2to1 ISPORT( d0, d1, s :IN STD_LOGIC;f :OUT STD_LOGIC);
END mux2to1;
-
8/8/2019 Intoduction au VHDL
11/58
Description compartmental
If s=0, d0 passes sur la sortie f: f=d0
If s=1, d1 passes sur la sortie f=d1
Introduction to VHDLIntroduction to VHDL
d0
d1
f
s
-
8/8/2019 Intoduction au VHDL
12/58
Introduction to VHDLIntroduction to VHDL
d0
d1
f
s
ARCHITECTURE behavior OF mux2to1 IS
BEGIN
WITH s SELECTf
-
8/8/2019 Intoduction au VHDL
13/58
Description structuralDescription structural
Introduction to VHDLIntroduction to VHDL
d0
d1
f
s
d0
d1
s
f
-
8/8/2019 Intoduction au VHDL
14/58
Introduction to VHDLIntroduction to VHDL
d0
d1
f
s
d0
d1
s
f
ARCHITECTURE structure OF mux2to1 IS
BEGINf
-
8/8/2019 Intoduction au VHDL
15/58
Un bon exemple est la construction d'un multiplexeur(4-pour-1) partir de 2 (Muxes 2-pour-1 ) qui seront
utilis comme composants
HierarchieHierarchie
Introduction to VHDLIntroduction to VHDL
d0
d1
f
d2
d3
s0s1
-
8/8/2019 Intoduction au VHDL
16/58
The 4-to-1 Mux
Introduction to VHDLIntroduction to VHDL
d0
d1
f
d2
d3
ENTITY mux4to1 ISPORT( d0, d1, d2, d3, s0, s1 : IN STD_LOGIC;
f : OUT STD_LOGIC);
END mux4to1;
d0
d 1
f
d2
d3
s 1 s 0
-
8/8/2019 Intoduction au VHDL
17/58
Introduction to VHDLIntroduction to VHDLIntroduction to VHDLIntroduction to VHDL
d0
d 1
fd2
d3
s 1 s 0
ENTITY mux4to1 ISPORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;
f :OUTSTD_LOGIC);
END mux4to1;
ARCHITECTURE structure OF mux4to1 IS
SIGNALI1, I2 :STD_LOGIC;
COMPONENT mux2to1
PORT(d0, d1, s :IN STD_LOGIC;f :OUTSTD_LOGIC);
END COMPONENT;
BEGIN
u1:mux2to1 PORT MAP(w0, w1, sel0, I1);
u2:mux2to1 PORT MAP(w2, w3, sel0, I2);
u3:mux2to1 PORT MAP(I1, I2, sel1, f);
END structure;
-
8/8/2019 Intoduction au VHDL
18/58
Processes
Un processus est une rgion de code VHDL qui
excute squentiellement
Existe l'intrieur de l'architecture
Plusieurs processus sexcutent en
concurrence les uns avec les autres
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
19/58
Introduction to VHDLIntroduction to VHDL
ProcessesProcesses
ENTITY orgate IS
PORT (a,b : in bit;
z : out bit);
END orgate;
ARCHITECTURE Behavior OR orgate IS
BEGIN
or_func: PROCESS (a,b)
BEGIN
IF (a='1' OR b='1') THEN
z
-
8/8/2019 Intoduction au VHDL
20/58
Back to the 4-to-1 Mux example
Introduction to VHDLIntroduction to VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT (d0, d1, s :IN STD_LOGIC;
f :OUTSTD_LOGIC);
END mux2to1;
ARCHITECTURELogicFunc OF mux2to1 IS
BEGIN
f
-
8/8/2019 Intoduction au VHDL
21/58
Types
Introduction to VHDLIntroduction to VHDL
ENTITY fulladd IS
PORT (a,b,Cin : IN bit;
sum, Carry : OUT bit);
END fulladd;
ARCHITECTURE struct OF fulladd IS
SIGNAL n_sum : bit;
-- oth
er declarationsBEGIN
-- Code
END struct;
-
8/8/2019 Intoduction au VHDL
22/58
When an assignment is made to a signal,
the types on either side of the signal
assignment operator must match up
Introduction to VHDLIntroduction to VHDL
TypesTypes
ENTITY fulladd IS
PORT (a,b,Cin :IN bit;
Sum, Carry: OUT bit);
END fulladd;
ARCHITECTURELogic OF fulladd IS
BEGIN
Sum
-
8/8/2019 Intoduction au VHDL
23/58
Types prdfinis
Introduction to VHDLIntroduction to VHDL
PACKAGE standard ISTYPE boolean IS (true, false);
TYPE bit IS (0, 1)
TYPE character IS (-- ascii set)
TYPE integer IS range implementation_defined;
TYPE real IS range implementation_defined;
-- bit_vector, string, timeEND standard;
-
8/8/2019 Intoduction au VHDL
24/58
Types predefinsTypes predefins
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
25/58
Standard Logic represented byIEEE 1164
In general, std_logic should be used ALL OF
THETIME
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
26/58
Introduction to VHDLIntroduction to VHDL
ArraysArrays
-
8/8/2019 Intoduction au VHDL
27/58
Introduction to VHDLIntroduction to VHDL
Assignment des matricesAssignment des matrices
-
8/8/2019 Intoduction au VHDL
28/58
Introduction to VHDLIntroduction to VHDL
Assignment de matrixAssignment de matrix
-
8/8/2019 Intoduction au VHDL
29/58
Introduction to VHDLIntroduction to VHDLIntroduction to VHDLIntroduction to VHDL
matrices etmatrices et ConcatenationConcatenation
-
8/8/2019 Intoduction au VHDL
30/58
Introduction to VHDLIntroduction to VHDL
ArraysArrays etetAggregatesAggregates
-
8/8/2019 Intoduction au VHDL
31/58
Introduction to VHDLIntroduction to VHDL
Assignment dun matrixpar nomAssignment dun matrixpar nom
-
8/8/2019 Intoduction au VHDL
32/58
Introduction to VHDLIntroduction to VHDL
Assignment dun matrixpar nomAssignment dun matrixpar nom
-
8/8/2019 Intoduction au VHDL
33/58
VHDL Operators
Il existe 3 varits d'oprateurs: logique, relationnel,et arithmtique.
Les oprateurs logiques sont "et", "ou", etc
Les oprateurs relationnels sont utiliss pourcomparer les diffrentes valeurs
Les oprateurs arithmtiques sont utilises poureffectuer des fonction mathmatiques
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
34/58
Comprend ET, OU, NAND, NOR, XOR et NOT
Tous ont la mme priorit
Excuter de gauche droite
NOT a la plus grande priorit, et excute donc avant
d'autres oprateurs dans une expression logique.
Les oprations logiques ne peut tre applique que
des matrice du mme type et de mme longueur Correspondants des lments dans des matrice se
fait par POSITION
Introduction to VHDLIntroduction to VHDL
VHDL OperatorsVHDL Operators -- LogicalLogical
-
8/8/2019 Intoduction au VHDL
35/58
Introduction to VHDLIntroduction to VHDL
VHDL OperateursVHDL Operateurs -- RelationnelRelationnel
-
8/8/2019 Intoduction au VHDL
36/58
Introduction to VHDLIntroduction to VHDL
VHDL OperatorsVHDL Operators -- RelationalRelational
111 > 1011
-
8/8/2019 Intoduction au VHDL
37/58
Introduction to VHDLIntroduction to VHDL
VHDL OperatorsVHDL Operators -- ArithmeticArithmetic
-
8/8/2019 Intoduction au VHDL
38/58
Dclarations squentielle en VHDL
Processes
If-then-else
Case
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
39/58
Back to the ProcessBack to the Process
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
40/58
-
8/8/2019 Intoduction au VHDL
41/58
Introduction to VHDLIntroduction to VHDL
DclarationDclaration IFIF--ELSIFELSIF
-
8/8/2019 Intoduction au VHDL
42/58
The order in which statements are written in theIF-ELSIF structure is very important
More than one of the conditions may be true
The first true condition causes its set ofstatements to be executed
Introduction to VHDLIntroduction to VHDL
The IFThe IF--ELSIF StatementELSIF Statement
-
8/8/2019 Intoduction au VHDL
43/58
Introduction to VHDLIntroduction to VHDL
The IFThe IF--ELSIF ExampleELSIF Example
dd
-
8/8/2019 Intoduction au VHDL
44/58
The CASEStatement
Introduction to VHDLIntroduction to VHDL
I d VHDLI d VHDL
-
8/8/2019 Intoduction au VHDL
45/58
Introduction to VHDLIntroduction to VHDL
The CASE StatementThe CASE Statement
I d i VHDLI d i VHDL
-
8/8/2019 Intoduction au VHDL
46/58
The FOR Loop
Introduction to VHDLIntroduction to VHDL
I t d ti t VHDLI t d ti t VHDL
-
8/8/2019 Intoduction au VHDL
47/58
ConfigurationsConfigurations
Introduction to VHDLIntroduction to VHDL
Theory behind the configurationTheory behind the configuration
-
8/8/2019 Intoduction au VHDL
48/58
I t d ti t VHDLI t d ti t VHDL
-
8/8/2019 Intoduction au VHDL
49/58
ConfigurationsConfigurations
Introduction to VHDLIntroduction to VHDL
ENTITY mux2to1 ISPORT( d0, d1, s :IN STD_LOGIC;
f :OUTSTD_LOGIC);END mux2to1;
ARCHITECTURE behavior OF mux2to1 IS
BEGIN
WITH s SELECT
f
-
8/8/2019 Intoduction au VHDL
50/58
THE COMPLETE IDEA
Introduction to VHDLIntroduction to VHDL
A complete design hierarchy is defined by multiple entities, which have atA complete design hierarchy is defined by multiple entities, which have at
least one architectureleast one architecture
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
51/58
THE COMPLETE IDEATHE COMPLETE IDEA
Introduction to VHDLIntroduction to VHDL
Each of these entities and architectures will reference standards and typesEach of these entities and architectures will reference standards and types
from within a stated libraryfrom within a stated library
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
52/58
THE COMPLETE IDEATHE COMPLETE IDEA
Introduction to VHDLIntroduction to VHDL
Many of these entities and architectures will reference one or moreMany of these entities and architectures will reference one or more
packages of common definitionspackages of common definitions
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
53/58
THE COMPLETE IDEATHE COMPLETE IDEA
Introduction to VHDLIntroduction to VHDL
The link between each level of hierarchy, and the specification as to whichThe link between each level of hierarchy, and the specification as to which
architecture will be used is provided by the configurationarchitecture will be used is provided by the configuration
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
54/58
A package contains a collection of definitions thatmay be referenced by many designs at the same time
Usage is similar to that of a component
Separate design file that exists outside of the otherdesign units seen thus far, such as entities and
architectures
Introduction to VHDLIntroduction to VHDL
Packages
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
55/58
User DefinedTypes
Types can also be defined by the user
A user defined type is known as an enumerated
type
Types are most commonly defined inside a package,architecture, or process
Most synthesis tools are able to synthesize VHDLcontaining enumerated types
Introduction to VHDLIntroduction to VHDL
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
56/58
Syntax for declaring a user defined type
Introduction to VHDLIntroduction to VHDL
User DefinedTypesUser DefinedTypes
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
57/58
Having defined a type, signals can be
defined of that type SIGNAL state cannot be assigned anything
which is not of type my_state
Introduction to VHDLIntroduction to VHDL
User DefinedTypesUser DefinedTypes
Introduction to VHDLIntroduction to VHDL
-
8/8/2019 Intoduction au VHDL
58/58
Synthesis tools build logic from a signal which is of anenumerated type Usually the minimum number of bits required to
represent the number of possible values
Introduction to VHDLIntroduction to VHDL
User DefinedTypesUser DefinedTypes