Jan M. Rabaey
Low Power Design Essentials ©2008 Chapter 3
Power and Energy Basics
Low Power Design Essentials ©2008 3.2
Chapter Outline
Metrics Dynamic power Static power Energy-delay trade-off’s
Low Power Design Essentials ©2008 3.3
Metrics
Delay (sec):– Performance metric
Energy (Joule)– Efficiency metric: effort to perform a task
Power (Watt)– Energy consumed per unit time
Power*Delay (Joule)– Mostly a technology parameter – measures the efficiency of
performing an operation in a given technology Energy*Delay = Power*Delay2 (Joule-sec)
– Combined performance and energy metric – figure of merit of design style
Other Metrics: Energy-Delayn (Joule-secn)– Increased weight on performance over energy
Low Power Design Essentials ©2008 3.4
Where is Power Dissipated in CMOS?
Active (Dynamic) power– (Dis)charging capacitors– Short-circuit power
Both pull-up and pull-down on during transition
Static (leakage) power– Transistors are imperfect switches
Static currents– Biasing currents
Low Power Design Essentials ©2008 3.5
Active (or Dynamic) Power
Sources: Charging and discharging capacitors Temporary glitches (dynamic hazards) Short-circuit currents
Key property of active power:
fPdyn with f the switching frequency
Low Power Design Essentials ©2008 3.6
Charging Capacitors
210 CVE
2
2
1CVER
R
CV
2
2
1CVEC
Applying a voltage step
Value of R does not impact energy!
Low Power Design Essentials ©2008 3.7
Applied to Complementary CMOS Gate
One half of the power from the supply is consumed in the pull-up network and one half is stored on CL
Charge from CL is dumped during the 10 transition Independent of resistance of charging/discharging network
Vdd
Vout
iL
CL
PMOS
NETWORK
NMOS
A1
AN
NETWORK
210 DDLVCE
2
2
1DDLR VCE
2
2
1DDLC VCE
Low Power Design Essentials ©2008 3.8
Circuits with Reduced Swing
C
0→V - VTH
V
0→V
€
E0→1 = VC0
∞
∫ dVC
dtdt = CV dVC
0
V −VT
∫ = CV (V −VTH )
Energy consumed is proportional to output swing
Low Power Design Essentials ©2008 3.9
Charging Capacitors - Revisited
RC EEE 10
2)( CVT
RCER
R
CI
2
2
1CVEC
Driving from a constant current source
22
0
)()( CVT
RCTRIdtRIIE
I
CVT
R
Energy dissipated in resistor can be reducedby increasing charging time T (that is, decreasing I)
Low Power Design Essentials ©2008 3.10
Charging Capacitors
Using constant voltage or current driver?
Energy dissipated using constant current charging can be made arbitrarily small at the expense of delay:Adiabatic charging
Econstant_current < Econstant_voltage
if
T > 2RC
Note: tp(RC) = 0.69 RC t0→90%(RC) = 2.3 RC
Low Power Design Essentials ©2008 3.11
Charging Capacitors
Driving using a sine wave (e.g. from resonant circuit)
Energy dissipated in resistor can be made arbitrarily smallif frequency w << 1/RC (output signal in phase with input sinusoid)
R
Cv(t)
2
2
1CVEC
Low Power Design Essentials ©2008 3.12
Dynamic Power Consumption
Power = Energy/transition • Transition rate
= CLVDD2 • f01
= CLVDD2 • f • P01
= CswitchedVDD2 • f
Power dissipation is data dependent – depends on the switching probability
Switched capacitance Cswitched = P01CL= a CL(a is called the switching activity)
Low Power Design Essentials ©2008 3.13
Impact of Logic Function
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
Example: Static 2-input NOR gate
Assume signal probabilities pA=1 = 1/2 pB=1 = 1/2
Then transition probability p01 = pOut=0 x pOut=1
= 3/4 x 1/4 = 3/16
aNOR = 3/16
If inputs switch every cycle
NAND gate yields similar result
Low Power Design Essentials ©2008 3.14
Impact of Logic Function
A B Out
0 0 0
0 1 1
1 0 1
1 1 0
Example: Static 2-input XOR Gate
Assume signal probabilities pA=1 = 1/2 pB=1 = 1/2
Then transition probability p01 = pOut=0 x pOut=1
= 1/2 x 1/2 = 1/4
P01 = 1/4
If inputs switch in every cycle
Low Power Design Essentials ©2008 3.15
Transition Probabilities for Basic Gates
p01
AND (1 - pApB)pApB
OR (1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB))
XOR (1 - (pA +pB – 2pApB))(pA + pB – 2pApB)
Activity for static CMOS gatesa = p0p1
As a function of the input probabilities
Low Power Design Essentials ©2008 3.16
Activity as a Function of Topology
aNOR,NAND = (2N-1)/22N aXOR = 1/4
XOR versus NAND/NOR
XOR
NAND/NOR
Low Power Design Essentials ©2008 3.17
How about Dynamic Logic?
Energy dissipated when effective output is zero!
or P0→1 = P0
VDD
Eval
Precharge
Always larger than P0P1!
Activity in dynamic circuits hence always higher than static.But … capacitance most often smaller.
E.g. P0→1(NAND) = 1/2N ; P0→1(NOR) = (2N-1)/2N
Low Power Design Essentials ©2008 3.18
Differential Logic?
VDD
Out Out
Gate
Static: Activity is doubled Dynamic: Transition probability is 1!
Hence: power always increases.
Low Power Design Essentials ©2008 3.19
Evaluating Power Dissipation of Complex Logic
Simple idea: start from inputs and propagate signal probabilities to outputs
But:– Reconvergent fanout– Feedback and temporal/spatial correlations
0.10.50.9
0.1
0.1
0.5
0.5
0.045
0.25
0.99 0.989
P1
Low Power Design Essentials ©2008 3.20
Reconvergent Fanout (Spatial Correlation)
A
B
XZ
PZ = 1- PA . P(X|A) = 1
Becomes complex and intractable real fast
Inputs to gate can be interdependent (correlated)
no reconvergence
PZ = 1-(1-PA)PB
A XZ
reconvergent
PZ = 1-(1-PA)PA ?NO!
PZ = 1
reconvergence
Must use conditional probabilities
PZ: probability that Z=1
probability that X=1 given that A=1
Low Power Design Essentials ©2008 3.21
Temporal Correlations
Activity estimation the hardest part of power analysis Typically done through simulation with actual input
vectors (see later)
R LogicX
Feedback
X is a function of itself→ correlated in time
Temporal correlation ininput streams
01010101010101…00000001111111…
Both streams have same P = 1 but different switching statistics
Low Power Design Essentials ©2008 3.22
Glitching in Static CMOS
ABC 101 000
X
Z
Gate Delay
The result is correct,but extra power is dissipated
A
BX
ZC
Glitch
Analysis so far did not include timing effects
Also known as dynamic hazards:“A single input change causing multiple changes in the output”
Low Power Design Essentials ©2008 3.23
Example: Chain of NAND Gates
1Out1 Out2 Out3 Out4 Out5
0 200 400 6000.0
1.0
2.0
3.0
Time (ps)
Out8
Out6
Out2
Out6
Out1
Out3
Out7
Out5
Vol
tage
(V
)
Low Power Design Essentials ©2008 3.24
What Causes Glitches?
A
B
C
D
Y
Z
X
A,B
C,D
X
Y
Z
A
B
D
C
X
ZY
A,B
C,D
X
Y
Z
Uneven arrival times of input signals of gate due tounbalanced delay pathsSolution: balancing delay paths!
Low Power Design Essentials ©2008 3.25
Short-Circuit Currents
(also called crowbar currents)
Vin Vout
CL
VDD
Isc
vin
VDD -VT
ishort
VT
t
t
Ipeak
PMOS and NMOS simultaneously on during transition
Psc ~ f
Low Power Design Essentials ©2008 3.26
Short-Circuit Currents
Equalizing rise/fall times of input and output signals limits Psc to 10-15% of the dynamic dissipation
Large load Small load
VinVout
CL
VDD
Isc~ 0
VinVout
CL
VDD
Isc= IMAX
time (s)0 20
-0.5
0
0.5
1
1.5
2
2.5
40 60
I sc (
A)
x 10 -4
CL = 20 fF
CL = 100 fF
CL = 500 fF
[Ref: H. Veendrick, JSSC’84]
Low Power Design Essentials ©2008 3.27
Modeling Short-Circuit Power
Can be modeled as capacitor
)( bakCout
inSC
a, b: technology parameters
k: function of supply and threshold voltages, and transistor sizes
2DDSCSC VCE
Easily included in timing and power models
Low Power Design Essentials ©2008 3.28
Transistors Leak
Drain leakage– Diffusion currents– Drain-induced barrier lowering (DIBL)
Junction leakages– Gate-induced drain leakage (GIDL)
Gate leakage– Tunneling currents through thin oxide
Low Power Design Essentials ©2008 3.29
Sub-threshold Leakage
Off-current increases exponentially when reducing VTH
S
V
leak
TH
W
WII
100
0 Pleak = VDD.Ileak
Low Power Design Essentials ©2008 3.30
Sub-Threshold Leakage
Leakage current increases with drain voltage(mostly due to DIBL)
S
VV
leak
DSdTH
W
WII
100
0 (for VDS > 3 kT/q)
Hence
)10)(10(0
0S
V
DDS
V
leak
DDdTH
VW
WIP
Leakage Power strong function of supply voltage
Low Power Design Essentials ©2008 3.31
Stack Effect
NAND gate:
Assume that body effect in shortchannel transistor is small
S
VV
Mleak
MdTH
II
1002,
S
VVVV
Mleak
MDDdTHM
II)(
01, 10
DDd
dM VV
21
)21
1(
10 d
dDDd
S
V
inv
stack
I
I
(instead of theexpected factor of 2)
VDD
Low Power Design Essentials ©2008 3.32
Stack Effect
factor 9
Leakage Reduction
2 NMOS 9
3 NMOS 17
4 NMOS 24
2 PMOS 8
3 PMOS 12
4 PMOS 16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.5
1
1.5
2
2.5
3x 10
-9
VM (V)
I lea
k (A
) IM1 IM2
90 nm NMOS
Low Power Design Essentials ©2008 3.33
Gate Tunneling
IGD~ e-ToxeVGD, IGS~ e-ToxeVGS
Independent of the sub-threshold leakage
V DD 0V
V DD
I SUB
I GD
IGS
ILeak
Exponential function of supply voltage
Modeled in BSIM4Also in BSIM3v3 (but not always included in foundry models)NMOS gate leakage usually worse than PMOS
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
x 10-10
VDD (V)
I gat
e (A
)
90 nm CMOS
Low Power Design Essentials ©2008 3.34
Other sources of static power dissipation
Diode (drain-substrate) reverse bias currents
n well
n+n+ n+p+p+p+
p substrate
• Electron-hole pair generation in depletion region of reverse-biased diodes
• Diffusion of minority carriers through junction• For sub-50nm technologies with highly-doped pn junctions,
tunneling through narrow depletion region becomes an issue Strong function of temperature
Much smaller than other leakage components in general
Low Power Design Essentials ©2008 3.35
Other sources of static power dissipation
Circuit with dc bias currents:
Should be turned off if not used, or standby current should be minimized
sense amplifiers, voltage converters and regulators, sensors, mixed-signal components, etc
Low Power Design Essentials ©2008 3.36
Summary of Power Dissipation Sources
a – switching activity CL – load capacitance
CCS – short-circuit capacitance
Vswing – voltage swing
f – frequency
DDLeakDCDDswingCSL VIIfVVCCP ~
IDC – static current
Ileak – leakage current
powerstaticrateoperation
energyP
Low Power Design Essentials ©2008 3.37
The Traditional Design Philosophy
Maximum performance is primary goal– Minimum delay at circuit level
Architecture implements the required function with target throughput, latency
Performance achieved through optimum sizing, logic mapping, architectural transformations.
Supplies, thresholds set to achieve maximum performance, subject to reliability constraints
Low Power Design Essentials ©2008 3.38
CMOS Performance Optimization
Sizing: Optimal performance with equal fanout per stage
Extendable to general logic cone through ‘logical effort’ Equal effective fanouts (giCi+1/Ci) per stage Example: memory decoder
CL
CL
predecoder
3 15
CW
word driver
addrinput
wordline
[Ref: I. Sutherland, Morgan-Kaufman‘98]
Low Power Design Essentials ©2008 3.39
Model not Appropriate Any Longer
Traditional scaling model
CVDDf2 3.1)7.0
1()7.0()14.1
7.0
1(Power 22
1),
7.0(Freqand,7.0VDDIf
CVDD 8.1)2()7.0()14.17.0
1(fPower
,2Freqand,7.0VDDIf222
CVDD 7.2)2()85.0()14.17.0
1(fPower
,2Freqand,85.0VDDIf222
Maintaining the frequency scaling model
While slowing down voltage scaling
Low Power Design Essentials ©2008 3.40
The New Design Philosophy
Maximum performance (in terms of propagation delay) is too power-hungry, and/or not even practically achievable
Many (if not most) applications either can tolerate larger latency, or can live with lower than maximum clock-speeds
Excess performance (as offered by technology) to be used for energy/power reduction
Trading off speed for power
Low Power Design Essentials ©2008 3.41
12
34
-0.400.4
0.8
0
0.2
0.4
0.6
0.8
1x 10
-4
VTH (V)
VDD (V)
Po
wer
(W
)
A
B
12
34
-0.400.40.8
0
1
2
3
4
5x 10
-10
Del
ay (
s)VTH (
V)VDD (V)
AB
For a given activity level, power is reduced while delay is unchanged if both VDD and VTH are lowered such as from A to B.
Relationship Between Power and Delay
[Ref: T. Sakurai and T. Kuroda, numerous references]
Low Power Design Essentials ©2008 3.42
The Energy-Delay Space
VTH
VD
D
Equal performance curves
Energy minimum
Equal energy curves
Low Power Design Essentials ©2008 3.43
Energy-Delay Product as a Metric
delay
energy
energy-delay
90 nm technologyVTH approx 0.35V
Energy-delay exhibits minimum at approximately 2 VTH
(typical unless leakage dominates)
0.6 0.7 0.8 0.9 1 1.1 1.20
0.5
1
1.5
2
2.5
3
3.5
VDD
Low Power Design Essentials ©2008 3.44
In energy-constrained world, design is trade-off process
♦ Minimize energy for a given performance requirement
♦ Maximize performance for given energy budget
Delay
Unoptimized design
DmaxDmin
Energy
Emin
Emax
Exploring the Energy-Delay Space
Pareto-optimaldesigns
[Ref: D. Markovic, JSSC’04]
Low Power Design Essentials ©2008 3.45
Summary
Power and energy are now primary design constraints
Active power still dominating for most applications– Supply voltage, activity and capacitance the key
parameters
Leakage becomes major factor in sub-100nm technology nodes– Mostly impacted by supply and threshold voltages
Design has become energy-delay trade-off exercise!
Low Power Design Essentials ©2008 3.46
References
D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Methods for True Energy-Performance Optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective,” 2nd ed, Prentice Hall 2003.
Takayasu Sakurai, ”Perspectives on power-aware electronics,” Digest of Technical Papers ISSCC, pp. 26-29, Febr. 03.
I. Sutherland, B. Sproull, and D. Harris, “Logical Effort”, Morgan Kaufmann, 1999.
H. Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits,” IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 4, pp.468–473, 1984.