Download - Jonathan Bromley Doulos

1

Copyright © 2008 by Doulos. All rights reserved.

The Verification Methodology Landscape

Jonathan Bromley, Doulos

DVClub Bristol 22-April-2009

2


The Verification Methodology Landscape

CONTENTS

The M-word

Languages, methodologies, tools and standards

The big players: OVM, VMM, eRM

Interoperability and convergence

Conclusions?

3


TLMDUT

Monitor

Driver

Verification Environment

Stimulusgenerator

Transactions

Coveragecollector

Transactionrecording

Testcontroller

Scoreboard / Checker

4


Design UnderTest

Design UnderTest

Constrained Random Verification

11001001010010100000100101110110011001100100100101001110

11001001010010100000100101110110011001100100100101001110

000010010011000010100100001000110010000011

000010010011000010100100001000110010000011

Constrained random stimulus

CheckerChecker

Did we see a bug?Did we see a bug?

Functional Coverage

Functional Coverage

Are we done?Are we done?HeaderHeader PayloadPayload ChecksumChecksum

Constraints

Increase coverageIncrease coverage

5


The Verification Space

Verification

Acceleration + Emulation

Formal Verification

SimulationEquivalence

CheckingProperty Checking

Dynamic Formal

CoverageTransaction

Level ModellingConstrained

RandomAssertions

Simulation SimulationSimulation

FormalSimulation

Formal

Intelligent Testbench

6


What Our Customers Want

• Ease of deployment• Customizable environment

• but it must do something useful straight out of the box

• Simple, uniform interface to any verification IP block

• Gentle learning curve for the whole team

• Power• Complex testcases co-ordinated across the whole environment

• Randomization

• Sophisticated coverage analysis

• Interoperability• Every customer we meet has legacy verification IP

7


Methodology (or just a toolkit?)

• Tame the language monster• e, SystemVerilog, C++ are big and complicated

• Many ways to solve a problem

• Wheel reinvention is a hazard

• Toolkit• OOP encourages encapsulation of standard functionality

in base classes

• Ideal for component hierarchy, reporting, block-to-block communication, DUT connectivity

• Methodology• Published methodology encourages interoperability and re-use

• Promote best practice

8


Mature Language Standards

• IEEE 1076 VHDL

• IEEE 1850™ PSL

• IEEE 1364 Verilog

• IEEE 1800™ SystemVerilog

• IEEE 1647™ e

• ISO/IEC 14882 C++

• IEEE 1666™ SystemC

• Tcl/Tk, Perl

List unchanged for 4 years...

8

FPGA, RTL, Europe, Mil-Aero

ASIC, RTL, USA/RoW

Hardware verification

Virtual hardware prototypes for S/W dev

Hardware verification

Crude Caricature

Modelling, verification

Scripting

9


New Standards Activity

• Verilog and SystemVerilog unified

• LRM this year, currently in ballot feedback

• Major enhancements to assertions

• Verification methodology

• OVM 2.0, OVM-SC

• VMM open-source

• eRM3 - e / SV interoperability (Cadence)

• OVM / VMM interoperability (Accellera)

• SystemC TLM-2.0

10


The Big Methodology Players

www.ovmworld.org

www.vmmcentral.org

www.cadence.comeRM

11


Environment

Static View of Testbench

DUT

activeagent

DriverBFM

MonitorBFM

Sequ-encer

passiveagent

DriverBFM

MonitorBFM

Sequ-encer

checkerConfiguration

simple ports (e)virtual interfaces (SV)

eRM

12


Static View of Testbench (VMM)

DUT

Generator

...test_env env = new;env.run();...

Transactor

Driver

Self Check

Monitor

High leveltransactions

Checker

MonitorFunctionalCoverage

Properties Checker

Atomictransactions

Constraints;directed tests

13


OVM Key Features

• Constrained random, coverage-driven verification

• Separation of tests from verification environment

• Configuration of verification environment

• through a table

• Verification IP reuse (canonical structure and guidelines)

• TLM communication

• Automation (where missing from SystemVerilog language)

• Hierarchical sequential stimulus (sequences)

• Standardized messaging

14


eRM Key Features


• Separation of tests from verification environment


• through AOP extension and pre-run constraints

• Verification IP reuse (rigorously standardized rules)

• Communication via ports

• Automation (using e language's macro features)

• Hierarchical sequential stimulus (sequences)


15


VMM Key Features



• through configuration objects passed to verification components

• Verification IP reuse (conventions)

• Communication via channels, callbacks, notifications

• Automation (scripts and macros)

• Hierarchical sequential stimulus (scenarios)


• Strongly influenced by RVM (Synopsys Vera)

16


Structure of an OVM Component

class my_driver extends ovm_driver #(my_transaction); // ovm_seq_item_pull_port #(...) seq_item_port; my_dut_if_wrapper m_dut_if;

function new(string name, ovm_component parent); super.new(name, parent); endfunction: new

function void build; super.build(); endfunction: build

virtual task run; forever begin ... end endtask: runendclass: my_driver

class my_driver extends ovm_driver #(my_transaction); // ovm_seq_item_pull_port #(...) seq_item_port; my_dut_if_wrapper m_dut_if;

function new(string name, ovm_component parent); super.new(name, parent); endfunction: new

function void build; super.build(); endfunction: build

virtual task run; forever begin ... end endtask: runendclass: my_driver

TLM port (inherited)

Connection to DUT

Constructor

Build phase callback

Run phase callback

Base class

17


Phase Methods (OVM)

buildbuild

connectconnect

end_of_elaborationend_of_elaboration

start_of_simulationstart_of_simulation

runrun

extractextract

checkcheck

reportreport

Call factory

Make TLM connections

After connections hardened

Post-processing

Task (executed concurrently)

Get ready to run

Similar phase arrangements in VMM, eRM

18


Reconfigurable Environment (OVM)

DUTDUT

Reusable verification environmentReusable verification environment

ScoreboardScoreboard Virtual sequencer

Virtual sequencer

MonitorMonitorExisting

verification component

Existingverification component



SequencerSequencer

DriverDriver

MonitorMonitor

Config

TestTestTestTest

set_config_*set_config_*

Customize environmentsCustomize environmentsset_inst_override_*set_inst_override_*

set_type_override_*set_type_override_*

Customize typesCustomize types

By type or instance pathBy type or instance path

19


Layered Sequential Stimulus

DUTDUT

Driver Driver Drive transactions into DUT

tx1tx1 tx2tx2 tx3tx3Constrained random sequence of transactions

seq1seq1 seq2seq2seq2seq2Virtual or layered sequences

tx1tx1

Tests enumerate possible top-level sequences

Randomized transactions are not enough

20


ovm_envovm_env

ovm_agentovm_agent

Virtual Sequences

ovm_sequencerovm_sequencer

ovm_driverovm_driver


Component hierarchy Stimulus hierarchy(co-ordinated interfaces)

DUTDUT

dut_ifdut_if

ovm_agentovm_agent


ovm_driverovm_driver

dut_ifdut_if

ovm_sequenceovm_sequence

ovm_sequence_itemovm_sequence_item

ovm_sequenceovm_sequence

21


Scenario Generator (VMM)

Verification environmentVerification environment

Scenario generator

Downstream transactorDownstream transactorgenerator's output channelgenerator's output channel

atomic

scenario_set

burst[1]

[0]

RMW[2]

burst

items

select_scenario

select

copies of itemscopies of items

22


Now and Next

• VMM: rapidly growing collection of "applications"

• register abstraction layer, hierarchy, ...

• OVM/VMM interoperability toolkits/standards

• OVM/eRM mixed-language tools

• OVM-SC

• Increasing availability of verification IP

23


Conclusion

• Interesting times

• standards don't always keep up with user needs

• Challenges for users choosing a new approach:

• tools?

• methodology?

• decisions are not yet completely decoupled

• Training is important:

• VMM, OVM, eRM are not difficult ...

• ... but jump-starting your efforts pays dividends

24


Download - Jonathan Bromley Doulos

Top Related