K2G General Purpose Evaluation Module(EVMK2G)
Technical Reference Manual
Literature Number: SPRUI65June 2016
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Table of Contents
Contents
Preface ........................................................................................................................................ 61 Introduction......................................................................................................................... 7
1.1 Key Features.............................................................................................................. 71.2 Functional Block Diagram ............................................................................................... 81.3 Basic Operation ......................................................................................................... 101.4 System View............................................................................................................. 151.5 Power Supply ........................................................................................................... 171.6 Acronyms ................................................................................................................ 18
2 Functional Description ........................................................................................................ 192.1 Over Voltage Protection Circuit ....................................................................................... 192.2 JTAG Emulation Overview ............................................................................................ 202.3 Board Management Controller (BMC) ............................................................................... 222.4 Clock Distribution ....................................................................................................... 242.5 DDR3L Interface ........................................................................................................ 262.6 NAND Flash ............................................................................................................. 272.7 SPI Flash ................................................................................................................ 282.8 Quad SPI (QSPI) Flash ................................................................................................ 292.9 EEPROM ................................................................................................................ 292.10 SD Card.................................................................................................................. 302.11 eMMC .................................................................................................................... 302.12 Gigabit Ethernet......................................................................................................... 322.13 PCIe ...................................................................................................................... 332.14 Display Interface ........................................................................................................ 332.15 Touch Connector ....................................................................................................... 352.16 Audio Codec............................................................................................................. 352.17 COM8 Connector ....................................................................................................... 362.18 DCAN..................................................................................................................... 362.19 MLB....................................................................................................................... 372.20 USB Host ................................................................................................................ 382.21 USB Dual Role .......................................................................................................... 382.22 UART ..................................................................................................................... 392.23 Audio Expansion Connector........................................................................................... 412.24 Serial Expansion Connector........................................................................................... 422.25 I2C Address Mapping .................................................................................................. 432.26 McASP Configuration .................................................................................................. 44
3 EVM Board Physical Specifications ...................................................................................... 453.1 Mounting of LCD and Spacers........................................................................................ 453.2 Board Layout ............................................................................................................ 473.3 Connector Index ........................................................................................................ 493.4 Switches ................................................................................................................. 613.5 Test Points............................................................................................................... 64
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Contents
3.6 System LEDs............................................................................................................ 654 System Power Requirements ............................................................................................... 67
4.1 Power Distribution Diagram ........................................................................................... 674.2 Power Supply Calculation ............................................................................................. 684.3 Power-Up Sequence ................................................................................................... 69
5 EVM with Audio Daughter Card ............................................................................................ 705.1 K2G Audio Daughter Card Block Diagram .......................................................................... 715.2 EVM with Audio Daughter Card Connections....................................................................... 72
6 EVM Important Notice ......................................................................................................... 74
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List of Figures
List of Figures1 EVMK2G Functional Block Diagram ...................................................................................... 92 EVMK2G Board Assembly Pictorial - Top View........................................................................ 153 EVMK2G Board Assembly Pictorial - Bottom View .................................................................... 164 Over Voltage Protection Circuit........................................................................................... 195 Fault Indication Circuit ..................................................................................................... 196 Display and Trace Resistor Multiplexing ................................................................................ 207 JTAG Interface Block Diagram ........................................................................................... 218 Board Management Controller (BMC) Block Diagram................................................................. 239 66AK2G02 SoC Clocks Block Diagram ................................................................................. 2410 Other Clocks Block Diagram.............................................................................................. 2511 DDR3L Interface Block Diagram ......................................................................................... 2612 NAND Flash Block Diagram .............................................................................................. 2713 SPI Flash Block Diagram.................................................................................................. 2814 Quad SPI (QSPI) Flash Block Diagram ................................................................................. 2915 EEPROM Interface Block Diagram ...................................................................................... 2916 SD/MMC Interface Block Diagram ....................................................................................... 3017 eMMC Interface Block Diagram .......................................................................................... 3018 eMMC and COM8 Resistor Multiplexing ................................................................................ 3119 Gigabit Ethernet Interface Block Diagram .............................................................................. 3220 PCIe Interface Block Diagram ............................................................................................ 3321 Display Interface Block Diagram ......................................................................................... 3422 Touch Interface Block Diagram........................................................................................... 3523 Audio Codec Interface Block Diagram................................................................................... 3524 COM8 Connector Interface Block Diagram ............................................................................. 3625 DCAN Interface Block Diagram .......................................................................................... 3626 MLB Interface Block Diagram............................................................................................. 3727 USB Host Interface Block Diagram ...................................................................................... 3828 USB Dual Role Interface Block Diagram................................................................................ 3829 UART0 Interface Block Diagram ......................................................................................... 3930 UART1 Interface Block Diagram ......................................................................................... 4031 UART2 Interface Block Diagram ......................................................................................... 4032 Audio Expansion Connector Interface Block Diagram ................................................................ 4133 Serial Expansion Connector Interface Block Diagram ................................................................ 4234 McASP Interface Block Diagram ......................................................................................... 4435 EVMK2G Mechanical Drawing ........................................................................................... 4636 EVMK2G Board Assembly Layout - Top View ......................................................................... 4737 EVMK2G Board Assembly Layout - Bottom View ..................................................................... 4838 EVMK2G Board Connectors .............................................................................................. 5039 LCD (J22) and Touch Screen (J21) Connectors ....................................................................... 5440 EVMK2G Switches ......................................................................................................... 6141 DIP (SW3) Switch .......................................................................................................... 6342 EVMK2G Board LEDs ..................................................................................................... 6643 Power Distribution Diagram ............................................................................................... 6744 Power-Up Sequence Diagram ............................................................................................ 6945 K2G Audio Daughter Card ................................................................................................ 7046 K2G Audio Daughter Card Block Diagram.............................................................................. 7147 Connecting the K2G Audio Daughter Card ............................................................................. 72
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List of Tables
List of Tables1 EVMK2G Regulators....................................................................................................... 172 Acronyms.................................................................................................................... 183 Display and Trace Resistor Multiplexing ................................................................................ 214 Muxing Between BMC UART1 and SOC_UART2 ..................................................................... 225 Muxing Between BMC UART0 to USB and 4-pin Header ............................................................ 226 eMMC and COM8 Resistor Multiplexing ................................................................................ 317 DSS Lines Between LCD and HDMI Multiplexing ..................................................................... 348 HDMI Audio Line Selection Between McASP0 and McASP2 ........................................................ 359 Audio Codec Multiplexing ................................................................................................. 3510 UART0 Multiplexing ........................................................................................................ 3911 UART1 Multiplexing ........................................................................................................ 3912 SoC Address Table ........................................................................................................ 4313 BMC I2C Address Table................................................................................................... 4314 McASP Configuration ...................................................................................................... 4415 EVMK2G Board Connectors .............................................................................................. 4916 COM8 (J2) Pin List......................................................................................................... 5117 PCI Express (J5) Pin List.................................................................................................. 5218 JTAG MIPI-60 (J19) Pin List .............................................................................................. 5319 LCD (J22) and Touch Screen (J21) Pin List............................................................................ 5420 RJ45 Ethernet (J31) Pin List.............................................................................................. 5621 Stereo Analog Audio Input (J32) and Output (J33) Pin List .......................................................... 5622 MLB (J34) Pin List.......................................................................................................... 5723 USB0 Host Type A (J35) Pin List ........................................................................................ 5724 HDMI (J36) Pin List ........................................................................................................ 5825 MMC/SD (J37) Pin List .................................................................................................... 5926 USB1-Micro (J38) Pin List................................................................................................. 5927 DB9 Connector (P1, P2, and P3) Pin List............................................................................... 6028 EVMK2G Tactile Switches ................................................................................................ 6229 Boot Mode Configurations for SW3 ...................................................................................... 6330 EVMK2G Test Points ...................................................................................................... 6431 EVMK2G Board LEDs ..................................................................................................... 6532 Power Supply Calculation ................................................................................................. 68
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Preface
PrefaceSPRUI65–June 2016
Read This First
About This ManualThis technical reference manual (TRM) describes the hardware architecture of the 66AK2G02 GeneralPurpose (GP) Evaluation Module (EVMK2G) designed and developed by Mistral Solutions Pvt. Ltd. The66AK2G02 is a KeyStone™ II-based DSP + ARM System-on-Chip (SoC).
GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas InstrumentsFor product information, visit the Texas Instruments website at http://www.ti.com.
SPRUHY8— 66AK2G02 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) Technical ReferenceManual. Details the integration, the environment, the functional description, and the programmingmodels for each peripheral and subsystem in the device.
Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;see TI's Terms of Use.
TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to fostercollaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to helpdevelopers get started with Embedded Processors from Texas Instruments and to foster innovationand growth of general knowledge about the hardware and software surrounding these devices.
Board History
PCB Revision HistoryRev A Pre-Proto EVM for power, Board management Controller and On-board emulator validation.Rev B Socketed Proto EVM for Silicon bring up.Rev C Modified as per change list MS_TI_EVMK2G_MC_REVC_CHNG_LIST.xlsRev D Over Voltage protection circuit added.
TrademarksKeyStone, E2E, Code Composer Studio, Tiva, WiLink are trademarks of Texas Instruments. ARM, Cortexare registered trademarks of ARM Limited.
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K2G General Purpose Evaluation Module (EVMK2G)
Technical Reference ManualSPRUI65–June 2016
K2G General Purpose Evaluation Module (EVMK2G)
1 IntroductionThis technical reference manual (TRM) describes the hardware architecture of the 66AK2G02 GeneralPurpose (GP) Evaluation Module (EVMK2G) designed and developed by Mistral Solutions Pvt. Ltd. The66AK2G02 is a KeyStone™ II-based DSP + ARM System-on-Chip (SoC).
1.1 Key FeaturesThe EVMK2G is a high-performance, cost-efficient, standalone, general purpose development platformthat enables you to evaluate and develop applications for the Texas Instrument’s Keystone II System-on-Chip (SoC) 66AK2G02.
The EVM comes with an on-board, high-speed XDS200 Emulator.
The K2G SoC (66AK2G02) is the new device from TI’s Keystone II architecture with:• ARM® Cortex®-A15 Microprocessor Unit (ARM A15) Subsystem at up to 600 MHz• TMS320C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600 MHz• Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS)• Multicore Shared Memory Controller (MSMC) with 1024KB of Shared L2 RAM• Up to 36-Bit DDR3 External Memory Interface (EMIF) with ECC (32-Bit Data + 4-Bit ECC)• Peripheral Component Interconnect Express (PCIe) 2.0 Port with Integrated PHY• Three Multichannel Audio Serial Port (McASP) Peripherals• Multichannel Buffered Serial Port (McBSP)• Six Enhanced High-Resolution Pulse Width Modulation (eHRPWM) Modules• Three Inter-Integrated Circuit (I2C) Interfaces• Three Universal Asynchronous Receiver/Transmitter (UART) Interfaces• Four Serial Peripheral Interfaces (SPI)• Seven 64-Bit Timers• Secure Device - Supports Standard secure boot and One-time-Programmable (OTP) memory for key
storage• 21 × 2 mm2 0.8mm pitch WBBGA
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K2G General Purpose Evaluation Module (EVMK2G)
The key features of the EVM are:• Based on the KeyStone II architecture with ARM® Cortex®-A15 @600 MHz and TMS320C66x DSP
@600 MHz• Board Management Controller (BMC) for board management functions like system status and Boot
mode control• 2 GByte of DDR3L with ECC• 2 Gbit of NAND Flash• 128 Mbit of SPI Flash• 512 Mbit of QSPI Flash• 128 kByte of I2C EEPROM for Boot support from I2C• Micro SD-Card slot• 16 GByte of eMMC• Gigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connector• PCIe ×1 card slot• 4.3” LCD display with Capacitive touch (Sold separately)• HDMI transmitter• Audio Line In and Line Out• COM8 interface• DCAN and MLB interfaces• One USB2.0 host and one USB2.0 Dual-role ports• One RS-232 serial interface on DB9 connector or UART over mini-USB connector, One UART
interface on 6-pin header• Audio Daughter Card (Sold separately) plugable to Audio Expansion, Serial Expansion headers• MIPI 60-pin JTAG header to support all types of external emulator• On-board XDS200 Emulator• RoHS compliant design• Powered by DC power-wall adaptor (12V/5A)• ATX form factor (12” × 9.6” )
1.2 Functional Block DiagramThe functional block diagram of the EVMK2G is shown in Figure 1.
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TLV70708LP2996A
PMIC ± TPS659118
PB Switch Bank (4)
DIP Switch Bank (4)
NAND (x16) Flash
66AK2G02SoC
1x PCIe Card-Edge Connector
Serial expansion header
JTAG / EMU[1:0]
GPIO / EMU[19:2]JTAG / EMU Muxes / Buffers
MIPI Connector
JTAGEMU[19:0]
GPIOs
SPI0
Mini USB
CP2105
UART1
Timer 1
I2C0
SmartReflex
Resets / Boot
PCI CE Reference Clock
SYSCLK
DDRCLK
USB0_CLK
24MHz XO
MMC0 (3.3V)
MMC1 (1.8V)
DDR3 EMIF (x36)
DDR3 devices
QSPI
MLB
LCD, touch connectors
DSS-UL
NSS (RGMII)
UART0
SPI1SPI2
CDCM6208
USB1_CLK
I2C1I2C2
McBSP
Quad SPI512 Mbit
Samtec QSH-020-01-L-D-DP-A
PCIe
USB0 ± 2.0pair
USB1 ± 2.0pair
PCIECLK
UART2
SPI3
I2C EEPROM
SPINOR FLASH
USB2.0Type A socket
NSS (MDIO)
Micrel KSZ9031RNX
RJ4525 MHz
XtalMDIO
eMMC
uSDCard
CPTS CS2000
DCAN1
To DSS-UL touch screen
connector
I2C1, GPIO
AUDIOOSC22.5792 MHz Xtal
SYSOSC24 MHz Xtal
DUT Adj. Supply #1AVS Core /´&9''´
(+0.9V)
DUT Adj. Supply #2DSP Core
Fixed Core / ³&9''1"(+0.9V)
SERDES L.V. Supply
³/'2_PCIE/USB_&$3´
(+0.85V)
DUT Adj. Supply #5
³'9''_''5´(+1.35V)
DUT Fixed Supply³''595()667/´
DDR VTT(+0.675V)
DUT Adj. Supply #3³'9''18´
DSP IO / PLL(+1.8V)
DUT Adj. Supply #4³'9''33´
DSP IO
(+3.3V)INA226 INA226 INA226 INA226 INA226
S25FL512S
Timer 0
SiI902
2A
HDMIType A
To DSS-UL connectors, due to pin muxing. Need
isolation in between.
100 MHz (HCSL)
100 MHz (LVDS)
24 MHz (LVCMOS)
CPTSREFCLK
24 MHz (LVDS)
USB2.0Micro-AB
DCAN0
To 2-pin header
CAN xcvr
SN65HVDA54
To DB-9
1588 DAC
TC-VCXO SPI3
SPI3 to 1588 circuit
DB9 Conn
RS232
COM8 connector
To COM8
UART1
Level shifter McASP2
GPIO
Console headerTo BMC
To BMC
McASP2McASP1
McASP0
AIC3106McASP2
3.5mm stereo jacks
To AIC3106
I2C1
GPMCAudio
expansion header
To COM8
eQEP
eHRPWM3, 4, 5eCAP0, 1
To DSS-UL connectors, due to pin muxing.
eHRPWM0, 1, 2
Mini-USB
XDS200
I2C2
BMC
LED x4
16x2 LCD character display
BMC, WARM, FULL RESETS
CP2105
Console header
NOTE: all port numbers within the
BMC block are BMC port numbers, not SoC port numbers.
PH[3:0]
PJ0, PJ1, RSTn
UART0
I2C1To K2G SOC
JTAG14-pin header
SPI1
UART1 RxSoC UART2 Tx
DSS Isolator
To 2-pin header
CAN xcvr
SN65HVDA54
To DB-9
PHY can also be clocked from
RMII_CLK output pin.
Kingston
Switch
Resistor MUX
100 MHz (CML)
250 MHz (LVDS)
Rakon E6718LF
DAC855020 MHz
MT29F2G16ABA
MT41K512M8RH (qty 5)
Y4
Y5
Y3Y2
Y6Y7
To PMIC
I2C1
MAX3221
MINI USB
Temperature Sensor
I2C0 To INA226 x5
McASP0 from ExpansionConnector
SN74AVC4T245PWR
I2C to GPIO expander
TCA9555RTWR
To 5 pin header/BMC
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 1. EVMK2G Functional Block Diagram
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K2G General Purpose Evaluation Module (EVMK2G)
1.3 Basic OperationThe EVMK2G is a full-featured general purpose development tool for the 66AKG02 Keystone II-basedSoC. It supports a comprehensive software including the Texas Instruments Code Composer Studio™(CCS) integrated development environment (IDE) and Processor Software Development Kit (SDK). TheProcessor SDK is a unified software platform for TI embedded processors providing easy setup and fastout-of-the-box access to benchmarks and demos.
The Processor SDK for the EVMK2G can be downloaded from Processor SDK for 66AK2Gx Processors -Linux and TI-RTOS Support.
The latest version of CCS can be downloaded from Code Composer Studio (CCS) IntegratedDevelopment Environment (IDE). It is recommended to use CCS revision 6.1.2 or later with the EVMK2G.
The Processor SDK Linux images are preprogrammed to the SD Card that is shipped with the EVMK2G.Refer to the Processor SDK user guide for more details on running Linux with the EVM.
Refer to documentation available at Processor SDK for 66AK2Gx Processors - Linux and TI-RTOSSupport for instructions on setting up CCS and exploring software packages delivered with the EVMK2G.
NOTE: For TI RTOS users, refer to the Processor SDK RTOS Getting Started Guide.
To boot Linux images and run matrix demonstrations on the board, follow these instructions:1. Set DIP switch (SW3) to 0111 (MSB first), as shown, to select MMC/SD boot mode.
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K2G General Purpose Evaluation Module (EVMK2G)
2. Insert the SD card.
3. Using the Ethernet cable, connect the EVM to a network containing a PC running a DHCP server.
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K2G General Purpose Evaluation Module (EVMK2G)
4. Connect 12V power cable to the DC power jack (J3). Slide the power switch SW1 to the ON positionmarked on the silkscreen. LED LD9 lights.
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K2G General Purpose Evaluation Module (EVMK2G)
5. Note the IP address displayed on the LCD screen. Enter this address into a web browser connectedto the same network as the EVM.
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K2G General Purpose Evaluation Module (EVMK2G)
6. The host PC connects to the EVM, and the demonstration may now be run.
BMCLCD
BMCJTAG
COM8Connector
+12 V DC
BMCController
66AK2G02SoC
PCIeConnector
DCAN0
UART0Over DB9
SoC UART0&
BMC UART0Over USB
BMCUART0
DCAN1
UART2
LCDConnector
HDMIConnector
RJ45Ethernet
Connection
USB0Host
Mini USBFor XDS200
AudioLine Out
TouchConnector
MLBConnector
USB1Dual Role
Micro SD cardConnector
AudioLine In
MiPi 60Connector
Audio ExpansionConnector
Serial ExpansionConnector
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K2G General Purpose Evaluation Module (EVMK2G)
1.4 System ViewThe top and the bottom pictorial views of the EVMK2G are provided in Figure 2 and Figure 3, respectively.
Figure 2. EVMK2G Board Assembly Pictorial - Top View
NANDFlash
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 3. EVMK2G Board Assembly Pictorial - Bottom View
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K2G General Purpose Evaluation Module (EVMK2G)
1.5 Power Supply
NOTE: Always use the power supply (CUI Inc., part number ETSA120500U) or equivalent 12V/5Amodel with the applicable regional product regulatory/safety certification standards such as(by example) UL, CSA, VDE, CCC, PSE, and so on.
The EVMK2G can be powered from a single +12V / 5.0A DC (60W) external power supply connected tothe DC power jack (J3). Internally, +12V input is converted into required voltage levels using local DC-DCconverters. The regulators used in the EVM are listed in Table 1.
Table 1. EVMK2G Regulators
Regulator PurposeTPS54429 3V3 Generation
TPS54620RGY 5V GenerationLM22675MR 3V3 Generation for BMC
TPS650006RTET For on-board emulator circuitryTPS79601DCQR COM8
TPS71712 HDMITPS61081 LCD Backlight
LP3985IM5-3.0 BMC DisplayTPS659118 All voltages for processor
LP2996A DDRTLV707085DQNT PCIe, USB
The power requirements of the processor are met by the TPS659118 (U32) Power Management IC(PMIC). The generation and sequencing requirements of various powers to the 66AK2G02 processor arealso handled by the TPS659118. The TPS659118 is controlled by the I2C0 interface of the 66AK2G02.• Core Voltage
– PMIC_VDD1– PMIC_VDD2– CVDD
• LDO Voltages– LDO1_1V8– LDO2_1V8– LDO3_1V8– LDO4_1V8– LDO5_3V3– LDO6_3V3– LDO7_3V3– LDO8_3V3
• I/O Voltages– PMIC_VIO
• RTC Voltages– VRTC
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1.6 AcronymsTable 2 is a description of some terms used in this document.
Table 2. Acronyms
Acronym DescriptionATX Advanced Technology eXtendedBMC Board Management ControllerCCS Code Composer Studio
DDR3 Double Data Rate 3 InterfaceDSP Digital Signal Processor
eHRPWM Enhanced High-Resolution Pulse Width ModulationEEPROM Electrically-Erasable Programmable Read-Only Memory
EMAC Ethernet Media Access ControllerEMIF External Memory InterfaceEVM Evaluation ModuleI2C Inter-Integrated Circuit
JTAG Joint Test Action GroupLED Light-Emitting Diode
McASP Multichannel Audio Serial PortMMC Module Management ControllerPCIe Peripheral Component Interconnect ExpressSPI Serial Peripheral Interfaces
UART Universal Asynchronous Receiver/TransmitterUSB Universal Serial Bus
XDS200 Texas Instruments’ Emulator
Condition LED Status(LD14)
VINPUT between 11 to 13V&
Current below 5A
ON
OFF
RED
VINPUT above 13V or below 11V&
Current above 5A
PGD
DGND
VINPUTVINPUT
DGND
R925100 K
LD14
598-8110-107F
12
R924
10 K
D18BZT52C13S
21
R923
10 K Q19
BSS138
3
1
2
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Note:-
Vinput nominal = 12VI input max = 5A
RED
Condition
ONReverse Voltage
LED Status(LD15)
PGD
GATE
GATE
DGND DGND
DGND
DGNDDGND DGNDDGND DGND
VCC12V0_DC_IN
DGND
VINPUT
VINPUT
DGND
DGND DGND
VCC12V0_DC_INVINPUT
DGND
+
C23
100uF
_35V
R922
100K
+
C825
22uF_100V
U149
LM5060MM
SENSE1
VIN
2
OVP3
UVLO4
EN5
GN
D6
TIMER7
NPGD8
OUT9
GATE10
R918261K_1%
D19S1G-13-F
21
R9175.62k_1%
LD15598-8110-107F
12
J50
HDR_2X112
R892
0E
R919237K_1%
R92610K
LD9598-8170-107F
12
C827
0.01uF
DNI
F2
5A1 2
D17
SMCJ64CA
21
R92047K _1%
C8260.1uF
R301K
D3
B540C-13-F
2 1
R92147K _1%
Q20 SUM60N10-17-E3
4
1
3
C8240.1uF
C2
22uF
J3
CON_PWRJACK3_RAPC722
1
23
SW1
500ASSP3M2QE
12
3
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K2G General Purpose Evaluation Module (EVMK2G)
2 Functional Description
2.1 Over Voltage Protection CircuitThe Voltage Protection Circuit on the EVMK2G protects the board from over voltage, under voltage,transient voltage, and reverse voltage input cases. The safe operation input voltage range is 11v to 13v.Any voltage not in this range will be considered as fault and the voltage protection circuit will isolate theboard from this input. LED LD14 indicates if the DC input applied to board is in a safe input range.
Figure 4. Over Voltage Protection Circuit
Figure 5. Fault Indication Circuit
MIPI_EMU18MIPI_EMU19
MIPI_EMU17MIPI_EMU16MIPI_EMU14MIPI_EMU11MIPI_EMU15MIPI_EMU10MIPI_EMU12MIPI_EMU13
MIPI_EMU02
MIPI_EMU03
MIPI_EMU04
MIPI_EMU05
MIPI_EMU06
MIPI_EMU07
MIPI_EMU08
MIPI_EMU09
SOC_DSSDATA620SOC_DSSDATA720
BUFF_DSSDATA6 19BUFF_DSSDATA7 19
SOC_DSSDATA520SOC_DSSDATA420 BUFF_DSSDATA4 19
BUFF_DSSDATA5 19
SOC_DSSDATA1920SOC_DSSDATA1720SOC_DSSDATA2220SOC_DSSDATA1620SOC_DSSDATA2320SOC_DSSDATA2120SOC_DSSDATA1820SOC_DSSDATA2020 BUFF_DSSDATA20 19
BUFF_DSSDATA18 19BUFF_DSSDATA21 19BUFF_DSSDATA23 19BUFF_DSSDATA16 19BUFF_DSSDATA22 19BUFF_DSSDATA17 19BUFF_DSSDATA19 19
SOC_DSSDATA820SOC_DSSDATA920SOC_DSSDATA1120SOC_DSSDATA1420SOC_DSSDATA1020SOC_DSSDATA1520SOC_DSSDATA1320SOC_DSSDATA1220 BUFF_DSSDATA12 19
BUFF_DSSDATA13 19BUFF_DSSDATA15 19BUFF_DSSDATA10 19BUFF_DSSDATA14 19BUFF_DSSDATA11 19BUFF_DSSDATA9 19BUFF_DSSDATA8 19
RA8 0E
12345678
161514131211109
RA7 0E
1234 5
678
RA19 10EDNI
12345678
161514131211109
RA17 10EDNI
1234 5
678
RA9 0E
12345678
161514131211109
RA18 10EDNI
12345678
161514131211109
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K2G General Purpose Evaluation Module (EVMK2G)
2.2 JTAG Emulation OverviewThe EVM supports two types of Emulation: On-Board-XDS200 emulator and 60-pin MIPI Header.
When external emulator is not connected to MIPI 60-pin connector, On-board XDS200 embedded JTAGemulator is the default type of emulation (SoC JTAG signals are routed to XDS200 on-board emulator).When external emulator is connected to MIPI 60-pin header, it is automatically detected and SoC JTAGsignals are routed to external emulator.
2.2.1 On-Board XDS200 EmulatorThe EVMK2G has on-board XDS200 embedded JTAG emulation circuitry. Hence user does not requireany external emulator to connect EVM with Code Composer Studio (CCS). You can connect the targetSoC in the EVM to CCS through the USB cable supplied in the EVM kit.
2.2.2 MIPI 60-pin Header for Connecting External EmulatorIn case you want to connect an external emulator to the EVM, the MIPI 60-pin JTAG header is providedon-board for high-speed real-time emulation. All JTAG and EMUx signals are terminated on the MIPI 60-pin header.
The MIPI 60-pin JTAG header supports all standard (XDS510 or XDS560) TI DSP emulators. Refer to thedocumentation supplied with your emulator for connection assistance.
EMU pins are pin muxed with DSS (Display Subsystem) and Boot mode pins. The EMU signals areresistor muxed with DSS signals. A Boot mode buffer is enabled during boot-up to latch the Boot modesignals.
Resistor muxing between display and trace functionality is shown in Figure 6 and Table 3.
Figure 6. Display and Trace Resistor Multiplexing
K2G SoC
CPLD
BUFFER
FET SWICH
RESISTOR
MUX
EMU [00:01]
EMU [02:19]
2
18
SD RAM
AM1802
PROCESSOR
JTAG
SIGNALS
CPLD
I/Os
SPI1 6 A0-11
12
DQ0-15
BA0-1
18
6
6
MIPI - 60
JTAG
SIGNALS
BUFFER
FET
SWITCH
JTAG
SIGNALS
6
6
SPI FLASH
CONTROLSIGNALS
8
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K2G General Purpose Evaluation Module (EVMK2G)
Table 3. Display and Trace Resistor Multiplexing
DNI Mount DescriptionRA17, RA18, RA19 RA7, RA8, RA9 For HDMI/LCD display (default)
RA7, RA8, RA9 RA17, RA18, RA19 For Trace
The JTAG interface, on-board XDS200 emulator, MIPI 60-pin header for external emulator connectiondetails are shown in Figure 7.
Figure 7. JTAG Interface Block Diagram
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K2G General Purpose Evaluation Module (EVMK2G)
2.3 Board Management Controller (BMC)The Tiva™ C Series ARM® Cortex®-M4 microcontroller TM4C129XNCZAD is used as a boardmanagement controller for the EVMK2G. The BMC controls the SoC boot sequence and displays thestatus on the character LCD interfaced to the BMC. The BMC facilitates the selection of Boot mode, resetsettings, and configuring clock generators.
The JTAG interface is provided to access and program the BMC controller. Note that the BMC is usedmainly for EVM test automation and, in general, is not required for customer products.
The push buttons, DIP switches, and LEDs are connected to the BMC by way of GPIOs. The 4-bit DIPswitch is used to set the processor boot mode, the three push buttons are for reset, and the remaining areuser configurable.
Isolators are used between the BMC and SoC peripherals. The BMC is interfaced to the SoC throughI2C1 and UART1. The BMC I2C0 is interfaced to the INA devices for processor current monitoring. TheBMC UART0 is muxed between the 4-pin header through RS-232 level translator and the CP2105 forconsole purpose.
Table 4. Muxing Between BMC UART1 and SOC_UART2
Signal Logic SoC UART 2 Connected To
BMC_UART_SELHigh UART2 header (J49)Low BMC
Table 5. Muxing Between BMC UART0 to USB and 4-pin Header
Signal Logic BMC_UART0 Pins Connected To
BMC_UART0_DETECTHigh USB-to-UART module CP2105Low BMC console 4-pin header (J6)
CDCM6208
ISOLATOR x4
BMC
DC-DC
LM22675
DIP
Switch
LED
LCD
128 X 32
Pixels
DC_DC
TPS54429ERSAREN
Push
Button
x6
MUX/Buffer
PMIC DC_DC
TPS54429ERSAR
Buffer
Buffer
Isolator
Isolator
5 Pin HDR
INA226 x5
12V
12 V
12V
MAX3221
SPI1
GPIOs
4
EN
GPIOs
SPI0
23 GPIOs
2
JTAG Lines
I2C1
I2C0
INT1
BMC_RESETn
5
INT
UART1
DSS[8:23]
16
UART0
3.3V
CP2105
4 Pin HDR
K2G SoC
I2C2
I2C0
CVDD
CVDD1
DVDD_DDR
3.3V
-Mini USB
SoC_INT
BMC_INT
UART2
BOOT MODE SIGNALS
JTAG
14 Pin
ConnectorGPIOs
SOC,
DEVICES
RESET &
CTRL
Signals
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K2G General Purpose Evaluation Module (EVMK2G)
The BMC is powered from 12V through the LM22675 DC-DC regulator. The connection details are shownin Figure 8.
Figure 8. Board Management Controller (BMC) Block Diagram
Y8
CDCM6208
PCIe x1 Connector
K2G SoC
CS2000
CLKOUT
Y7
CLKIN
PCIe_CLK_100MHz
AUDOSC_IN
AUDOSC_OUT
SYSOSC_IN
SYSOSC_OUT
CPTS_TS_COMP
SYSCLOCK
CPTS_REFCLK
DDR_CLK
PCIe_CLK
McASP2AHCLK
24 MHz
250 MHz
24 MHz
100 MHz
100 MHz
Y5
Y6
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K2G General Purpose Evaluation Module (EVMK2G)
2.4 Clock DistributionThe EVMK2G has the following clock sources, crystals, and oscillators.• 66AK2G02 SoC clocks (see Figure 9):
– Y5: 22.579 MHz Audio clock for SoC– Y6: 24 MHz System clock to the SoC– Y7: 12.28 MHz to CS2000– Y8: 24 MHz Secondary Reference for clock generator– U62: CDCM clock generator
• Other clocks (see Figure 10):– Y1: 32.768 kHz to AM1802 XDS– Y2: 24 MHz System clock to AM1802 XDS– Y3: 25 MHz Clock to BMC Controller– Y4: 32.768 kHz Real-Time Clock (RTC) to Power Management IC (TPS659118)– Y9: 25 MHz Clock for Ethernet PHY– U21: 32.768 kHz Real-Time Clock (RTC) to BMC– U75: 12.28 MHz oscillator for audio clocks
Figure 9. 66AK2G02 SoC Clocks Block Diagram
Y4
AM1802
PMIC
Audio Codec
HDMI TX
32.768 kHz
BMC
12.288MHz
Y2
Y1
Y9
Y3
KSZ9031RNX
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 10. Other Clocks Block Diagram
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K2G SoC
DDR3L
MT41K512M8RH-125:E
DDR3LMT41K512M8RH
-125:E
DDR3LMT41K512M8RH
-125:E
DDR3LMT41K512M8RH
-125:E
DDR3LMT41K512M8RH
-125:E
DD
R3C
LK0
CE
0#
RA
S#
A0-A
15
BA
0-BA
2
CK
E0#
CA
S#
RE
SE
T#
WE
#
OD
T0
DVDD_DDR
1.35V
CBDQM
CBDQS
CB00-CB03
DQM3
DQS3
DQ24-DQ31
DQM2
DQS2
DQ16-DQ23
DQM1
DQS1
DQ8-DQ15
DQM0
DQS0
DQ0-DQ7
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K2G General Purpose Evaluation Module (EVMK2G)
2.5 DDR3L InterfaceThe 66AK2G02 SoC supports ×36 bit (32-bit data + 4-bit ECC) DDR3L. Four 4-Gbit (512M × 8) DDR3Lchips (MT41K512M8RH-125) from Micron are used to obtain a memory size of 2GByte and one DDR3Lchip is interfaced to the ECC data bus CB00-CB03, CBDQS, and CBDQM. The DDR3L chips are routedas per Fly-by topology as shown in Figure 11.
Figure 11. DDR3L Interface Block Diagram
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NAND FLASHMT29F2G16ABA
K2G SoC
GPMC_AD [0:15]
GPMC_ADVn_ALE
GPMC_BEn0_CLE
GPMC_OEn_REN
GPMC_WEn
GPMC_WPn
GPMC_CSn0
GPMC_WAIT0
3.3 V
I/O
ALE
CLE
#RE
#WE
#WP
#CE
R/B#
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K2G General Purpose Evaluation Module (EVMK2G)
2.6 NAND Flash2-Gbit NAND Flash (MT29F2G16ABA) from Micron with a 16-bit data width is interfaced to the processorGPMC (General-Purpose Memory Controller) interface. The NAND Flash is interfaced to GPMC chipselect 0.
The connection details are as shown in Figure 12. The operating voltage of the GPMC interface andNAND flash is 3.3v.
Figure 12. NAND Flash Block Diagram
K2G SoC
SPI FLASH
N25Q128A13ESF40F
RESET#
BMC
AND GATE
SOC_RESETSTATz
FLASH_WP#
FLASH_RESET#
3.3 V
GPIO
SPI1_MOSI
SPI1_CSn0
SPI1_MISO
SPI1_CLK
Q
#S
D
#HOLD
C
#W
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K2G General Purpose Evaluation Module (EVMK2G)
2.7 SPI FlashThe SPI Flash (N25Q128A13ESFESF40F) from Micron is a 128-Mbit Serial Flash interfaced as shown inFigure 13. The Serial Flash is interfaced to the SPI1 port of the processor and is connected to chipselect 0.
The write protection for the Flash is controlled by the BMC. The Hold signal (to pause the serialcommunication without deselecting the device) is connected to SoC GPIO with a default pull-up.
Figure 13. SPI Flash Block Diagram
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K2G SoC
EEPROMAT24CM01
EEPROM_WP
WP
I2C2_SDA
I2C2_SCL
3.3 V
SCL
SDA
BMC
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RESET#
QSPI FLASHS25FL512S
K2G SoC
AND GATE
SOC_RESETSTAT
QSPI_RSTn
QSPI_RCLK
QSPI_D3
QSPI_D0
QSPI_CSn0
QSPI_CLK
QSPI_D1
QSPI_D2I/O1
CS#
SCK
I/O3
I/O2
I/O0
3.3 V
BMC
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K2G General Purpose Evaluation Module (EVMK2G)
2.8 Quad SPI (QSPI) FlashThe Quad SPI (QSPI) Flash is a 512-Mbit device (S25FL512S) from Spansion interfaced as shown inFigure 14. The reset signal for the QSPI Flash is connected to the BMC. The Quad SPI Flash is interfacedto chip select 0 of the QSPI interface on the processor.
Figure 14. Quad SPI (QSPI) Flash Block Diagram
2.9 EEPROMThe Atmel AT24CM01 provides 1Mb of Serial Electrically-Erasable and Programmable Read-OnlyMemory (SEEPROM). This is interfaced to I2C0 port of the processor as shown in Figure 15. The deviceaddress is set by the two address pins A1 and A2 that are connected to ground to give a 7-bit address0x50. The Write protect pin of the EEPROM is connected to a GPIO of the BMC.
Figure 15. EEPROM Interface Block Diagram
eMMC
(eMMC16G-S100) K2G SoC
MMC1_CLK
MMC1_CMD
CMD
CLK
MMC1_D [0-8]
D [0-8]
MMC1_CLK
MMC1_CMD
MMC1_D [0-4]
COM8
Connector
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ESD
DIODES
MICROSD CARD
CONN
K2G SoC
3.3 V
MMC0_CLKMMC0_CMD
MMC0_D [0-3]MMC0_SDCD
CMDCLK
D[0-3]CD
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K2G General Purpose Evaluation Module (EVMK2G)
2.10 SD CardMicro SD Card connector is connected to MMC0 interface of the processor as shown in Figure 16. ESDprotection circuits are included for all the connector pins that are prone to ESD. Refer to Section 3.3.12 forSD Card connector pin outs.
Figure 16. SD/MMC Interface Block Diagram
2.11 eMMCThe eMMC flash chip from Kingston (16GB) is interfaced with MMC1 of the processor as shown inFigure 17. MMC1 is muxed between the eMMC Flash and the COM8 connector. By default, MMC1 isconnected to eMMC.
Resistor muxing between eMMC and COM8 is shown in Figure 18 and Table 6.
Figure 17. eMMC Interface Block Diagram
DGND
NOTE: MMC1 IS BY DEFAULT CONNECTED TO EMMC. IF COM8 TO BE USED RESISTOR RA6, R387 AND R822SHOULD BE DNI AND RQZZ+15, R713, R714 & R393 SHOULD BE MOUNTED
SOC_MMC1_CLKSOC_MMC1_CMD
SOC_MMC1_DAT0
SOC_MMC1_DAT3SOC_MMC1_DAT2SOC_MMC1_DAT1
BUF_MMC1_DAT0 23BUF_MMC1_DAT1 23BUF_MMC1_DAT2 23BUF_MMC1_DAT3 23
BUF_MMC1_CMD 23BUF_MMC1_CLK 23
R714 0E_1%DNI
RA15 0EDNI
1234 5
678
R713 0E_1%DNI
SOC_MMC1_DAT4SOC_MMC1_DAT5
SOC_MMC1_DAT0_R
SOC_MMC1_DAT7
SOC_MMC1_DAT3_R
SOC_MMC1_DAT1_R
SOC_MMC1_DAT6
SOC_MMC1_DAT2_R
SOC_MMC1_SDWP
SOC_MMC1_CLKSOC_MMC1_CMD
SOC_MMC1_DAT3
SOC_MMC1_DAT1SOC_MMC1_DAT2
SOC_MMC1_DAT0
SOC_MMC1_CLK_RSOC_MMC1_CMD_R
TRANS_EMMC_RSTn17R3471K
TP124SMD
TP125SMD
R281
10K
_1%
RA6 0E
1234 5
678 R
286
10K
_1%
R304
10K
_1%
MM
C1
U1-16
66AK2G02
MMC1CLK /GPIO0_67J4
MMC1DAT0/GPIO0_66H3
MMC1DAT1/GPIO0_65F5
MMC1DAT2/GPIO0_64J5
MMC1DAT3/GPIO0_63H4
MMC1DAT5/GPIO0_61G4
MMC1DAT6F4
MMC1DAT7/GPIO0_59G5
MMC1SDCD/GPIO0_69J3
MMC1SDWP/GPIO0_70K3
MMC1POWK2
MMC1DAT4E3
MMC1CMDJ2
R267
R3880E_1%
R676 0E_1%DNI
R3870E_1%
R292
10K
_1%
R299
10K
_1%
R269
10K
_1%
R271
10K
_1%
SOC_MCASP2AXR0
SOC_MCASP2AXR2SOC_MCASP2AXR1
SOC_McASP2ACLKX
SOC_McASP2AHCLKR
SOC_McASP2AHCLKX
SOC_McASP2FSX
SOC_MCASP2AMUTE
SOC_MCASP2AXR3
SOC_McASP2ACLKRSOC_McASP2FSR
SOC_MCASP2AXR4SOC_MCASP2AXR5
SOC_MCASP2AXR0_RSOC_MCASP2AXR0SOC_MCASP2AMUTE SOC_MCASP2AMUTE_R
SOC_MCASP2AXR3 23
SOC_MCASP2AXR4 23
SOC_MCASP2AXR1 23
SOC_MCASP2AXR2 23
SOC_McASP2ACLKX 23SOC_McASP2FSX 23
SOC_McASP2AHCLKR 36
WLAN_TRANS_EN 23,29
SoC_LED0 34
R415 0E_1%
R393 0E_1%DNI
R396 0E_1%
R413 0E_1%
R420 0E_1%
R409 0E_1%
R407 0E_1%
McASP2
U1-8
66AK2G02
GPIO0_109/MCASP2AXR1A2
GPIO0_110/MCASP2AXR2E4
GPIO0_114/MCASP2ACLKRB2
GPIO0_112/MCASP2AXR4A3
GPIO0_113/MCASP2AXR5E5
GPIO0_120/MCASP2ACLKXB3
GPIO0_116/MCASP2AHCLKRE6
GPIO0_119/MCASP2AHCLKXD5
GPIO0_108/MCASP2AXR0D3
XREFCLK/GPIO0_117/MCASP2AMUTEC2
GPIO0_115/MCASP2FSRD4
GPIO0_118/MCASP2FSXC3
GPIO0_111/MCASP2AXR3B1
R822 0E_1%DNI
R411 0E_1%
R428 0E_1%
R401 0E_1%
R417 0E_1%
R423 0E_1%
R821 0E_1%DNI
R433 0E_1%
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 18. eMMC and COM8 Resistor Multiplexing
Table 6. eMMC and COM8 Resistor Multiplexing
DNI Mount DescriptionRA6, R387, R388, and R822 RA15, R713, R714, and R393 Connect MMC1 to COM8RA15, R713, R714, and R393 RA6, R387, R388, and R822 Connect MMC1 to eMMC (default)
Gigabit Ethernet PHYKSZ9031RNX
K2G SoC
RJ45Connector with
MagneticsLPJG16314A4NL
RGMII_TXCLK
RGMII_TXCTL
RGMII_TXD [0-3]
RGMII_RXCLK
RGMII_RXCTL
RGMII_RXD [0-3]
MDIO_CLK
MDIO_DATA
TXC
TX_CTL
TD [0-3]
RXC
MDIO
RX_CTL/PHYAD2
RD [0-3] / MODE [0:3]
MDC
TXRXPA
TXRXMA
TXRXPB
TXRXMB
TXRXPC
TXRXMC
TXRXPD
TXRXMD
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K2G General Purpose Evaluation Module (EVMK2G)
2.12 Gigabit EthernetThe Gigabit Ethernet PHY (KSZ9031RNX) from MICREL is interfaced to the RGMII port of the processoras shown in Figure 19.
The RJ45 connector with magnetics is interfaced to the MDI (media dependent interface) port of PHY. ThePHY address, PHYAD [2:0], is sampled and latched at power-up/reset and is configurable to any valuefrom 0 to 7. Each PHY address bit is configured as:• Pull-up = 1• Pull-down = 0
The MODE [3:0] pins are sampled and latched at power-up/reset. Each Mode bit is configured as:• Pull-up = 1• Pull-down = 0
The MODE pins are set for RGMII mode (10/100/1000 speed half/full-duplex).
Reference clock for PHY is provided by the 25-MHz crystal, Y9. (See Section 2.4)
Figure 19. Gigabit Ethernet Interface Block Diagram
CDCM6208
K2G SoC
100MHz(CML)
TXN0TXP0
RXN0RXN0
PCIE_CLK_P/N
x1 Edge Card Connector
TXP0
RXN0RXP0
TXN0
100MHz (HCSL)
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K2G General Purpose Evaluation Module (EVMK2G)
2.13 PCIeThe PCIe RX and TX pairs are connected to x1 PCIe edge card connector as shown in Figure 20. Clockgenerator (CDCM6208) provides the 100-MHz reference clocks for the PCIe port of the processor and tothe daughter card that connects to the edge card connector.
Figure 20. PCIe Interface Block Diagram
2.14 Display InterfaceThe Display interface (DSS) is muxed between the LCD and the HDMI transmitter SiI9022A as shown inFigure 21. The DSS is muxed using two 32-bit buffers to connect to the LCD or the HDMI transmitter.Either the LCD or the HDMI transmitter is enabled by switches SW13 and SW14:• for HDMI: SW13 and SW14 = ON• for LCD: SW13 and SW14 = OFF
2.14.1 LCDThe TFT LCD module (NHD-4.3-480272EF-ATXL-CTP) from Newhaven display can be plugged into the40-pin FPC connector on the EVMK2G. The LCD backlight is driven by DC-DC boost-converterTPS61081DRCT.
The LCD is not part of the EVMK2G kit, it should be purchased separately. More details of LCDinstallation procedure is provided in Section 3.
2.14.2 HDMI TransmitterThe EVMK2G supports HDMI interface with the HDMI transmitter SiI9022A. The HDMI signals areterminated to a connector by way of an ESD protection device TPD12S016PWR. The HDMI interface iscontrolled by I2C1 of the SoC. The HDMI signals consist of three differential pairs of data lines and onedifferential pair of clock line.
The McASP2 is interfaced to the HDMI transmitter to support audio over HDMI and I2C1 for control.McASP2TX is shared between the HDMI transmitter and the Audio Codec. The Audio MCLK for the HDMItransmitter is derived from a 12.288-MHz Oscillator, U75, that is shared between the Audio Codec and theHDMI transmitter (See Section 2.4).
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SW14
OE# 3.3 V 1.2 V
EVMK2G SOC
DSS_DE
DSS_PCLK
DSS_DATA [0:23]
32 bit Buffer
S74LVC32244ZKER
DSS_HSYNC LCD Conn40 pin FPC Connector
DSS_VSYNC
32 bit Buffer
S74LVC32244ZKER
SW13 K2G SoC
OE#
ESDTPD12S016
I2C1_SDA
I2C1_SCL
HDMIAudio
Selection
HDMI TransmitterSiI9022A
12.288MHz OSC
HDMI Connector
Std Type A
HD
MI_C
E
HD
MI_H
P
HD
MI_ I2C
TM
DS
_CL
TM
DS
_TX
HD
MI_C
E
HD
MI_H
PLG
HD
MI_I2C
TM
DS
_CL
TM
DS
_TX
MCASP2_ACLKX
MCASP2_AFSX
MCASP2_AXR
MCASP0_ACLKX
MCASP0_AFSX
MCASP0_AXR
LCD_AC_BIAS_EN
LCD_PCLK
LCDDATA [0:23]
LCD_HSYNC
LCD_VSYNC
HDMI_AC_BIAS_EN
HDMI DATA
HDMI HSYNC
HDMI_VSYNC
HDMI_PCLK
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 21. Display Interface Block Diagram
Table 7. DSS Lines Between LCD and HDMI Multiplexing
SW13 and SW14 Position Signal ResultON SEL_HDMIn signal is low HDMI is enabledOFF SEL_LCDn signal becomes low LCD is enabled
K2G SoC
Buffer
SW15 OE#
MCASP2_AXR [2:3]
MCASP2_AFSX
MCASP2_ACLKXHPROUT
HPLOUT
LINE1R
LINE1L
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AUDIO
CODEC
TLV320AIC
K2G SoC
TOUCH Connector
I2C1_SDA
I2C1_SCL
TOUCH_INTR
RST
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K2G General Purpose Evaluation Module (EVMK2G)
Table 8. HDMI Audio Line Selection Between McASP0 and McASP2
Signal Logic Result
DC_BRD_DETLow McASP2 is connected to HDMI Transmitter SiI9022A.High McASP0 is connected to HDMI Transmitter SiI9022A.
2.15 Touch Connector
NOTE: The EVMK2G does not come with an LCD Touchscreen display, it should be purchasedseparately.
The Touch Connector interface is shown in Figure 22.
Figure 22. Touch Interface Block Diagram
2.16 Audio CodecThe Audio Codec TLV320AIC3106IRGZT is interfaced to the McASP2 port of the processor as shown inFigure 23. The ACLKX and FSX lines of McASP2 are shared between the Audio Codec, COM8, and theHDMI transmitter. Hence, a buffer with OE# is connected as shown in Figure 23 for muxing. Switch SW15is turned ON for connecting the McASP2 to the Audio Codec. Audio Line In and Line Out are providedthrough 3.5mm audio jacks (J32 and J33).
Figure 23. Audio Codec Interface Block Diagram
Table 9. Audio Codec Multiplexing
Signal Switch OutputAUD_BUFF_EN SW15 is ON SOC_McASP2 signals are going to Audio Codec and HDMI transmitter.
COM8_BUFF_EN SW11 is ON COM8 signals are connected to SOC_McASP2.
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K2G SoC
CANTransceiver
ISO1050DUB
DB9
Connector
DCAN_TX
DCAN_RX
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K2G SoC
COM8
Connector
OE#
Level
Translator
SN74AVC4T245PW
SDIO Buffer
TXB0108PWR
MMC1_D [0-3]
MMC1_CMD
WLAN_EN
UART1_TX
UART1_RX
UART1_CTS
MMC1_CLK
UART1_RTS
MCASP2_AXR [0:1]
MCASP2_ACLKR
MCASP2_AFSR
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K2G General Purpose Evaluation Module (EVMK2G)
2.17 COM8 ConnectorThe COM8 connector interface is generally used to communicate with wireless modules. It can beconnected to a WiLink™ 8 module. A Level Translator SN74AVC4T245PW is used to convert the signalsUART and McASP from 3.3V to 1.8V as shown in Figure 24.
Figure 24. COM8 Connector Interface Block Diagram
2.18 DCANThe CAN transceiver ISO1050DUB is connected to DCAN0 and DCAN1 interface of the processor asshown in Figure 25.
Figure 25. DCAN Interface Block Diagram
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MLBK2G SoC
MLB_PCLKN
MLB_PSIGP
MLB_PSIGN
MLB_PDATP
MLB_PDATN
MLB_PCLKP
MLB_CLK
MLB_DAT
MLB_SIG
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K2G General Purpose Evaluation Module (EVMK2G)
2.19 MLBThe Media Local Bus (MLB) interface signals are terminated in Samtec’s QSH-020-01-L-D-DP-Aconnector as shown in Figure 26.
Figure 26. MLB Interface Block Diagram
5V USB1_VBUS
USB1_VBUS
USB-OTGMicro-AB Connector
K2G SoC
Common ModeChoke
ESD Diodes(TPD2EUSB30DRTR)
POWER
SWITCH
EN
USB1_DP
USB1_DRVVBUS
USB1_DM
USB1_ID
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USB0_VBUS
POWERSWITCH
EN
ESD Diodes(TPD2EUSB30DRTR)
CommonModeChoke
K2G SoC
USB Type A
USB0_DRVVBUS
USB0_ID
USB0_VBUS
USB0_DMUSB0_DP
5V
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K2G General Purpose Evaluation Module (EVMK2G)
2.20 USB HostUSB0 shall be used for the USB Host interface in the EVMK2G. The USB0ID pin is grounded through a 0-ohm resistor in order to configure it as USB Host as shown in Figure 26. Common mode choke coil andESD diodes (TPD2EUSB30DRTR) are used on USB data signals. A power distribution switch(TPS2051BD) is used to deliver USB power to the devices.
Figure 27. USB Host Interface Block Diagram
2.21 USB Dual RoleUSB1 shall be configured as the USB Dual Role in the EVMK2G. The USB Dual Role interface is shownin Figure 28. Common mode choke coil and ESD diodes are used on USB data signals. A powerdistribution switch (TPS2051BD) is used to deliver USB power when it acts as a host.
Figure 28. USB Dual Role Interface Block Diagram
Serial ExpansionConnector
DB9Connector
UART Transceiver
Buffer
K2G SoC
USBMini-B
Connector
USB to UARTCP2105
Buffer
UART0_RX
CP2105_DP
CP2105_DM
SOC_UART0_CP2105_EN
OE#
OE#
UART0_RTS
UART0_CTS
UART0_TX
UART0_TXVR_EN
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K2G General Purpose Evaluation Module (EVMK2G)
2.22 UARTThere are three UART ports available in the EVMK2G.
UART0 debug port is multiplexed between the DB9 port, USB-to-UART converter (CP2105), and theSerial Expansion header as shown in Figure 29.
Table 10. UART0 Multiplexing
Signal SW12 Logic SoC UART0 Pins Connected To
UART0_TXVR_ENON Low DB9 connector via RS-232 chip.OFF High USB-to-UART converter CP2105.
UART1 is connected to the COM8 connector as shown in Figure 30. Connection to COM8 and eMMC ismuxed and is explained in Section 2.11.
Table 11. UART1 Multiplexing
Signal Logic Output
WLAN_TRANS_ENLow SoC UART1 pins are connected to COM8High MMC1 connected
UART2 is muxed between the BMC UART1 and the 6-pin header, as shown in Figure 31 and explained inSection 2.3.
Figure 29. UART0 Interface Block Diagram
K2G SoC
BMCUART1
UART2_TX
UART2_RX
Buffer
TX
RX 6 Pin
Header Buffer
TX
RX
OE#
OE#
BMC_UART_SEL
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K2G SoC
LevelTranslator
COM8 Connector
OE#
COM_BTUARTTX
COM_BTUARTRX
COM_BTUARTRTS
COM_BTUARTCTS
UART1_TX
UART1_RX
UART1_CTSn
UART1_RTSn
WLAN_TRANS_EN
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 30. UART1 Interface Block Diagram
Figure 31. UART2 Interface Block Diagram
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K2G SoC
AUDIO ExpansionConnector
McASP0_AXR [0:7], [12-15]
MCASP0_AFSX
MCASP1_AFSX
SPI2_SCS0/SPI2_SCS1
SPI2_CLK SPI2_SIMO
SCL1
SDA1
MCASP1_AHCLKX
MCASP0_AHCLKX
MCASP0_AMUTE
GPIO
MCASP1_AXR [0:9]
MCASP2_AXR 5
MCASP0_AFSR
MCASP0_AHCLKR
MCASP1_AFSR
MCASP1_ACLKR
MCASP1_AHCLKR
MCASP2_AFSR
MCASP2_ACLKR
MCASP2_AHCLKR
SPI2_SOMI
MCASP1_ACLKX
MCASP0_ACLKX
MCASP0_ACLKR
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K2G General Purpose Evaluation Module (EVMK2G)
2.23 Audio Expansion ConnectorThe EVMK2G consists of an audio expansion connector for an audio daughter card. Audio expansionconnector contains McASP0, McASP1, and McASP2 signals along with the I2C1, SPI2, and GPIO signalsas shown in Figure 32.
Figure 32. Audio Expansion Connector Interface Block Diagram
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K2G SoC
SerialExpansionConnector
I2C2_SCL
I2C2_SDA
TIMO0
eHRPWM5_B
eHRPWM_TZn3
eHRPWM_TZn4
I2C0_SCL
I2C0_SDA
TIMO1
SPI0_CLK
SPI0_SIMO
ECAP1_IN_PWM1_OUT
TIMI0
eHRPWM3_SYNCO
SPI0_SOMI
UART0
eHRPWM3_A
eHRPWM3_B
eHRPWM3_SYNCI
eHRPWM4_A
eHRPWM5_A
eHRPWM4_B
eHRPWM_TZn5
TIMI1
SPI0_SCS0
UART0
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K2G General Purpose Evaluation Module (EVMK2G)
2.24 Serial Expansion ConnectorThe EVMK2G consists of a Serial Expansion connector that contains I2C0, SPI0, UART0, Timer 0,Timer1, eHRPWM3, eHRPWM4, eHRPWM5, and eCAP signals as shown in Figure 33.
Figure 33. Serial Expansion Connector Interface Block Diagram
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K2G General Purpose Evaluation Module (EVMK2G)
2.25 I2C Address MappingThe address mapping for the I2C interface on the EVMK2G is shown in Table 12 and Table 13.
Table 12. SoC Address Table
I2C Used Device Address
I2C0
EEPROM 0x50, 0x51BMC 0x0 (Programmable)
Serial Expansion Connector TBDPCIe Connector TBD
I2C1
HDMI Transmitter 0x3B, 0x3F, 0x62Audio Codec 0x1BTouch Screen 0x70, 0x71I/O Expander 0x20
Temperature Sensor 0x48MLB Connector TBD
Audio Expansion Connector 0x4A, 0x4B, 0x4C, 0x4DClock Generator 0x4F
I2C2 PMIC0x2D (General Purpose)0x12 (Voltage Scaling)
Table 13. BMC I2C Address Table
BMC I2C Used Device 7-Bit Address
I2C0 PMBUS
0x40 : 3.3V0x41 : CVDD0x42 : CVDD1
0x43 : 1.8V0x44 : DVDD_DDR
I2C1 Processor Always Master
BCKO
LRCKO
DOUTSCKO
DOUT1
DOUT2
DOUT1DOUT2
SCKI
SCKI
BCK
BCK
LRCK
LRCK
DIN[1:4]
DIN[1:4]
SCKI
BCK
BCKSCKI
LRCK
LRCK
MUTE
MUTE
MCLKOUTBCLKOUTLRCKOUTDOUT[0:3]
DIN[0:7]
MCLKINBCLKINLRCKIN
HD
MT
XR
AUDIO CODEC
CO
M8
AU
DIO
EX
PA
NS
ION
CO
NN
EC
TO
R
AD
C0
DIR
90
01
AD
C1
DA
C0
I2S
HE
AD
ER
DA
C1
MCASP2_ACLKX
MCASP2_AFSX
MCASP2_AXR2
MCASP2_AXR3
MCASP2_ACLKR
MCASP2_AFSR
MCASP2_AXR5
MCASP1_AXR0
MCASP1_AXR1
MCASP1_AHCLKR
MCASP1_AFSR
MCASP1_ACLKR
MCASP1_AXR2
MCASP1_AXR3
MCASP0_AXR[0:3]
MCASP0_ACLKX
MCASP0_AFSX
MCASP0_AHCLKX
MCASP0_AXR[4:7]
MCASP0_AXR[12:15]
MCASP0_AHCLKR
MCASP0_AFSRMCASP0_ACLKR
MCASP1_AHCLKX
MCASP2_AHCLKR CS2000
BU
FF
ER
M
c
A
S
P
2
M
c
A
S
P
1
M
c
A
S
P
0
A
U
D
I
O
D
A
U
G
H
T
E
R
C
A
R
D
BUFFER
MCASP2_AXR4BUFFER
MUX 2
4
4
44
4
4
12.288MHzOSC
BUFFER
MCASP2_AXR1
4
BU
FF
ER
JUMPER
4
BU
FF
ER
BUFFER
BU
FF
ER
4
OE#
BUFFER
JUMPER
4
Digital Audio OUTCoaxial RCA Conn
MCASP1_AXR9
MCASP0_AMUTEMUX
DNI
OE#
DIN
DOUT
WCLK
BCLK
AUD_CLK
AUD_DOUT
AUD_DIN
AUD_FSYNC
MCLK
SD[0:3]
MCLK
WS
SCK
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K2G General Purpose Evaluation Module (EVMK2G)
2.26 McASP Configuration
Table 14. McASP Configuration
McASP Port Device Clock MasterMcASP0 RX I2S Header I2S HeaderMcASP0 TX DAC McASP0 TXMcASP1 RX ADC- PCM1865 x2 McASP1 RX
McASP2 TXHDMI Transmitter McASP2 TX
Audio Codec AIC3106 McASP2 TX
McASP2 RXDIR9001 DIR9001
Audio Codec AIC3106 McASP2 Rx (SYNC mode)COM8 COM8
Figure 34. McASP Interface Block Diagram
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K2G General Purpose Evaluation Module (EVMK2G)
3 EVM Board Physical SpecificationsThis section describes the physical layout of the EVMK2G board and its connectors, switches, and testpoints.
NOTE: The EVMK2G does not come with an LCD Touchscreen display, it should be purchasedseparately.
3.1 Mounting of LCD and Spacers
CAUTIONMount the spacers and screws while unpacking the EVM from the package box.Without the spacers, damage may occur to the board or bottom assembledcomponents.
Figure 35 shows the mechanical diagram to mount the LCD and the spacers. The EVMK2G Kit containsthe following parts for assembling the LCD and the spacers:• Spacers• Screws• Rubber feet• Brackets for 4.3’’ LCD
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 35. EVMK2G Mechanical Drawing
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K2G General Purpose Evaluation Module (EVMK2G)
3.2 Board LayoutThe EVMK2G board dimension is 12’ × 9.60’’ (305mm × 244mm). It is a 10-layer board and poweredthrough connector J3. The top and the bottom layout views of the EVMK2G are provided in Figure 36 andFigure 37, respectively.
Figure 36. EVMK2G Board Assembly Layout - Top View
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K2G General Purpose Evaluation Module (EVMK2G)
Figure 37. EVMK2G Board Assembly Layout - Bottom View
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K2G General Purpose Evaluation Module (EVMK2G)
3.3 Connector IndexThe EVMK2G board has several connectors that provide access to various interfaces on the board, aslisted in Table 15 and shown in Figure 38.
Table 15. EVMK2G Board Connectors
Connector Part Number Pins FunctionJ1 548190519 7 Mini USB B-Type for XDS200J2 MEC6-150-02-S-D-RA1-TR 100 COM8 connectorJ3 RAPC722X 3 DC Power input jack connectorJ5 10061913-100CLF 38 PCI Express connectorJ19 QSH-030-01-L-D-A 60 MIPI 60 -pin SoC JTAG connectorJ21 68610614122A 8 Touch Screen connectorJ22 62684-401100ALF 40 LCD connectorJ23 54819-0572 9 Mini USB B-Type for CP2105J31 LPJG16314A4NL 16 RJ45 Ethernet connector
J32, J33 SJ-3524-SMT-1 4 Audio Line In and Line Out connectorsJ34 QSH-020-01-L-D-DP-A 44 MLB connectorJ35 87583-2010BLF 6 USB Type A - HostJ36 10029449-001RLF 23 HDMI connectorJ37 DM3AT-SF-PEJM5 14 SD/MMCJ38 ZX62-AB-5PA(11) 8 USB Micro for Dual RoleP1 182-009-113R531 11 UART0 Over DB9
P2, P3 182-009-113R531 11 DB9 connectors for DCAN0 and DCAN1
3.3.1 DC Jack (J3)The EVMK2G is powered by inserting the 12V-DC adapter into this power jack.
3.3.2 Mini USB for On-board XDS (J1) and CP2105 (J23)The EVMK2G has 2 mini USB connectors. J1 is for on-board XDS200 circuit. J23 is for SoC UART0 andBMC console over USB.
J2
P2
J21
J19
J5 J3
P3
P1
J23
J22 J36 J34 J31 J38 J35 J37 J1 J32 J33
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Figure 38. EVMK2G Board Connectors
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K2G General Purpose Evaluation Module (EVMK2G)
3.3.3 COM8 (J2)The EVMK2G has a COM8 connector for interfacing to TI WiLink 8 modules. The pin out is given inTable 16.
Table 16. COM8 (J2) Pin List
Pin Description Pin Description Pin Description Pin Description1 COM_SLOW_CLK 26 COM_SDIO_D0 51 NC 76 COM_BTUARTDEBUG2 DGND 27 NC 52 COM_AUD_CLK 77 DGND3 DGND 28 COM_SDIO_D1 53 NC 78 COM_GPIO94 COM_WL_RST 29 NC 54 COM_AUD_FSYNC 79 NC5 VCOM_BAT 30 COM_SDIO_D2 55 NC 80 NC6 DGND 31 NC 56 COM_AUD_IN 81 NC7 VCOM_BAT 32 COM_SDIO_D3 57 NC 82 NC8 V1_8D 33 NC 58 COM_AUD_OUT 83 DGND9 DGND 34 COM_WL_IRQ 59 NC 84 NC10 NC 35 TP17 60 DGND 85 NC11 COM_WL_RS232_TX 36 NC 61 NC 86 NC12 NC 37 DGND 62 TP14 87 DGND13 COM_WL_RS232_RX 38 NC 63 NC 88 NC14 NC 39 TP18 64 DGND 89 COM_BTRST15 COM_WL_UART_DBG 40 NC 65 NC 90 NC16 NC 41 NC 66 COM_BTUARTTX 91 NC17 NC 42 DGND 67 NC 92 DGND18 DGND 43 NC 68 COM_BTUARTRX 93 NC19 DGND 44 NC 69 NC 94 NC20 COM_SDIO_CLK 45 NC 70 COM_BTUARTCTS 95 DGND21 NC 46 NC 71 NC 96 COM_GPIO1122 DGND 47 DGND 72 COM_BTUARTRTS 97 DGND23 NC 48 TP15 73 NC 98 COM_GPIO1224 COM_SDIO_CMD 49 NC 74 NC 99 NC25 NC 50 TP16 75 NC 100 COM_GPIO10
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K2G General Purpose Evaluation Module (EVMK2G)
3.3.4 PCI Express (J5)The EVMK2G has x1 PCI express interface to connect PCIe add-on cards. The pin out is given inTable 17.
Table 17. PCI Express (J5) Pin List
Pin Description Pin DescriptionA1 PRSNT# B1 VCC12V0A2 VCC12V0 B2 VCC12V0A3 VCC12V0 B3 VCC12V0A4 GND B4 GNDA5 GND B5 SCLA6 TDI B6 SDAA7 NC B7 GNDA8 TMS B8 VCC3V3A9 VCC3V3 B9 GNDA10 VCC3V3 B10 VCC3V3A11 CON_PORz B11 WAKEnA12 GND B12 NCA13 CLKP_HCSL_100MHz B13 GNDA14 CLKN_HCSL_100MHz B14 PCIe_TXN0A15 GND B15 PCIe_TXP0A16 RXN0 B16 GNDA17 RXP0 B17 PRSNT1#A18 GND B18 GNDSH1 PCIe_GND SH2 PCIe_GND
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3.3.5 JTAG MIPI-60 (J19)The EVMK2G has an MIPI connector for JTAG communication to the SoC through an external emulator.The pin out is given in Table 18.
Table 18. JTAG MIPI-60 (J19) Pin List
Pin Description Pin Description Pin Description1 VCC 21 EMU01 41 EMU132 TMS 22 NC 42 NC3 TCK 23 EMU04 43 EMU144 TDO 24 NC 44 NC5 TDI 25 EMU05 45 EMU156 MIPI_JTAG_RESET 26 NC 46 NC7 RTCK 27 EMU06 47 EMU168 TRST 28 NC 48 NC9 NC 29 EMU07 49 EMU1710 NC 30 NC 50 NC11 NC 31 EMU08 51 EMU1812 VCC 32 NC 52 NC13 EMU02 33 EMU09 53 EMU1914 NC 34 NC 54 NC15 GND 35 EMU10 55 NC16 GND 36 NC 56 NC17 EMU03 37 EMU11 57 GND18 NC 38 NC 58 VCC19 EMU00 39 EMU12 59 NC20 NC 40 NC 60 NC
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K2G General Purpose Evaluation Module (EVMK2G)
3.3.6 LCD (J22) and Touch Screen (J21)The EVMK2G has a 40-pin FPC LCD and a 6-pin touch screen connector. A 4.3-inch LCD can beconnected to the EVM through the connectors shown in Figure 39. The pin out is given in Table 19.
Figure 39. LCD (J22) and Touch Screen (J21) Connectors
Table 19. LCD (J22) and Touch Screen (J21) Pin List
LCD Connector (J22) Touch Screen Connector (J21)Pin Description Pin Description1 LED- 1 VDD2 LED+ 2 GND3 GND 3 CLK4 VDD 4 DATA
5-12 R0-R7 5 TOUCH INTERRUPT13-20 G0-G7 6 RESET21-28 B0-B7
29 GND30 CLK31 DISP32 HSYNC33 VSYNC34 DE35 NC36 GND37 NC38 NC39 NC40 NC
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K2G General Purpose Evaluation Module (EVMK2G)
The LCD connection procedure is:1. Lift the tab of the connectors J22 and J21.2. Safely insert the LCD and Touch Flex cables. Make sure the cables are correctly fitting in the
connector.3. Close the tab.4. Install the brackets.
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K2G General Purpose Evaluation Module (EVMK2G)
3.3.7 RJ45 Ethernet (J31)The EVMK2G has one RJ45 connector with magnetics for Ethernet interface. It is connected to theEthernet PHY Transceiver through parallel termination. The pin out is given in Table 20.
Table 20. RJ45 Ethernet (J31) Pin List
Pin Description1 GND2 NC3 Data3_P4 Data3_N5 Data2_P6 Data2_N7 Data1_P8 Data1_N9 Data0_P10 Data0_N11 VDD12 LED_ACTn13 LED_Linkn14 VDD15 GND16 GND
3.3.8 Stereo Analog Audio Input (J32) and Output (J33)The EVMK2G has two 3.5-mm female stereo jacks that are connected to the AIC3106 Audio Codec:• Line In: For connecting to the output of an mp3 player• Line Out: For connecting to headphones or speakers
Pin out details of Audio connector is given in Table 21.
Table 21. Stereo Analog Audio Input (J32) and Output (J33) Pin List
Line In Connector (J32) Line Out Connector (J33)Pin Description Pin Description1 GND 1 GND2 LEFT_IN 2 LEFT_OUT3 RIGHT_IN 3 RIGHT_OUT4 NC 4 NC
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3.3.9 MLB (J34)The EVMK2G has a single media local bus connector (QSH-020-01-L-D-DP-A) that is used for connectingthe MLB daughter card (Microchip’s OS81110). The pin out is given in Table 22.
Table 22. MLB (J34) Pin List
Pin Description Pin Description1 SIGN 21 NC2 MLBCLK 22 NC3 SIGP 23 NC4 NC 24 GPIO25 NC 25 Reset6 MLBSIG 26 NC7 NC 27 NC8 NC 28 NC9 DATDN 29 NC10 MLBDAT 30 NC11 DATDP 31 NC12 NC 32 NC13 NC 33 SCL14 NC 34 TP17915 NC 35 SDA16 TP174 36 NC17 PCLKN 37 VCC3V318 NC 38 VCC3V319 PCLKP 39 VCC3V320 NC 40 VCC12V0
3.3.10 USB0 Host Type A (J35)The EVMK2G has a USB Type A connector as host. The pin out is given in Table 23 .
Table 23. USB0 Host Type A (J35) Pin List
Pin Description1 VDD2 D-3 D+4 ID Pin to GND5 USB0_GND6 USB0_GND
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3.3.11 HDMI (J36)The EVMK2G has an HDMI out where it can be used to connect to the HDMI monitor via cable. It is a 23-pin Type A Receptacle connector. The pin out is given in Table 24.
Table 24. HDMI (J36) Pin List
Pin Description1 HDMI_TX2+2 GND3 HDMI_TX2-4 HDMI_TX1+5 GND6 HDMI_TX1-7 HDMI_TX0+8 GND9 HDMI_TX0-10 HDMI_CLK+11 GND12 HDMI_CLK-13 HDMICONN_CEC14 NC15 HDMICONN_I2CSCL16 HDMICONN_I2CSDA17 GND18 5V_OUT_HDMI19 HDMI_HP_OUT20 GND21 GND22 GND23 GND
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3.3.12 MMC/SD (J37)The MMC/SD card holder is located on the top side of the board and is used to provide an interface to aMMC/SD card. It is a 14-pin MMC/SD card holder. The pin out is given in Table 25.
Table 25. MMC/SD (J37) Pin List
Pin Description1 DAT22 CD/DAT33 CMD4 VDD5 CLOCK6 VSS7 DAT08 DAT19 CD110 SDCD_GND11 SDCD_GND12 CD213 SDCD_GND14 SDCD_GND
3.3.13 USB1-Micro (J38)The EVMK2G has a micro-USB connector as USB1 dual role. The pin out is given in Table 26.
Table 26. USB1-Micro (J38) Pin List
Pin Description1 VDD2 D-3 D+4 ID5 GND6 USB0_GND7 USB0_GND8 USB0_GND9 USB0_GND
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3.3.14 DB9 Connector (P1, P2, and P3)The EVMK2G has three DB-9 connectors. DB9 connector (P1) is connected to the SoC UART0 throughthe RS-232 Transceiver. Two DB9 connectors (P2 and P3) are used for DCAN0 and DCAN1, respectively,connected to the SoC through the CAN transceiver. The pin out is given in Table 27.
Table 27. DB9 Connector (P1, P2, and P3) Pin List
P1 Connector P2 and P3 ConnectorsPin Description Pin Description1 NC 1 NC2 RXD 2 CANL3 TXD 3 CAN_GND4 NC 4 NC5 GND 5 CAN_GND6 NC 6 CAN_GND7 NC 7 CANH8 NC 8 NC9 NC 9 VCAN10 Shield_GND 10 Shield_GND11 Shield_GND 11 Shield_GND
SW12
SW15
SW14 & SW13
Tactile Switches
SW3 SW11
SW1
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3.4 SwitchesThe EVMK2G has a total of 15 switches (Figure 40):• 1 Sliding switch for Powering on the board• 8 Tactile switches for various Reset, PMIC Power on, VOL+, VOL-• 1 DIP slide switch for boot mode configuration• 5 DIP SPST switches for enabling various interfaces
Figure 40. EVMK2G Switches
3.4.1 Slide SwitchThe EVMK2G has one sliding switch/Power switch (SW1) for powering ON/OFF the board.
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3.4.2 Tactile SwitchThe EVMK2G has 8 tactile switches. Pressing each performs different functions. Switches and theircorresponding functions are listed in Table 28.
Table 28. EVMK2G Tactile Switches
Switch Function DescriptionSW2 VOL+ Currently not implementedSW4 VOL- Currently not implementedSW5 PWRON_RSTz Power-on ResetSW6 BMC_RESETz Pressing this switch resets the BMCSW7 ATTENTIONz Currently not implementedSW8 PMIC_HDRST PMIC Hard ResetSW9 PMIC PWRON PMIC Power onSW10 WARMRSTz Warm Reset
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3.4.3 DIP SwitchThe DIP Switch/Boot mode switch (SW3), shown in Figure 41, is used for selecting the boot mode. TheBoot mode configurations are given in Table 29.
Figure 41. DIP (SW3) Switch
Table 29. Boot Mode Configurations for SW3
SW3 Setting (MSB first) Boot Mode0000 Sleep/No Boot0001 PCIe Boot0010 Ethernet Boot0011 I2C PLL Boot0100 SPI No PLL Boot0101 SPI PLL-1 Boot0110 USB Boot0111 MMC/SD Boot1000 UART Boot1001 QSPI 96 Boot1010 eMMC Boot1011 NAND Boot1100 I2C No PLL Boot1101 SPI PLL-2 Boot1110 SPI PLL-3 Boot1111 QSPI 48 Boot
3.4.4 DIP SPST SwitchThe DIP SPST switches on the board are used for enabling and disabling various interfaces. Switch andtheir functions are:• Audio Switch: Audio switch (SW15) is to enable the Audio buffer.• COM8 Switch: The COM8 switch (SW11) is to Enable/Disable COM8 Buffer.• LCD/HDMI Selection Switches: The LCD and HDMI selection switches (SW14 and SW13) is to select
between the LCD or the HDMI. In both OFF condition, the LCD will be functioning. In the ON condition,the HDMI will be functioning.
• UART0 over USB/DB9 Switch: This switch (SW12) is used to enable UART0 over USB. In the ONcondition, UART0 is over DB9 connector. In the OFF condition, UART0 is over USB.
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3.5 Test PointsThe EVMK2G board has 187 test points. Each test point and its function is given in Table 30.
Table 30. EVMK2G Test Points
TestPoint Signal
TestPoint Signal
TestPoint Signal
TestPoint Signal
9 Reserved for U51 61 DGND 110 LDO5_3V3 160 Reserved for U62.4513 Reserved for U20B 62 DGND 111 U32-2.G6-GPIO5 161 Reserved for U62.4514 Reserved for J2 63 VCC12V0_DC_IN 112 NRESPWRON1 162 Reserved for U62.4515 Reserved for J2 64 VCC12V0_DC_IN 113 PMIC_VDD2 163 Reserved for U62.4516 Reserved for J2 65 Reserved for U17-4 114 U32-2.EN2 164 MFP217 Reserved for J2 66 Reserved for U20A 115 Reserved for U39.A7 165 MFP318 Reserved for J2 67 Reserved for U20A 116 U32-2.EN1 166 HDMI_CEC_D19 Reserved for U20B 68 Reserved for U20A 117 U32-2.GPIO8 167 U96-GPIO220 Reserved for U20G.V5 69 Reserved for U20A 118 LDO2_1V8 168 U96-GPIO121 Reserved for U20A 70 Reserved for U20A 119 LDO8_3V3 169 LINE2L+22 Reserved for U20A 71 Reserved for U20A 120 LDO6_3V3 170 LINE2L-23 Reserved for J2 72 Reserved for U20A 121 LDO7_3V3 171 LED_MODE25 Reserved for J2 74 Reserved for U20A 122 LDO1_1V8 172 HPLCOM26 Reserved for J2 75 Reserved for U20A 123 Reserved for U46.A7 173 HPRCOM29 TPS65000_PG# 76 Reserved for U20A 124 MMC1POW 174 Reserved for J3430 COM_GPIO9 77 Reserved for U20A 125 Reserved for U1-16.J3 175 U32-2 . GPIO031 COM_BTUARTDEBUG 78 Reserved for U20A 126 Reserved for U49.A7 176 BMC_JTAG_TRSTn33 COM_GPIO10 79 Reserved for U20A 127 SYSCLKOUT 177 Reserved for U17-634 COM_GPIO12 80 Reserved for U20A 128 Reserved for U52.A7 178 Reserved for U17-935 COM_GPIO11 81 Reserved for U20A 129 DGND 179 Reserved for J3436 T_TDIS 82 Reserved for U17-4 131 OBSCLK_N 180 Reserved for U20F37 SPARE0 84 VRTC 132 RMIIREFCLK/
PR0ECAP0ECAPSYNCOUT
181 Reserved for U20F
38 SPARE1 85 PMIC_PGOOD 133 SoC Reserved pin 182 Reserved for U20B39 uEXP3 86 Reserved for U20B 135 OBSCLK_P 184 Reserved for U5140 MEM_A12 88 U32-2 - GPIO3 136 SoC Reserved pin 185 Reserved for U5141 uEXP2 89 U32-2 - TEST 138 SoC Reserved pin 186 Reserved for U5142 VCC5V0_DCDC 90 DGND 139 SoC Reserved pin 187 Reserved for U5143 Reserved for U17-1 91 U32-2.C6-TRAN 140 SoC Reserved pin 189 Reserved for U5144 uEXP1 92 DGND 141 SoC Reserved pin 191 Reserved for U5145 Reserved for U17-1 93 Reserved for U20-L 142 SoC Reserved pin 192 Reserved for U5146 uEXP0 94 Reserved for U20-L 143 SoC Reserved pin 193 BUF_McASP2ACLKX47 Reserved for U17-1 95 Reserved for U20-L 144 SoC Reserved pin 194 VCC3V3_DC_CONN48 Reserved for U17-6 96 Reserved for U20-L 145 SoC Reserved pin 195 VCC3V349 Reserved for U17-1 97 XOSC1 146 SoC Reserved pin 196 VCC1V2_XDS50 Reserved for U17-6 98 BMC_HIBn 147 SoC Reserved pin 197 VCC1V8_XDS51 U18 SS/TR 100 LDO4_1V8 149 SoC Reserved pin 198 VCC3V3_XDS52 5V_PWRGD 101 CLK32KOUT 150 SoC Reserved pin 199 VCC3V3_DCIN53 U18.8-COMP 102 U32-2.D5-EN 151 SoC Reserved pin 200 3V3_DCIN_PG54 Reserved for U20B 103 LDO3_1V8 152 VLED+ 201 DGND55 3V3_CONN_PG 104 DGND 153 DDR_ODT1 202 DGND56 Reserved for U20J.A4 106 Reserved for U27.A7 154 DDR_CKE1 203 DGND57 Reserved for
U17-5.T19107 U32-2.F6-GPIO1 155 DDR_CE1Z 204 DGND
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Table 30. EVMK2G Test Points (continued)TestPoint Signal
TestPoint Signal
TestPoint Signal
TestPoint Signal
58 Reserved for U20A 108 U32-2.H7-GPIO4 157 SOC_DSS_FID 205 BUF_McASP2FSX59 Reserved for U20A 109 U32-2.G8-VREF 158 Reserved for U62.45 206 BUF_MCASP2AXR2
159 SOC_SPI3_MISO 207 BUF_MCASP2AXR3208 HDMI_AUDD0209 HDMI_AUDD1210 HDMI_AUDD2211 HDMI_AUDD3212 HDMI_AUDMCLK213 HDMI_AUDBCLK214 HDMI_AUDFSX
3.6 System LEDsThe EVMK2G has 13 LEDs. The description of each LED is given in Table 31 and shown in Figure 42.
Table 31. EVMK2G Board LEDs
LED Color DescriptionLD1 Yellow SoC_LED1LD2 Yellow SoC_LED3LD3 Yellow SoC_LED0LD4 Yellow SoC_LED2LD5 Yellow SoC_LED4LD6 Green XDS Power LEDLD7 Green EMULED1. Glows after XDS is flashedLD8 Green EMULED2. Glows when XDS connects with SoCLD9 Green Board Power (12V) ON Indication LEDLD10 Green SOC_PLL_LOCKLD11 Blue Glows after BMC is programmedLD12 Green BMC_GREEN_LEDLD13 Blue SOC_RESETSTATzLD14 Red Fault indicationLD15 Red Reverse Voltage detection
LD13
LD10
LD3
LD1
LD4
LD2
LD5
LD11
LD12
LD9
LD15
LD14
LD6
LD7
LD8
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Figure 42. EVMK2G Board LEDs
+3.3V2554mA
Level Translator x3
SN74AVC4T245PW
I2C EEPROM
AT24CM01
AUD EXP INA226 x5 TEMP SENSOR
TMP102AIDRLTTCA9517DGKR
VCC12V0_DC_IN+12V780mA
VCC12V0_DC_IN+12V1160mA
SOC GPIO
VCC12V0_MLB
+12V
EN AUDIO EXPANSION CONNECTOR
VCC12V0_AUD_EXP
+12V
750mA
VCC12V0_DC_IN+12V380mA
LP2996ASD#
VDDR_VTT+0.675V272mA
VCC_DDR_VREF+0.675V0.05mA
DDR_VREF+0.675V0.010mA
ETHERNET PHY
KSZ9031RNXCARJ45 LEDs x2
LEDs x7GPIO EXPANDER
TCA9555RTWR
EMMC16G-S100 UART TO USB
CP2105CS2000CP-CZZ
DAC 8550IBDGKT
MLB CONNECTOR370mA DCAN R1Z-3.305
x2400mA
CLOCK
CDCM6208V2RGZT
TPS54429
LDO3_1V8,+1.8V,90mA
12.288MHz
HDMI
SiI9022ACNU
CLOCK
CDCM6208V2RGZT
DSS BUFFER x2
MICRO SD CARD
TLV707085DQNT
LDO_PCIE/USB_CAP,+0.85V109mA
LED
LED
LED
LED x 3
TOUCH SCREEN & LCD
TPS54620RGY LM22675MR
LP3985IM5-3.0TPS79601DRBR
PMIC TPS659118
BMC DISPLAY
NHD-C12832A1Z-NSW-BBW-3V3
BOARD MANAGEMENT
CONTROLLER( BMC)
TM4C129XNCZADI3
VCC12V0_DC_IN
+12V
1679mA
VCC3V0_BMC_LCD
+3V
35mA
VCC5V0_DCDC
+5V
4741mA
VCC3V3_BMC
+3.3V
924mA
TPS71712 TPS61081TPS650006RTET
VCC1V2
+1.2V
60mA
VLED+
+19.2V
40mA
LCD BACKLIGHT
NHD-4.3-480272EF-ATXL-CTPHDMI TX
SiI9022ACNU
VCOM_BAT
1000mA
VCC1V2_XDS+1.2V38mA
VCC1V8_XDS+1.8V18.3mA
VCC3V3_XDS+3.3V365mA
SPI FLASH
IS25CD010-JNLE
COM8 CONN
DDR3 x5
MT41K512M8RH-125:E
SDRAM
MT48LC4M16A2B4
-75G
AVDDA_XPLLDVDD18+1.8V300mA
Level Translator x3
SN74AVC4T245PW
COM8 VBAT
LDO
QSPI
S25FL512SAGMFI011
SPI EPROM
N25Q128A13ESF40F
NAND FLASH
MT29F2G16ABAFAWP:F
DVDD33,VCC3V3+3.3V133mA
AUDIO CODEC
TLV320AIC3106IRGZT
EMMC16G-S100
K2G PROCESSOR
(66AK2G02)
CVDD+0.9V4654mA
DVDD_DDR+1.35V284mA
USB0 LOAD SWITCH
TPS2051BD
CPLD
XC2C64A-5VQ44C
PROCESSOR
AM1802
PROCESSOR
AM1802
CPLD
XC2C64A-5VQ44C
PROCESSOR
AM1802
VCC12V0_DC_IN
+12V
310mA
CVDD1+0.9V464mA
DCAN0 & 1
ISO1050
AUDIO CODEC
TLV320AIC3106IRGZT
NOTE: REGULATORS
DEVICES
Multiple powered
device
VCC5V0_USBx 1000mA
EN
VCC3V3
EN5V_EN
EN
VCC3V3
EN
VCC_VBUS_XDS
VCC1V8LDO2+1.8V276mA
ENPMIC_GPIO2
VDD_DDR+1.35V1175mA
TPS54429
VCC12V0
+12V
1243mA
USB1 LOAD SWITCH
TPS2051BD
DC IN
+12V
7.6A
PCIE CONNECTOR3300mA
VCC12V0_PCIE+12V2000mA
PMIC_VIO
VCC3V3_DC_INVCC5V0_DC_DC
EN
VCC3V3_DCINOVP CKT
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4 System Power Requirements
4.1 Power Distribution Diagram
Figure 43. Power Distribution Diagram
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4.2 Power Supply CalculationEnter the device active percentage of utilization (1 to 100) to obtain the total power consumption.
Table 32. Power Supply Calculation
Device Part Number% Utilization
Current Consumption inmA (Maximum)
Current Consumption inmA (Typical)
Active 12V Rail 12V RailProcessor 66AK2G02 80 480.5495648 480.5495648
XDS200_Processor AM1802BZWTD3 50 29.87481972 29.87481972BMC_Processor TM4C129XNCZADI3 80 232.9411765 232.9411765
CPLD XC2C64A-5VQ44C 50 4.360465116 4.360465116DDR3 *5 MT41K512M8RH-125:E 80 205.5612403 195.3786625SDRAM MT48LC4M16A2B4-75G 50 50.87209302 33.91472868
Ehternet PHY KSZ9031RNXCA 50 28.74972222 28.74972222Buffer *2 SN74LVC32244ZKER 80 96.89922481 87.20930233
HDMI Transmitter SiI9022A CNU 80 31.1627907 24.9302325612.288-MHz Oscillator 12.288MHZ CFPS-73I B 50 3.63372093 2.90697674432.768-kHz Oscillator AS EK-32.768KHZ-LRT 50 0.566176471 0.275
Backlight Power TPS61081DRCT 50 43.60465116 35.12596899
LCD Module NHD-4.3-480272EF-ATXL-CTP 50 7.509689922 6.298449612
QSPI Flash S25FL512SAGMFI011 50 24.2248062 24.2248062DCAN *2 IS O1050 50 1.356589147 1.356589147
Audio Codec TLV320AIC3106IRGZT 50 2.00500646 2.00500646Level Translator TWL1200ZQCR 50 11.85077519 11.85077519I2C EEPROM AT24CM01 50 0.726744186 0.726744186
Clock Generator CDCM6208V2RGZT 80 116.0573333 83.11111111Clock Synthesizer CS2000CP-CZZ 50 5.559593023 2.906976744
DAC DAC8550IBDGKT 50 0.060562016 0.060562016VCXO E6718LF 50 1.453488372 1.453488372
USB-to-UART Module CP2105 50 4.481589147 4.481589147UART Transceiver *2 MAX3232ECD 50 0.484496124 0.145348837
UART Transceiver MAX3221CPWR 50 0.161764706 0.048529412SPI EEPROM M95512-RMN6TP 50 4.84496124 4.84496124NAND Flash MT29F2G16ABAEAWP-IT:E 80 13.56589147 11.62790698
eMMC EMMC16G-S100 80 68.65064599 68.65064599SPI Flash IS 25CD010-JNLE 50 7.26744186 3.63372093
BMC I2Cx Bus Repeater *2 TCA9517DGKR 50 4.040127679 2.42248062I2C Buffer Repeater TCA9517DGKR 50 1.21124031 1.21124031
LCD Module NHD-C12832A1Z-NSW-BBW-3V3 50 5.661764706 4.852941176
COM8 Module TPS79501DCQR 50 212.2416021 212.2416021USB — 50 244.6705426 243.4593023
PCIe Connector — 50 1504.166667 1181.9444448MLB Connector — 50 56.52777778 56.52777778
DCAN Connector *2 — 50 61.11111111 61.11111111Audio Daughter Card — 80 600.003876 480.003876
MicroSD Card — 80 31.00775194 31.00775194GPIO Expander TCA9555 50 38.75968992 38.75968992
Temperature Sensor TMP102 20 0.001453488 0.001453488LEDs ×7 — 50 16.95736434 16.95736434
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Maximum MinimumTotal Current Consumption in mA 4255.397993 3714.144867Total Power Consumption in mW 51064.77591 44569.73841
4.3 Power-Up SequenceThe power-up sequence required for the processor, shown in Figure 44, is provided by the PMIC. ThePower input to the PMIC is enabled by the BMC. The BMC is powered on as soon as the board ispowered on. The firmware flashed in the BMC enables power to the PMIC.
Figure 44. Power-Up Sequence Diagram
Optical / CoaxialSelection switch
ADC_IN 0
DAC_OUT 0
Digital Audio IN
(Optical)
Digital AudioIN
(Coaxial)
Digital AudioOUT
OPAMPPower Module
DAC0Mute Switch
I2S Buffer SelectionSwitch
I2S Header
DAC1 MuteSwitch
ADC_IN 1
ADC_IN 2
ADC_IN 3
DAC_OUT 1
DAC_OUT 2
DAC_OUT 3
DAC_OUT 4
DAC_OUT 5
DAC_OUT 6
DAC_OUT 7
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5 EVM with Audio Daughter CardThe K2G Audio Daughter Card (Figure 45) allows you to prototype and develop multichannel audioapplications, such as A/V receivers, automotive amplifier systems, and mixing consoles. The AudioDaughter Card connects to the main card by way of the Audio Expansion Connector. The K2G AudioDaughter Card provides:• 8 channels of analog input• 16 channels of analog outputs• S/PDIF input (optical/coaxial)• S/PDIF output
Figure 45. K2G Audio Daughter Card
DAC x 2
Switch
I2S Header
Audio E
xpansion Header
McASP1AXR[0:3]
McASP0AXR[0:7]
ADC x 2(PCM1865)
Digital Audio Receiver(DIR9001)
McASP2AXR[5]
McASP1AXR[9] Digital Audio OUT
Coaxial RCA Connector
I2C
GPIO[0,1]
McASP0AXR[0:15]
Stereo IN (x4)3.5mm Jack
Stereo OUT (x4)3.5mm Jack
Digital Audio IN
Optical Connector
Line Driver(SN74LVC2G14)
Digital Audio IN
Coaxial RCA Connector
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5.1 K2G Audio Daughter Card Block Diagram
Figure 46. K2G Audio Daughter Card Block Diagram
J64JP1
J63J12
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5.2 EVM with Audio Daughter Card ConnectionsPerform the following procedure to connect the K2G Audio Daughter Card to the K2G general-purpose(GP) EVM, see Figure 47.
CAUTIONFollow the mechanical instructions to avoid warpage to both boards.
Mount the spacers and screws while unpacking the K2G Audio Daughter Cardfrom the package box. Without the spacers, damage may occur to both boards.
Figure 47. Connecting the K2G Audio Daughter Card
1. Mount the Audio Daughter Card onto the K2G GPEVM:• Align the pins of the Audio Daughter Card (connectors J63 and J64) with the main card
(connectors J12 and JP1), respectively. Press gently to mate the connectors at the corners.
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• Press the Audio Daughter Card connectors in the middle carefully to ensure mating at the center.
• Apply pressure on the middle and the sides evenly to ensure proper mating of the connectors.2. The board looks, as shown, after mating the K2G GP EVM and Audio Daughter Card.
Input(12 V / 5 A)
PoweredSpeakers
Switch SW1
AnalogOutput
Analog inputfrom media
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3. Powering the K2G Audio Daughter Card. The K2G Audio Daughter Card is powered from the K2G GPEVM through the expansion connectors.• After mounting the Audio Daughter Card and connecting all audio sources/speakers, connect the
12V/5A adapter to connector J3 on the main board.• Slide the switch SW1 on the GP EVM to the ON position.• Once the GP EVM has booted, it is safe to turn ON any powered speakers.
6 EVM Important NoticeRefer to the STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES.
IMPORTANT NOTICE
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