Lecture07:RISC-VISA
CSE564ComputerArchitectureSummer2017
DepartmentofComputerScienceandEngineeringYonghongYan
[email protected]/~yan
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Contents
1. RISC-VISA2. 1stageimplementaCon3. ChiselhardwareconstrucConlanguage4. PipelineimplementaCon
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Acknowledgement
• Slidesadaptedfrom– ComputerScience152:ComputerArchitectureand
Engineering,Spring2016byDr.GeorgeMichelogiannakisfromUCB
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WhatisRISC-V
• RISC-V(pronounced"risk-five”)isaISAstandard(adocument)– AnopensourceimplementaWonofareducedinstrucWonsetcompuWng(RISC)
basedinstrucWonsetarchitecture(ISA)– TherewasRISC-I,II,III,IVbefore
• MostISAs:X86,ARM,Power,MIPS,SPARC– Commerciallyprotectedbypatents– PrevenWngpracWcaleffortstoreproducethecomputersystems.
• RISC-Visopen– Permi]nganypersonorgrouptoconstructcompaWblecomputers– Useassociatedso^ware
• Theprojectwasoriginatedin2010byresearchersintheComputerScienceDivisionatUCBerkeley,butitnowhasalargenumberofcontributors.Asof2017version2oftheuserspaceISAisfixed– User-LevelISASpecificaWonv2.2– Dra^CompressedISASpecificaWonv1.79– Dra^PrivilegedISASpecificaWonv1.10
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GoalsindefiningRISC-V
• AcompletelyopenISAthatisfreelyavailabletoacademiaandindustry• ArealISAsuitablefordirectnaWvehardwareimplementaWon,notjust
simulaWonorbinarytranslaWon• AnISAthatavoids"over-architecCng"for– aparWcularmicroarchitecturestyle(e.g.,microcoded,in-order,decoupled,out-of-
order)or– implementaWontechnology(e.g.,full-custom,ASIC,FPGA),butwhichallows
efficientimplementaWoninanyofthese
• RISC-VISAincludes– AsmallbaseintegerISA,usablebyitselfasabaseforcustomizedacceleratorsor
foreducaWonalpurposes,and– OpConalstandardextensions,tosupportgeneral-purposeso^waredevelopment– OpConalcustomerextensions
• Supportfortherevised2008IEEE-754floaWng-pointstandard
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LicensefortheISAspecificaCon
• ItisaBSDOpenSourceLicense.– Thisisanon-virallicense,onlyaskingthatifyouuseit,youacknowledgethe
authors,inthiscaseUCBerkeley.– NopatentthatwouldberequiredtoimplementaRISC-V-compaWbleprocessor– Theymaybemanymicro-architecturalpatentsthatmightbeinfringedbya
parWcularRISC-VimplementaWon.• ButcannotindemnifyusersagainstISAorimplementaWonpatentsassertedbyothers
• ThegoaloftheproposedRISC-VconsorWumistomaintainandtrackpossiblepatentissuesforRISC-Vimplementors
• OpenSourceSo^wareLicense– GPL:Extensionsmustbeopensourcedwiththesamelicense(kindof)– BSD:Useitasyouwant/like(kindof)
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RISC-VISAPrinciples
• Generallykeptverysimpleandextendable• SeparatedintomulWplespecificaWons– User-LevelISAspec(computeinstrucWons)– CompressedISAspec(16-bitinstrucWons)– PrivilegedISAspec(supervisor-modeinstrucWons)– More…
• ISAsupportisgivenbyRV+word-width+extensionssupported– E.g.RV32Imeans32-bitRISC-VwithsupportfortheI
instrucWonset
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UserLevelISA
• DefinesthenormalinstrucWonsneededforcomputaWon– AmandatoryBaseintegerISA• I:IntegerinstrucCons:ALU,branches/jumps,andloads/stores• Supportformisalignedmemoryaccessismandatory
– StandardExtensions• M:IntegerMulCplicaConandDivision• A:AtomicInstrucCons• F:Single-PrecisionFloaCng-Point• D:Double-PrecisionFloaCng-Point• C:CompressedInstrucCons(16bit)
• G=IMAFD:Integerbase+fourstandardextensions– OpWonalextensions
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RISC-VISA
• Both32-bitand64-bitaddressspacevariants– RV32andRV64• Easytosubset/extendforeducaWon/research– RV32IM,RV32IMA,RV32IMAFD,RV32G
• SPEConthewebsite– www.riscv.org
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RV32ProcessorState• Programcounter(pc)
• 32x32-bitintegerregisters(x0-x31)– x0alwayscontainsa0– x1toholdthereturnaddressona
call.
• 32floaWng-point(FP)registers(f0-f31)– Eachcancontainasingle-ordouble-
precisionFPvalue(32-bitor64-bitIEEEFP)
– Isanextension
• FPstatusregister(fsr),usedforFProundingmode&excepWonreporWng
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RISC-VHybridInstrucConEncoding
• 16,32,48,64…bitslengthencoding• BaseinstrucWonset(RV32)alwayshasfixed32-bitinstrucWonslowesttwobits=112
• Allbranchesandjumpshavetargetsat16-bitgranularity(eveninbaseISAwhereallinstrucWonsarefixed32bits
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FourCoreRISC-VInstrucConFormats
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Reg.Source2 Reg.Source1
7-bitopcodefield(butlow2bits=112)
AddiConalopcodebits/immediate
DesCnaConReg.
Alignedonafour-byteboundaryinmemory.Therearevariants!Signbitofimmediatesalwaysonbit31ofinstrucCon.Registerfieldsnevermove
hqps://github.com/riscv/riscv-opcodes/blob/master/opcodes
AddiConalopcodebits
WithVariants
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Reg.Source2 Reg.Source1
7-bitopcodefield(butlow2bits=112)
AddiConalopcodebits/immediate
DesCnaConReg.
AddiConalopcodebits
Basedonthehandlingoftheimmediates
IntegerComputaConalInstrucCons(ALU)
• I-type(Immediate),allimmediatesinallinstrucConsaresignextended– ADDI:addssignextended12-bitimmediatetors1– SLTI(U):setlessthanimmediate– ANDI/ORI/XORI:LogicaloperaCons– SLLI/SRLI/SRAI:Shicsbyconstants
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I-typeinstrucConsendwithI
IntegerComputaConalInstrucCons(ALU)
• I-type(Immediate),allimmediatesinallinstrucConsaresignextended– LUI/AUIPC:loadupperimmediate/addupperimmediatetopc
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I-typeinstrucConsendwithI
• Writes20-bitimmediatetotopofdesWnaWonregister.• Usedtobuildlargeimmediates.• 12-bitimmediatesaresigned,sohavetoaccountforsignwhen
building32-bitimmediatesin2-instrucWonsequence(LUIhigh-20b,ADDIlow-12b)
IntegerComputaConalInstrucCons• R-type(Register)– rs1andrs2arethesourceregisters.rdthedesCnaCon– ADD/SUB:– SLT,SLTU:setlessthan– SRL,SLL,SRA:shiclogicalorarithmeCclecorright
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ADDIx0,x0,0
ControlTransferInstrucCons
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NOarchitecturallyvisibledelayslots• UncondiWonalJumps:PC+offsettarget– JAL:Jumpandlink,alsowritesPC+4tox1,UJ-type• Offsetscaledby1-bitle^shi^–canjumpto16-bitinstrucWonboundary(Sameforbranches)
– JALR:JumpandlinkregisterwhereImm(12bits)+rd1=target
ControlTransferInstrucCons
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NOarchitecturallyvisibledelayslots• CondiWonalBranches:SB-typeandPC+offsettarget
12-bitsignedimmediatesplitacrosstwofields
Branches,comparetworegisters,PC+(immediate<<1)target(Signedoffsetinmul0plesoftwo).Branchesdonothavedelayslot
DataFormatsandMemoryAddresses
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Dataformats:8-bBytes,16-bHalfwords,32-bwordsand64-bdoublewords
Someissues• Byteaddressing
• WordalignmentSupposethememoryisorganizedin32-bitwords.Canawordaddressbeginonlyat0,4,8,....?
0 1 2 3 4 5 6 7
MostSignificantByte
LeastSignificantByte
ByteAddresses
3 2 1 0
0 1 2 3BigEndian
LiAleEndian(RISC-V)
ISA Design • RISC-Vhas32integerregistersandcanhave32floaWng-pointregisters– Registernumber0isaconstant0– Registernumber1isthereturnaddress(linkregister)
• Thememoryisaddressedby8-bitbytes
• TheinstrucWonsmustbealignedto32-bitaddresses• LikemanyRISCdesigns,itisa"load-store"machine– TheonlyinstrucWonsthataccessmainmemoryareloadsandstores– AllarithmeWcandlogicoperaWonsoccurbetweenregisters
• RISC-Vcanloadandstore8and16-bititems,butitlacks8and16-bitarithmeWc,includingcomparison-and-branchinstrucWons
• The64-bitinstrucWonsetincludes32-bitarithmeWc
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ISA DesignforPerformance
• Featurestoincreaseacomputer'sspeed,whilereducingitscostandpowerusage– placingmost-significantbitsatafixedlocaWontospeedsign-extension,andabit-
arrangementdesignedtoreducethenumberofmulWplexersinaCPU
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ISA Design
• IntenWonallylackscondiWoncodes,andevenlacksacarrybit– TosimplifyCPUdesignsbyminimizinginteracWonsbetweeninstrucWons
• BuildscomparisonoperaWonsintoitscondiWonal-jumps
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ISA Design
• ThelackofacarrybitcomplicatesmulWple-precisionarithmeWc– GMP,MPFR
• doesnotdetectorflagmostarithmeWcerrors,includingoverflow,underflowanddividebyzero– NospecialinstrucWonsetsupportforoverflowchecksonintegerarithmeWcoperaWons.
• Mostpopularprogramminglanguagesdonotsupportchecksforintegeroverflow,partlybecausemostarchitecturesimposeasignificantrunWmepenaltytocheckforoverflowonintegerarithmeWcandpartlybecausemoduloarithmeWcissomeWmesthedesiredbehavior
– FloaWng-PointControlandStatusRegister
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ISA Design
• Lacksthe"countleadingzero"andbit-fieldoperaWonsnormallyusedtospeedso^warefloaWng-pointinapure-integerprocessor
• Nobranchdelayslot,aposiWona^erabranchinstrucWonthatcanbefilledwithaninstrucWonwhichisexecutedregardlessofwhetherthebranchistakenornot– Thisfeaturecanimproveperformanceofpipelinedprocessors,– OmiqedinRISC-VbecauseitcomplicatesbothmulWcycleCPUsandsuperscalarCPUs
• Lacksaddress-modesthat"writeback"totheregisters– Forexample,itdoesnotdoauto-incremenWng
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ISA Design
• Aloadorstorecanaddatwelve-bitsignedoffsettoaregisterthatcontainsanaddress.Afurther20bits(yieldinga32-bitaddress)canbegeneratedatanabsoluteaddress– RISC-VwasdesignedtopermitposiWon-independentcode.IthasaspecialinstrucWonto
generate20upperaddressbitsthatarerelaWvetotheprogramcounter.Thelowertwelvebitsareprovidedbynormalloads,storesandjumps
– LUI(loadupperimmediate)placestheU-immediatevalueinthetop20bitsofthedes0na0onregisterrd,fillinginthelowest12bitswithzeros
– AUIPC(addupperimmediatetopc)isusedtobuildpc-rela0veaddresses,formsa32-bitoffsetfromthe20-bitU-immediate,fillinginthelowest12bitswithzeros,addsthisoffsettothepc,thenplacestheresultinregisterrd
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ISA Design
• TheRISC-VinstrucWonsetwasdesignedforresearch,andthereforeincludesextraspacefornewinstrucWons– PlannedinstrucWonsubsetsincludesysteminstrucWons,atomicaccess,integermulWplicaWon,floaWng-
pointarithmeWc,bit-manipulaWon,decimalfloaWng-point,mulWmediaandvectorprocessing
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– ItincludesinstrucWonsfor32-bit,64-bitand128-bitintegerandfloaWng-point
– Itwasdesignedfor32-bit,64-bitand128-bitmemorysystems,with32-bitmodelsdesignedforlowerpower,64-bitforhigherperformance,and128-bitforfuturerequirements
– It'sdesignedtooperatewithhypervisors,supporWngvirtualizaWon
– ItwasdesignedtoconformtorecentfloaWng-pointstandards
CallingConvenCon
• CDatatypesandAlignment– RV32employsanILP32integermodel,whileRV64isLP64– FloaWng-pointtypesareIEEE754-2008compaWble– Allofthedatatypesarekeepednaturallyalignedwhenstoredinmemory– charisimplicitlyunsigned– InRV64,32-bittypes,suchasint,arestoredinintegerregistersaspropersignextensionsof
their32-bitvalues;thatis,bits63..31areallequal• ThisrestricWonholdsevenforunsigned32-bittypes
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CallingConvenCon
• RVGCallingConvenWon– IftheargumentstoafuncWonareconceptualizedasfieldsofaCstruct,eachwith
pointeralignment,theargumentregistersareashadowofthefirsteightpointer-wordsofthatstruct• FloaWng-pointargumentsthatarepartofunionsorarrayfieldsofstructuresarepassedin
integerregisters• FloaWng-pointargumentstovariadicfuncWons(exceptthosethatareexplicitlynamedin
theparameterlist)arepassedinintegerregisters– TheporWonoftheconceptualstructthatisnotpassedinargumentregistersis
passedonthestack• Thestackpointersppointstothefirstargumentnotpassedinaregister
– Argumentssmallerthanapointer-wordarepassedintheleast-significantbitsofargumentregisters
– WhenprimiWveargumentstwicethesizeofapointer-wordarepassedonthestack,theyarenaturallyaligned• Whentheyarepassedintheintegerregisters,theyresideinanalignedeven-oddregister
pair,withtheevenregisterholdingtheleast-significantbits– Argumentsmorethantwicethesizeofapointer-wordarepassedbyreference
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CallingConvenCon
– Thestackgrowsdownwardandthestackpointerisalwayskept16-bytealigned– ValuesarereturnedfromfuncWonsinintegerregistersv0andv1andfloaWng-point
registersfv0andfv1• FloaWng-pointvaluesarereturnedinfloaWng-pointregistersonlyiftheyareprimiWvesor
membersofastructconsisWngofonlyoneortwofloaWng-pointvalues• Otherreturnvaluesthatfitintotwopointer-wordsarereturnedinv0andv1• LargerreturnvaluesarepassedenWrelyinmemory;thecallerallocatesthismemoryregion
andpassesapointertoitasanimplicitfirstparametertothecallee
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Socware
• TheRISC-VwebsitehasaspecificaWonforuser-modeinstrucWons,adra^forprivilegedISAspecificaWonandadra^forcompressedISAspecificaWon
• ItalsoincludesthefilesofsixCPUdesigns,the64-bitsuperscalar"Rocket"andfive"Sodor"CPUs
• Theso^wareincludesadesigncompiler,Chisel,whichisabletoreducethedesignstoVerilogforuseindevices
• ThewebsiteincludesverificaWondatafortesWngcoreimplementaWons• AvailableRISC-Vso^wareincludesaGNUCompilerCollecWon(GCC)toolchain(with
GDB,thedebugger),anLLVMtoolchain,asimulator("Spike")andthestandardsimulatorQEMU
• OperaWngsystemssupportexistsforLinux,butthesupervisor-modeinstrucWonsarenotstandardizedatthisWme
• ThereisalsoaJavaScriptISAsimulatortorunaRISC-VLinuxsystemonawebbrowser
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ImplementaCons
• TheRISC-VISAhasbeendesignedtoresultinfaster,less-expensive,smaller,andless-power-hungryelectronics.
• ItiscarefullydesignednottomakeassumpWonsaboutthestructureofthecomputersonwhichitruns.– ValidaWngthis,theUCBSodorcoreswereimplementedasdifferenttypesofcomputers
• RISC-Visdesignedtobeextensiblefroma32-bitbarebonesintegercoresuitableforasmallembeddedprocessorto64or128-bitsuperandcloudcomputerswithstandardandspecialpurposeextensions.– IthasbeentestedinafastpipelinedsilicondesignwiththeopenRocketSoC.
• TheUCBprocessordesignsthatimplementRISC-VareimplementedusingChisel,anopen-sourcehardwareconstrucWonlanguagethatisaspecializeddialectofScala.– 'Chisel'isanabbreviaWon:ConstrucWngHardwareInaScalaEmbeddedLanguage
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ImplementaCons
• TheIndianInsWtuteofTechnologyMadrasisdevelopingsixRISC-Vopen-sourceCPUdesigns(SHAKTI)forsixdisWnctusages,fromasmall32-bitCPUfortheInternetofThingstolarge,64-bitCPUsdesignedforwarehouse-scalecomputersbasedonRapidIOandHybridMemoryCubetechnologies.
• Bluespec,Inc.,asemiconductortoolscompany,isexploringRISC-Vasapossibleproduct.
• lowRISCisanonprofitprojectthataimstoimplementafullyopen-sourceSoCbasedonthe64-BitRISC-VISA.
• TheplannedmulWmediasetmayincludeageneral-purposemixed-precisionvectorprocessorsimilartotheresearchproject“Hwacha.”
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