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Memory
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Memory
• Memorystructures arecritical to anylarge, complexdigital design.
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Memory
• Memory structures are crucial in digital design.– ROM, PROM, EPROM, RAM, SRAM, (S)DRAM, RDRAM,..
• All memory structures have an address bus and a data bus– Possibly other control signals to control output etc.
• E.g. 4 Bit Address bus with 5 Bit Data Bus
ADDR<3:0> DOUT<4:0>
24 x 5 ROM/RAM
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Memory
• Internal organisation– ‘Lookup Table of values’
– For each address there is acorresponding data output
ADDR<3:0> DOUT<4:0>
0000
0001
1111
ADDR
10101
11111
11001
DOUT
16 possible address valueswith 5 bit output(16 x 5 ROM)
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Memory
• Usually consider a repository for data or program code.
• Indexing of the data and ability to both read and writesuggests a mailslot analogy.– Byte = 8 bits
– Word = whatever data widthyou’re using
• But,
• especially when considering‘read only’,
• ‘Lookup Table’ ≡ ‘Truth Table”
0000
0001
1111
ADDR
10101
11111
11001
DOUT
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• k-input, n-output Read Only Memory (ROM) could be– 2k x n element lookup table
– k-input, n-output truth table
– k-input, n-output combinatorial logic block– DOUT(0) = ADDR(3).ADDR(2).ADDR(1).ADDR(0) + ADDR(3).ADDR(2)..
• Any k-input, n-output combinatorial block is available
• Benefits– Configure once PCB complete
– Flatten complex logic hierarchy to faster design
– Simple to create using high level language - no minimisation.
ROM
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ROM - VHDL
• VHDL Code
• Various forms of coding possible– E.g. if addr = “0000” then …
– Or case addr is, when “0000” => (better)
• A neater approach is to use a table of constants– See next slide !
• Could also easily add in further control signals etc.
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ROM - VHDLuse ieee.numeric_std.all;
architecture BEHAVIOR of ROM is
type romtable is array (0 to 15) of std_logic_vector(4 downto 0);
constant romdata : romtable :=
(“10101”,
“11111”, etc.)
);
begin
process (ADDR)
begin
DOUT <= ROMDATA (to_integer(unsigned(ADDR)));
end process;
end BEHAVIOR;
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ROM - VHDL
• Result after synthesis is simply a combinatorial logicimplementation of the ROM– i.e. DOUT(0) = ADDR(0) + ADDR(1) …
• In practical terms, memory structures can be implementedon Silicon much more efficiently by use of technologyspecific implementation– E.g. I need a 16 x 4 ROM with the values ….
– As noted above - use high level language to calculate the values.
– For simulation/ small structures the above approach is feasible !
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ROM - Internal Structure
• Historically
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1111
ROM - Internal Structure
• Why not just wires?
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ROM - Internal Structure
• Modern structure.
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ROM - Internal Structure
• The problem of decoding– A k-input ROM requires a k-to-2k decoder
– Such a decoder requires 2k, k-input NAND gates, k buffers andk inverters, each with fanout of 2k-1.
– 1Mbyte memory would obviously require over 1 million 20input NAND gates, and 40 buffers/inverters with fanout of half amillion, or a long (delay ridden) buffer chain.
– Ugh.
• And just how does such a beast fit into the system timing.
• Answer these questions when dealing with RAM.
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Types of ROM - mask ROM
• ‘Connections’ between word and bit lines are made byaltering one or more interconnect masks in the fabricationprocess.
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Types of ROM - mask ROM -2
• Ideal for high volume, low cost production.
• Turn around on mask production and NRE (non recurringengineering) costs make them pointless for prototyping.
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Types of ROM - PROM
• ‘Connections’ between word and bit lines destroyed byvaporising fusible links.
• Bipolar transistors typically used in these devices, sorelatively high power, but fast– nothing much faster than a wire in a microelectronic circuit!
• OTP (one time programmable) - obviously.
• Cheaper than EPROM or EEPROM and so often used inshort production runs, or where the contents of the ROMmay be altered right up to product launch but then set instone.
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Types of ROM - PROM - 2
• Technology can be employed in the look up tables / fusemaps of OTP PLDs or, more rarely FPGAs.
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Types of ROM - EPROM
• EPROM: Erasable, Programmable, Read Only Memory
• EEPROM: Electrically Erasable, Programmable, ReadOnly Memory
• flash EEPROM: a hybrid of the two.
• typically today ‘EEPROM’ and ‘flash EEPROM’ are bothapplied to flash EEPROM technology.
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Types of ROM - EPROM - 2
• Non volatile - 70% of charge remains after 10 years
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2020
Types of ROM - EPROM - 3
Device EPROM EEPROM flash EEPROMChannel-FloatingGate
100 nm 10 nm 10 nm
Programme AvalancheBreakdown
Fowler-Nordheimtunnelling
AvalancheBreakdown
Programming Time micro s milli s micro sErasure UV light Fowler-Nordheim
tunnellingFowler-Nordheimtunnelling
Erasure Time kilo s milli s / word milli s / wordProgramme/ErasureCycles
100 10 000 10 000
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E/EPROM Applications
• Firmware for embedded systems– Microcontrollers - staggeringly huge market…
– modems, graphics cards, etc.
• Embedded OS software for palmtops, set-top boxes,…
• Bootstrap loaders
• Relatively cheap to produce.
• As markets expand, economies of scale make cheaper.
• OTP devices are now usually EPROMs without quartzlids.
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E/EPROM Applications - 2
• Technology is often employed in look up tables / fusemaps of PLDs or FPGAs
• Both PROMs and EEPROMs are readily available from16 kbyte to 8 Mbyte configurations.
• Multiple flash EEPROMs can be packaged into flash cardsolid state memories.– Can lever 40 mp3 encoded CD tracks into the largest sold today.
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Random Access Memory
Static, Dynamic,Synchronous
and Asynchronous
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RAM - Overview
• RAM (random access memory)– read and write to any location given a valid address
– Historically term had more meaning when tape drives andpunched cards were used for mass storage.
– Today hard disks are ‘almost’ random, and modern RAM is ‘notcompletely’ random.
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RAM - Overview
• SRAM (static)– Formed from internal latches - 6 transistors per bit.
– Latch will store information as long as power supplied.
– Inherently synchronous.
– Integrable.
– Fast , 12 ns access time direct from Farnell
– Fast, 4 ns access time in ECL from Cypress
– On chip caches, off chip caches, HD caches,…
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RAM - Overview
• DRAM (dynamic)– Storage of charge on a capacitor gated by a transistor
– 1 ish transistor per bit.
– High packing density, large cheap memory,
– Cheap + economies of scale = very cheap. Commodity item.
– Less integrable
– Seriously faster than hard disk, 70 ns direct from Farnell
– Main memory
– These days most DRAM is also synchronous SDRAM
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RAM - Overview
• SDRAM today
• PC100, k=64, 64 bit datapath at 100MHz– How many bytes per second throughput / bandwidth?
– How many ns per clock cycle at 100MHz ?
– Didn’t we just say it took 70 ns to supply a byte from Farnell ?
• PC133, k=64, 64 bit datapath at 133MHz– How many bytes per second throughput / bandwidth ?
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RAM - Trends
• RDRAM (Rambus DRAM)
• PC600, k=16, at 266MHz, clocked on each edge!
• PC800, k=16, at 400MHz, clocked on each edge!– Bandwidths ?
• History– Nintendo 64, Intel i820 chipset (bleugh), Playstation 2, not the
Nintendo Dolphin, and practically no-one else.
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RAM - Trends
• RDRAM Benefits– Fewer pins, so smaller PCB
– Internal guts does good look-ahead for streamed memory access.
• But– Proprietary ($$)
– However more difficult initial design due to high speed
– Streamed memory access ≠ random access memory
– Big heatsinks (not really built for your pretty Mac Cube)
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RAM - Trends
• DDRDRAM (Double data rate DRAM)
• PC1600, k=64, at 100MHz, clocked on each edge!
• PC2100, k=64, at 133MHz, clocked on each edge!
• Benefits– Cheaper
– Lower power consumption
– Better for truly random access (but not streamed)
– Already used in graphics cards
– AMD and almost everyone else apart from Intel .
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RAM - interface
– Unless specifically designed(dual port), memory cannotbe read from and written to atthe same time.
– Instead of read and write, user/^w (or write enable) andchip select signals.
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Where are we ?
• VHDL
• VHDL– Combinatorial logic
– Counters, registers, state machines
• Memory– ROM, SRAM, DRAM
• Arithmetic Logic Unit (ALU)
• Datapaths
• Sequencing and Control
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async SRAM - internal structure
• Single SRAM cell
BUG!!
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async SRAM - internal structure
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async SRAM - 16 ××××1
• The wrong way
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async SRAM - 16 ××××1
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RAM - timing
• Read process– Choose desired word by applying address
– Ensure r/^w high
– Push chip select high and wait for a clock edge
• Read timing (CY7C102A, 256K ×4 Static RAM)– tAA, Address to valid data (12ns max)
– tOHA, Data hold from address change (3 ns min)
– tACS, chip select to data valid (12 ns max)
– tCSLZ, chip select to low impedance (3 ns min)
– tCSHZ, chip select to high impedance (6 ns max)
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RAM - timing
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RAM - timing
• Write process– Choose desired word slot by applying address to address lines
– Push r/^w low
– Push chip select low and apply data before it’s raised high again.
• Write timing (CY7C102A)– tAS, address set to write start (0 ns min)
– tCSW, chip enable pulse length (10 ns min)
– tDS, data setup to wite end (7 ns min)
– tDH, data hold to write end (0 ns min)
• all this assuming CS controlled write
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RAM - timing
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RAM - timing
• Read process similar to ROMs
• Latches - from schematic obviously no clock
• But aren’t all our devices supposed to be synchronous ?
– Edge triggered flip-flopswould double silicon area– Designers just accept thehassle in real systems.
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4242
synchronous SRAM - collaring/glue
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4343
sync SRAM
• Follow the same line as Wakerly ‘Digital DesignPrinciples and Practices’ - revise from §10.3
• Chapter 6 of Mano & Kine ‘Logic and Computer DesignFundamentals’ is fine as well.
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4444
sync SRAM - read operations
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4545
sync SRAM - write operations
Problem ?
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4646
sync SRAM - write operations
• Address delays are naturally longer thandata delays.
• Need to add delay sections to keep thetiming correct.
• Perfectly possible to do but in mostmemory systems not needed - two stageoperation is usually helpful for the rest ofthe system.
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4747
sync SRAM - write operations
Another problem !
Need two cyclesper memory access
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4848
sync SRAM - write operations
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4949
sync SRAM - write operations
?
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5050
sync SRAM - write operations
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5151
sync SRAM - write operations
• ZBT SRAM (zero burst turnaround) shows an alternatemethod of solving the problem of the address needing tohang around for two clock cycles.
• Store it in another register– Downside, waste of floorplan area…..
– Upside, can pipeline writes or interleave reads and writes.
• Wakerly - p865
• Is it worth it ?– IBM POWER architecture.
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5252
sync SRAM - 1M x 8 bits
How do we link multiple memories together ?
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5353
sync SRAM - 1M x 16 bits
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5454
sync SRAM - 4M x 8 bits
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5555
DRAM
• Memory element is entirely different in detail
• Destructive Read
• Leakage
• Need for ‘analogue’ rowlatch circuitry to amplifysense signal and feedbackrefresh.
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5656
DRAM - overall structure
P.S. No Clock !
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5757
DRAM - read cycle
Address to row address registerput row data into row latch
Pull out bit from row and send to output
Recycle row latch back to row
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5858
DRAM - write cycle
Address to row address registerput row data into row latch
Supply data bit and enable writing
Read bit and refresh
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5959
DRAM - refresh cycle
Address to row address registerput row data into row latch Recycle row latch back to row
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6060
DRAM - refresh cycle
• 4Mx4bit DRAM requires each bit to be refreshed at leastevery 64 ms
• 4096 rows (1024 columns) so 4096 refreshes in 64 ms
• Available time therefore 15.625 µs
• Actual refresh time is 60 ns per row.
• Less than 1%, so negligible if distributed
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6161
DRAM - refresh cycle
• Refresh cycle shown needs an external DRAM controllerto step through the rows and supply refresh signals atappropriate times
• More modern method is ‘CAS before RAS’ refresh(memory uses the otherwise unused CAS before RASinput to initiate a refresh cycle) which is associated withan internal refresh address counter. DRAM controlleronly chooses refresh times.
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DRAM - other types
• EDO DRAM– Still used in older machines
– Instead of output tri-state being controlled by CAS linebecoming active on read cycle, an output enable signal is used.
– CAS still controls output timing, OE controls output tri-state
– Burst mode reads can happen much more quickly as no Z statebetween each one (extended data out)
• SDRAM– Discussed before, collar some DRAM with synchronisers as in
SRAM above, and then play pipelining tricks internally.