May 16, 2000 1
2004 Edition 2
USB Hub Designs
USB Hub Designs
John GarneyJohn GarneyHub Working Group Chair, Intel CorporationHub Working Group Chair, Intel Corporation
Schumann RafizadehSchumann RafizadehVP Engineering, Yi Shi TongVP Engineering, Yi Shi Tong
John GarneyJohn GarneyHub Working Group Chair, Intel CorporationHub Working Group Chair, Intel Corporation
Schumann RafizadehSchumann RafizadehVP Engineering, Yi Shi TongVP Engineering, Yi Shi Tong
May 16, 2000 3
Hub AdditionsHub Additions
Requirements and ArchitectureRequirements and Architecture– Additions to USB1.1Additions to USB1.1
Transaction TranslatorTransaction Translator Bulk/Control Transaction HandlingBulk/Control Transaction Handling Isochronous/Interrupt Transaction HandlingIsochronous/Interrupt Transaction Handling
Additions to Chapter 11Additions to Chapter 11
May 16, 2000 4
Requirements:Requirements:
Provide high-speed expansionProvide high-speed expansion Isolate full/low-speed from high-speedIsolate full/low-speed from high-speed
– Avoid lower speed impact on HS, i.e., LS impact on FSAvoid lower speed impact on HS, i.e., LS impact on FS
All USB2.0 Hub Ports support HS/FS/LSAll USB2.0 Hub Ports support HS/FS/LS
Optional: standardized port indicators (LEDs)Optional: standardized port indicators (LEDs)
May 16, 2000 5
System SWSystem SW
Client DriverClient Driver Client DriverClient Driver
USB 1.1 USB 1.1 DeviceDevice
USB 1.1 USB 1.1 DeviceDevice
HS HubHS HubHS HubHS Hub
USB 1.1 HubUSB 1.1 Hub
USB 1.1 USB 1.1 DeviceDevice
USB 1.1 USB 1.1 DeviceDevice
HS DeviceHS DeviceHS DeviceHS Device
USB 2.0 HostUSB 2.0 HostControllerController
USB 2.0 HostUSB 2.0 HostControllerController
Full/Low SpeedFull/Low Speed
High Speed OnlyHigh Speed Only
(2 x 12Mb/s(2 x 12Mb/sCapacity)Capacity)
Hub In High Speed SystemHub In High Speed System
Hub provides high-speed expansion (ala 1.1 hub)Hub provides high-speed expansion (ala 1.1 hub) Hub provides additional classic bus(es)Hub provides additional classic bus(es)
– Same total number of devices per USB2.0 Host Controller (e.g. 127)Same total number of devices per USB2.0 Host Controller (e.g. 127) Greater end user value than classic hubGreater end user value than classic hub
– Performance, expansion and ease of usePerformance, expansion and ease of use Hub is user selected device (not required for all systems)Hub is user selected device (not required for all systems)
May 16, 2000 6
Reuse Classic Hub
Reuse Classic Hub
Design Knowledge
Design KnowledgeReuse Classic Hub
Reuse Classic Hub
Design Knowledge
Design Knowledge
HS/Classic HS/Classic Hub StateHub StateMachineMachine
HS/Classic HS/Classic Hub StateHub StateMachineMachine
HS/Classic HS/Classic HubHub
RepeaterRepeater
HS/Classic HS/Classic HubHub
RepeaterRepeater
HS/Classic HS/Classic HubHub
ControllerController
HS/Classic HS/Classic HubHub
ControllerController
High Speed OnlyHigh Speed Only
PortPort PortPort PortPort
PortPort
Hub “Classic Pieces”Hub “Classic Pieces”
RepeaterRepeater– High speed signalingHigh speed signaling
Also, FS/LS signaling for 1.1 compatibilityAlso, FS/LS signaling for 1.1 compatibility– ReclockingReclocking
State MachineState Machine– HS termination sequencingHS termination sequencing
HS Detect, Reset, Suspend, ResumeHS Detect, Reset, Suspend, Resume Hub ControllerHub Controller
– Respond to hub device class requests/eventsRespond to hub device class requests/events
May 16, 2000 7
Hub ArchitectureHub Architecture
Same as classic hub:Same as classic hub:– High & full/low-speed repeaters, determined by upstream facing linkHigh & full/low-speed repeaters, determined by upstream facing link– Hub controllerHub controller– No different then classic USB besides high-speed signalingNo different then classic USB besides high-speed signaling
Minor changes from classic hub:Minor changes from classic hub:– Hub state machine (HS detect, HS termination transitions, test mode)Hub state machine (HS detect, HS termination transitions, test mode)
New in hub:New in hub:– Transaction TranslatorTransaction Translator– Routing logicRouting logic
HS/Classic HS/Classic HubHub
ControllerController
HS/Classic HS/Classic HubHub
ControllerController
TransactionTransactionTranslatorTranslator
TransactionTransactionTranslatorTranslator
Full/LowFull/LowSpeedSpeed
High Speed OnlyHigh Speed Only
. . . . .. . . . .
HS/Classic HS/Classic Hub StateHub StateMachineMachine
HS/Classic HS/Classic Hub StateHub StateMachineMachine
Routing LogicRouting Logic
PortPort PortPort PortPort
PortPort
HS/Classic HS/Classic HubHub
RepeaterRepeater
HS/Classic HS/Classic HubHub
RepeaterRepeater
May 16, 2000 8
Routing LogicRouting Logic Routing LogicRouting Logic
TransactionTransactionTranslatorTranslator
TransactionTransactionTranslatorTranslatorFull/LowFull/Low
SpeedSpeed
High Speed OnlyHigh Speed OnlyPortPort
Repeater, Controller, ...Repeater, Controller, ...Repeater, Controller, ...Repeater, Controller, ...
PortPort PortPort PortPort
Hub New PiecesHub New Pieces
Port Routing LogicPort Routing Logic– Controllable electrical connection between:Controllable electrical connection between:
Full/Low (Transaction Translator), orFull/Low (Transaction Translator), or High-Speed (Repeater)High-Speed (Repeater)
– Route done once per device resetRoute done once per device reset Transaction TranslatorTransaction Translator
– Major addition for USB 2.0Major addition for USB 2.0– Uses split transaction protocol HC supportUses split transaction protocol HC support
. . . . .. . . . .
May 16, 2000 9
Host Controller / TT InteractionsHost Controller / TT Interactions
HostHostHostHost
DeviceDeviceDeviceDevice
TTTTTTTTXX22
TT buffers full/low speed transaction information (X) locallyTT buffers full/low speed transaction information (X) locally
1 – SPLIT-s, OUT, DATAx1 – SPLIT-s, OUT, DATAx(Start-split)(Start-split)
Host Controller issues start-split transaction to TTHost Controller issues start-split transaction to TT
TTTTTTTT RR
4 - ...,ACK4 - ...,ACK
TT buffers full/low speed transaction results (R) locallyTT buffers full/low speed transaction results (R) locally
3 - OUT, DATAx, ...3 - OUT, DATAx, ...
TT issues full/low speed transaction on downstream busTT issues full/low speed transaction on downstream bus
6 - …,ACK6 - …,ACK
TT responds with resultsTT responds with results
InterruptInterruptOutOut
ExampleExample
5 – SPLIT-c, OUT, …5 – SPLIT-c, OUT, …(Complete-split)(Complete-split)
Host Controller issues complete-split transaction to TTHost Controller issues complete-split transaction to TT
May 16, 2000 10
Transaction Translator Overview Transaction Translator Overview
Two separate portions to Transaction TranslatorTwo separate portions to Transaction Translator– Bulk/Control supportBulk/Control support– Interrupt/Isochronous supportInterrupt/Isochronous support
Bulk/Control uses USB flow control to make progressBulk/Control uses USB flow control to make progress– PING not usedPING not used
Interrupt/Isochronous uses a scheduled full/low speed transaction “pipeline”Interrupt/Isochronous uses a scheduled full/low speed transaction “pipeline” Separate buffers are used for each TT portionSeparate buffers are used for each TT portion
Transaction TranslatorTransaction TranslatorTransaction TranslatorTransaction Translator
Bulk &ControlBulk &Control
Interrupt &IsochronousInterrupt &
Isochronous
May 16, 2000 11
TT Bulk / ControlTT Bulk / Control
TT buffers 2 or more bulk/control transactionsTT buffers 2 or more bulk/control transactions TT issues full/low speed transaction when no periodicTT issues full/low speed transaction when no periodic
transactions pendingtransactions pending Host controller issues split transactions to TTHost controller issues split transactions to TT
– Allows starting/completing full/low-speed transactions each microframeAllows starting/completing full/low-speed transactions each microframe– Normal approach of “bandwidth reclamation” is usedNormal approach of “bandwidth reclamation” is used– Tries to issue HS start-split; if successful, next attempt does complete-splitTries to issue HS start-split; if successful, next attempt does complete-split
TTTTTTTT
Bulk/Ctrl #1Bulk/Ctrl #1 Bulk/Ctrl #2Bulk/Ctrl #2
High Speed Start-/Complete-SplitHigh Speed Start-/Complete-Split
Full/Low Speed TransactionFull/Low Speed Transaction
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TT Int. / Isoch. PipelineTT Int. / Isoch. Pipeline
Host software budgets when full/low-speed transaction will runHost software budgets when full/low-speed transaction will run Host schedules start-split before “earliest” start timeHost schedules start-split before “earliest” start time Host schedules complete-split at “latest” finish timesHost schedules complete-split at “latest” finish times Scheduling accounts for variation due to bit-stuffingScheduling accounts for variation due to bit-stuffing
and timeouts, etc.and timeouts, etc.
TTTTTTTT
High Speed Start-SplitHigh Speed Start-Split High Speed Complete-SplitHigh Speed Complete-Split
Start-splitStart-splitFIFOFIFO
Start-splitStart-splitFIFOFIFO
Complete-splitComplete-splitFIFOFIFO
Complete-splitComplete-splitFIFOFIFO
StartStartHandlerHandler
StartStartHandlerHandler
CompleteCompleteHandlerHandler
CompleteCompleteHandlerHandler
Full/LowFull/LowHandlerHandlerFull/LowFull/LowHandlerHandler
May 16, 2000 13
TTTTTTTT
Start-splitStart-splitFIFOFIFO
Start-splitStart-splitFIFOFIFO
Complete-splitComplete-splitFIFOFIFO
Complete-splitComplete-splitFIFOFIFO
Full/LowFull/LowHandlerHandlerFull/LowFull/LowHandlerHandler
StartStartHandlerHandler
StartStartHandlerHandler
CompleteCompleteHandlerHandler
CompleteCompleteHandlerHandler
XX22
TT buffers full/low speed transaction information locally
1 – SPLIT-s, OUT, DATAx1 – SPLIT-s, OUT, DATAx
Host Controller issues start-split transaction to TT
3 - OUT, DATAx, ...3 - OUT, DATAx, ...
TT issues full/low speed transaction on downstream bus
5 – SPLIT-c, OUT, ...5 – SPLIT-c, OUT, ...
Host Controller issues complete-split transaction to TT
6 - …,ACK6 - …,ACK
TT responds with results
Example: Int. OUT Split Trans.Example: Int. OUT Split Trans.
RR
4 - ...,ACK4 - ...,ACK
TT buffers full/low speed transaction results locally
Start-splitStart-splitFIFOFIFO
Start-splitStart-splitFIFOFIFO
May 16, 2000 14
Hub Cost / Complexity EstimateHub Cost / Complexity Estimate
Classic Hub + new thingsClassic Hub + new things– Classic Hub - implementation dependent, but knowable baselineClassic Hub - implementation dependent, but knowable baseline– New thingsNew things
SignalingSignaling Required for any High-Speed deviceRequired for any High-Speed device
Logic (routing, TT)Logic (routing, TT) RAM (buffer space, transaction pipeline)RAM (buffer space, transaction pipeline)
Total (approximate)Total (approximate)– 40KGates + 1800 Bytes with 4 downstream ports40KGates + 1800 Bytes with 4 downstream ports– 28KGates + (3KG * # of downstream ports) + 1800 Bytes28KGates + (3KG * # of downstream ports) + 1800 Bytes
TT FIFOsTT FIFOsTT FIFOsTT FIFOs
TT LogicTT LogicTT LogicTT Logic
Port
High-Speed “Classic Hub”High-Speed “Classic Hub”High-Speed “Classic Hub”High-Speed “Classic Hub”
Port Port Port
Routing LogicRouting Logic
May 16, 2000 15
USB2.0 HubAdditions SummaryUSB2.0 HubAdditions Summary
Hub Ports Support all Speeds (High/Full/Low)Hub Ports Support all Speeds (High/Full/Low)– Isolation of High and Full/Low Speeds via TTIsolation of High and Full/Low Speeds via TT
Simultaneous High and Full/Low-Speed TransactionsSimultaneous High and Full/Low-Speed Transactions– Full/Low Speed (12Mb/s) bus per TTFull/Low Speed (12Mb/s) bus per TT
Can be TT per hub or TT per portCan be TT per hub or TT per port
TT Internals OverviewTT Internals Overview– Bulk/Control bufferingBulk/Control buffering– Interrupt/Isochronous scheduled pipelineInterrupt/Isochronous scheduled pipeline
January 10, 2004 16
Mega Hub DesignsMega Hub Designs
ArchitectureArchitecture– Cascaded Hub DesignCascaded Hub Design– Interleaved Hub DesignInterleaved Hub Design
January 10, 2004 17
Mega Hub DesignsMega Hub Designs
Cascaded Mega HubCascaded Mega Hub
Host and Devices use the same TT & Buffers Host and Devices use the same TT & Buffers
January 10, 2004 18
Mega Hub DesignsMega Hub Designs
Interleaved Mega HubInterleaved Mega Hub
Host and Devices use different TT & Buffers Host and Devices use different TT & Buffers
January 10, 2004 19
Mega Hub DesignsMega Hub Designs
Advantages of Cascaded HubsAdvantages of Cascaded Hubs– Ease of design and manufactureEase of design and manufacture– Low CostLow Cost
Advantages of Interleaved HubsAdvantages of Interleaved Hubs– High Performance High Performance – Higher CapacityHigher Capacity
January 10, 2004 20
Flash Storage StrategyFlash Storage Strategy
January 10, 2004 21
Flash Storage StrategyFlash Storage Strategy
Current Current off-the-shelfoff-the-shelf Flash Storage disadvantages; Flash Storage disadvantages;
– Lower reliabilityLower reliability– Lower capacityLower capacity– Lower bandwidthLower bandwidth– Have lower performance Have lower performance
Advantages;Advantages;
– higher portabilityhigher portability– higher availability higher availability – lower power consumptionlower power consumption– wider applications (mobile phones, cameras, tablets, hand-held gadgets etc.)wider applications (mobile phones, cameras, tablets, hand-held gadgets etc.)– Lower cost Lower cost
The Flash Storage Strategy provides a roadmap of innovations that expand the advantages of Flash Storage The Flash Storage Strategy provides a roadmap of innovations that expand the advantages of Flash Storage devices and eliminate their restrictions and disadvantages.devices and eliminate their restrictions and disadvantages.
This roadmap includes, Wear-out detection (Patent xxx), Flash Array (Patent xxx), Flash Hub (Patent xxx) and Flash This roadmap includes, Wear-out detection (Patent xxx), Flash Array (Patent xxx), Flash Hub (Patent xxx) and Flash Cluster.Cluster.
January 10, 2004 22
Flash Storage Strategy - TestingFlash Storage Strategy - Testing
Device TestingDevice Testing– Flash Array/Flash RAID Flash Array/Flash RAID – HUBHUB– ClusterCluster
Range USB 2.0 & USB 3.0 Testing Range USB 2.0 & USB 3.0 Testing – Performance GoalsPerformance Goals
USB 2.0 up to 50 MB/SecUSB 2.0 up to 50 MB/Sec USB 3.0 up to 500 MB/SecUSB 3.0 up to 500 MB/Sec
– Capacity Capacity Dependant on Class and number of moculesDependant on Class and number of mocules
January 10, 2004 23
Flash Storage Strategy - TestingFlash Storage Strategy - Testing
Speed
Capacity
USB 2.0
USB 3.0
50MB/SEC